rfconnext pmtl ddr applications
DESCRIPTION
Application of PMTL(tm) technology to improve the Transfer rate of DDR DIMM memory modules...TRANSCRIPT
Application of PMTL™/VMTL™ for Improving DDR Signal Integrity, Skew and Jitter
Jamal S. Izadian, Ph.D.RFCONNEXT, Inc.
1091 Lio Court, San Jose CA 951201091 Lio Court, San Jose CA [email protected]
408-981-3700October 8, 2009
www.rfconnext.com
Advancing the High Speed Interconnect Ecosystem™ …
Mission for DDR DIMM
• Embedding PMTL™/VMTL™ into Memory Modules to Improve Cost/Performance Ratio
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
2
Ratio
Product Improvement Strategy for DDR2 Memory Modules
• Improve Overall Signal Integrity • Embed PMTL™/VMTL™ technology to
– Increase Velocity of Signal Propagation– Reduce Line Delay– Reduce effective K and Loss Tangent, – Reduce Insertion Loss
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
3
– Reduce Insertion Loss– Improve Power Consumption– Improve the Frequency Response of the Critical
Transmission Lines, which sharpens the rise time and opens up the Eye
– Eliminate Cross Talk– Using the same PCB process and design rules
How to use PMTL™ technology to improve the performance of
DDR2 Memory Modules
(in next few slides, the lines with (in next few slides, the lines with most impact, i.e., TL5b, are shown)
Improve Primary Traces of DDR2
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
5
Improve Secondary Traces of DDR2
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
6
Improve/Reduce DDR2 Stack
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
7
Improving the Transmission LinesLow Load, Long Length
• Reduce the effective K, LT• Increasing the Velocity of Propagation• Reducing the overall Delay• Improving the Skew variation % as a function of the overall
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
8
delay– For Global Lines like TL5b L=76.2mm (L9)– Regional Lines like TL7 L=7.11mm (L3)– Local Microstrip Line TL1=6.35mm and TL8 = 5.6mm,
(L1 and L12)
Improving the Transmission LinesHigh Load, Short Length
• Reduce the effective K, LT• Increasing the Velocity of Propagation• Reducing the overall Delay• Improving the Skew variation % as a function of the overall
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
9
• Improving the Skew variation % as a function of the overall delay– For Global Lines like TL5a L=51mm (L10)– Regional Lines like TL6 L=14.6mm (L3)– Local Microstrip Line TL1=6.35mm and TL8 = 5.46mm,
(L1 and L12)
Example, Global Line TL5b Before PMTL™
• TL5b, L = 76.2mm, Stripline, K = 4.35 LT=0.025• L9• VOP = c/sqrt(K) = 3E8/sqrt(4.35)=1.44e8m/s• Delay = L / VOP = 0.53ns
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
10
• Impedance Match = 45 Ohm, can be increased• Return Loss, improved• Insertion Loss, Over Frequency improved• Reduce Power Loss, by lowering IL• Bandwidth, thus Eye Diagram, 5GHz (5/.677) =
7Harmonics
Example, Global Line TL5b After PMTL™
• TL5b, L = 76.2mm, 30% reduction– Effective K ~= 3, – Effective LT ~=0.01 73
• VOP = improve by +20% min 1.73e8m/s• Delay = reduce by 17% min 0.44ns
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
11
• Delay = reduce by 17% min 0.44ns• Impedance Match, increase impedance to 60Ohm• Improve Return Loss• Insertion Loss slope 0.0173/0.025 =.87 over bandwidth• Reduce Power Consumption, due to lower loss slope• Increase Bandwidth, thus Open the Eye Diagram,
20GHz/.677GHz= 29 Harmonics, 29/7 = 4x
Product Improvement Strategy for DDR3 Memory Modules
• Improve Overall Signal Integrity for 800MHz, CLK, 1600MT/s
• Embed PMTL™/VMTL™ technology to – Increase Velocity of Signal Propagation– Reduce Line Delay– Reduce effective K and Loss Tangent,
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
12
– Reduce effective K and Loss Tangent, – Reduce Insertion Loss– Improve Power Consumption– Improve the Frequency Response of the Critical
Transmission Lines, which sharpens the rise time and opens up the Eye
– Eliminate Cross Talk– Using the same PCB process and design rules
Typical DDR3
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
13
DDR3 CLK Net Wiring (Fly By)
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
14
DDR3 Control Net
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
15
DDR3 Address Net
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
16
DDR3 Data Net
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
17
Possible DDR3 Stack
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
18
Table Of Comparison DDR2/3 Before and After PMTL/VMTL
DDR 2/DDR3 FRC % Change Comment
Item units
FR4 K ratio 4.53 3 -30
Material Loss Tagnet 0.025 0.0173 -30
VOP m/s 1.44 1.73 20
Length mm 76.2 76.2 0
Delay ns 0.53 0.44 -17
Bandwidth GHz 2.5 25 900 10x, at least
Data Rate Gbps 5 50 900 10x, at least
Num of Harmonics ratio 4 37 900 10x at least
wrt 667MHz Clk
Nom Freq for WVL GHz 2.5 2.5 0
Lamda_0 mm 120 120 0
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
19
Lamda_0 mm 120 120 0
L/Lambda_0 ratio 0.635 0.635 0
Power Loss W, 1W Ref 0.487 0.313 -55
Per Lambda_0
Power Loss W, 1W Ref 0.654 0.212 -62
Total Length
Noise mv 1 0.01 -99 1 is for ref..
SSN mV 1 0.1 -90 1 is for ref..
Alien mV 1 0.01 -99 1 is for ref..
Cross talk
FEXT mV 1 0.01 -99 1 is for ref..
NEXT mV 1 0.01 -99 1 is for ref..
ISI mV 200 50 -75 200 is for ref..
Jitter ps 50 10 -80 50 is for ref..
Flight Skew ns 50 10 -80 50 is for ref..
Skew Derating ns 50 10 -80 50 is for ref..
Slew Rate dI/dt
Reduced Delay Improves Margins, Increases Speed
• Lower Jitter• Lower Power Loss• Lower Skew• Excellent Impedance Control
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
20
• Excellent Impedance Control• Eye Diagram by Sharpening pulse due to improved
bandwidth and harmonics propagation 677MHz up to 5GHz and 20GHz and beyond…
Way Forward• Fund RFCONNEXT to develop a test bed
demonstrating Improved PCB Interconnect– Insert PMTL™/VMTL™ to improve TL5b type
Transmission line, to proof the concept, in DDR2, and Flyby in DDR3
3/1/2010Copyright 2008 RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
21
DDR2, and Flyby in DDR3
• Embed PMTL™/VMTL™ into DDR PCB’s– RFCONNEXT can supply new PCB for your
production– You can License the Technology
CONTACT US
• [email protected]• (408)981-3700• www.rfconnext.com
6/7/2008Copyright 2008-2010, RFCONNEXT, Inc. Propriatry, Confidential, Patents Pending
22