RF Modeling of Sub-100 nm CMOS

S.Yoshizaki1, M.Nakagawa1, W.Y.Chong1, Y.Nara2, M.Yasuhira2*, F.Ohtsuka2, T.Arikado2**, K.Nakamura2, K.Ka

kushima1, K.Tsutsui1 H.Aoki1, H.Iwai1

　 1 Tokyo Institute of Technology 2 Semiconductor Leading Edge Technologies, Inc. (Selete), Japan * Current affiliation : Matsushita Electric Industrial Co., Ltd., Japan ** Current affiliation : Tokyo Electron Ltd., Japan

0%

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80%

100%

2004 2005 2006 2007 2008 2009

Fig.1 4-th Generation mobile

Center Research Laboratory, Hitachi Ltd.

Spread of the cellular phone and the wireless LAN.

The age of Digital information appliances

RF technologies serve the rapidly growing wireless communication markets.

Background ~RF Technology~Background ~RF Technology~

Accurate RF Modeling become Accurate RF Modeling become important to more than before.important to more than before.

But …But …

ITRS2004update, 2004

Fig.2 Technology-development cost reduction (due to TCAD)

In RF, some parasitic In RF, some parasitic elements effect more elements effect more

severe.severe.

Merit Low cost compared with compound semiconductors

Consolidation with logic circuits

Low operation voltage with scaling

Scaling and Circuit technologies improve fT

and fmax

Feature in RFCMOSFeature in RFCMOSDemerit

SN ratio degradation

Fig.3 Application Spectrum ITRS2004, 2004

① Degradation of dielectric constant with dielectric relaxation.

② RF characteristic deterioration with degrading mobility.

③ Increase interface state density → Increase Low-frequency noise and thus Phase noise.

The concern about High-k The concern about High-k MOSFET in RFMOSFET in RF

MotivationMotivation

►There are little reports about RF performancThere are little reports about RF performance evaluation and modeling with High-k MOSe evaluation and modeling with High-k MOSFETs.FETs.

►Comparison HfSiON with SiON.Comparison HfSiON with SiON.

RF Modeling of Sub-100 nm High-k MOSFET

DeviceDevice► EOT = 1.5nm (HfSiON & SiON)EOT = 1.5nm (HfSiON & SiON)► Gate lengthGate length

HfSiON (LHfSiON (Lgg= 64nm), SiON (L= 64nm), SiON (Lgg= 51nm)= 51nm)► The number of finger = 12The number of finger = 12 （（ W=5μmW=5μm ））

Fig.4 HfSiON MOSFET structure

silicide

HfSiON SiN

Si

silicide

SiON SiN

Si

Fig.5 SiON MOSFET structureG G G G G

S S SD D

M1

STI

VIA1

63.9nm 61.7nm 62.3nm 65.5nm 65.3nm

S S

S S

G

D

G

S

D

Increase gate width with increasing number of fingers, the gate resistance become small.

23

1

f

totshGLN

WRR Nf : The number of fingerThe number of finger

Fig.6 Section of HfSiON MOSFET

DC Measurement and Simulation DC Measurement and Simulation 【【 HfSiONHfSiON 】】

0.00E+00

1.00E- 04

2.00E- 04

3.00E- 04

4.00E- 04

5.00E- 04

6.00E- 04

0 0.5 1 1.5

Vd[V]

Id/W

[A]

Fig.7 Measured and simulated Ids-Vds Fig.7 Measured and simulated Ids-Vds 【【 HfSiONHfSiON 】】

Vgs=0, 0.6, 0.9, 1.2, 1.5VVgs=0, 0.6, 0.9, 1.2, 1.5V MeasuredMeasured

SimulatedSimulated

0.00E+00

1.00E-04

2.00E-04

3.00E-04

4.00E-04

5.00E-04

6.00E-04

7.00E-04

0 0.5 1 1.5

Vd[V]

Id/W

[A]

Fig.8 Measured Ids-Vds Fig.8 Measured Ids-Vds 【【 SiONSiON 】】

To de-embed parasitic elements including wires and pads is important that could obtain the real device parameters.

RgLg

Cg

Rgp

Cgd Rgdp

Ld RdCd

Rdp

Rs

Ls

DUT

Drain

SHORT

De-embeddingDe-embedding

BSIM4

OPEN

Gate

DrainGate

Gate

Drain

Measured and Simulated fMeasured and Simulated fTT, f, fmax max 【【 HH

fSiONfSiON 】】

fT,HfSiON = 189.9[GHz]

fmax,HfSiON = 59.9[GHz]

GS

mT C

gf

2

)2)((2max

GDGTSGds

t

CRfRRg

ff

Fig.9 H21 and GAmax vs. Frequency Fig.9 H21 and GAmax vs. Frequency 【【 HfSiONHfSiON 】】

Fig.10 Equivalent circuit modelFig.10 Equivalent circuit model

Rg

CGD

CGS

LD

RD

BSIM4

0

10

20

30

40

50

0.1 1 10 100 1000

Frequency[GHz]

H21

, GA

max

[dB

]

Measured GAmaxSimulated GAmax

Measured H21Simulated H21

Vg=1.2V, Vd=1.5V

Measured S-parameter and PredicMeasured S-parameter and Predicted fted fTT, f, fmax max 【【 SiONSiON 】】

0

10

20

30

40

50

60

0.1 1 10 100 1000

Frequency[GHz]

H21

, GA

max

[dB

]

fT,SiON = 236[GHz]

fmax,SiON = 74[GHz]

Fig.11 H21 and GAmax vs. Frequency Fig.11 H21 and GAmax vs. Frequency 【【 SiONSiON 】】

Measured GAmaxExtrapolated GAmax

Measured H21Extrapolated H21

Vg=1.2V, Vd=1.5V

RF CharacterizationRF Characterization~ f~ fTT & g & gmm Comparison HfSiON with SiON~ Comparison HfSiON with SiON~

gm peak

0

50

100

150

200

250

0.01 0.1 1 10 100

Id[A]

fT[G

Hz]

0

10

20

30

40

50

60

70

80

90

100

gm[m

S]

fT SiON【 】fT HfSiON【 】gm SiON【 】gm HfSiON【 】

Cross SiON and HfSiON characteristics

Fig.12 fFig.12 fTT and g and gmm vs. Id vs. Id

Position of this devicePosition of this device

0

50

100

150

200

250

300

0.01 0.1 1

[μ m]ゲート長

ft [G

Hz]

nmos

pmos

SiON

HfSiON

0

50

100

150

200

250

300

0.01 0.1 1

[μ m]ゲート長

fmax

[GH

z]

nmos

pmos

Gate Length [um] Gate Length [um]

Fig.13 fFig.13 fTT and f and fmaxmax

IEDM, VLSI 1995 ～ 2004

We measured and simulated High-k MOSFET RF characteristics.

Measured from 500MHz to 40GHz, there is no dielectric relaxation.

Simulated fT and fmax in HfSiON, we obtained good fT (189.9GHz) relatively.

SiON is expected much more high performance than HfSiON. I guess this is because of mobility degradation.

SummarySummary

This work was partially supported by Special Coordination Funds for Promoting Science and Technology by Ministry of Education, Culture, Sports, Science and Technology, Japan.

AcknowledgementAcknowledgement

nmos

1.00E-19

1.00E-18

1.00E-17

1.00E-16

1.00E-15

1.00E-14

0.01 0.1 1 10 100Frequency[kHz]

Sid

[A2̂/

Hz]

SiONHfSiON

Id=1mA / Vd=0.1V

Appendix AAppendix A~Flicker noise~~Flicker noise~

Fig.14 Flicker noiseFig.14 Flicker noise

8 inch wafer, 40 GHz

Appendix BAppendix B~~RF CMOS Evaluation EquipmentRF CMOS Evaluation Equipment~~