reti risonanti - 1mwl.diet.uniroma1.it/people/pisa/rfelsys/l05_power_amp_2.pdf• measurement...

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1

Design flow of amplifiers for maximum output power

• Active devices (FET or BJT) are selected for design requirements

(Output power, efficiency, gain, IMD, bandwidth)

• Topology and Class are chosen in accordance with power, efficiency,

linearity

• Evaluation of optimum output termination (with respect to output

power, PAE, IMD)

• Design of output matching network

• Evaluation of optimum termination (with respect to gain and gain

ripple)

• Synthesis of input matching network to obtain:

– Gain and gain ripple;

– Stability

2

Power amplifiers design requirements

• In a power amplifier, the output has to be matched to the optimum load

for power delivery

• Output matching network cannot be used to compensate gain roll-off

in the bandwidth and to achieve stability

• Input matching network is used to fulfill at the same time requirements

on: VSWR, GT, Gain Flatness, stability

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3

Power amplifier design methodology

• In the design of a power amplifier the main challenge is to

determine the optimum load termination

• It can be done by:

– Load Pull measurements (either passive or active)

– Cripps method (analytic formula and Smith chart)

– Non-linear simulation in frequency domain (Harmonic

Balance)

4

Setup for Load pull measurement

DUT

Controller

Steppingmotors

DC BiasInput Tuner

Output Tuner

Power Source

Power meter

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5

Passive Load pull: main steps for measurements

• The input tuner has small effect on delivered power POUT : it is changed in

order to guarantee good input matching at specified frequencies

• The output tuner is varied in order to deliver the required POUT

• The DUT is disconnected, and input impedance of the tuner is measured

• The same operations are performed in order to draw the -X dB locus on

Smith chart

6

Passive Load pull measurements

• Operations described in previous slide are performed at

different power levels

• Typically, the designer is interested to locus at POPT-{1,2,3} dB

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7

Typical “Load Pull contours” (L88016 device from Polyfet )

8

Limitations of passive Load pull measurements

• Due to loss, passive Load-Pull is not able to fully cover

the unitary circle on the Smith chart

• Mechanical tuners are not able to guarantee measurement

accuracy

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Active Load pull set-up: operation principle

• A controlled power source is added at the output

• Active tuning is obtained by varying amplitude and phase of the output power

source

• Better Smith chart coverage is obtained: a variable complex termination (Z1) is

seen if the ratio I2/I1 is complex (amplitude and phase variation)

• No mechanical tuners are needed

Gen1 R Gen2

I2I1

1

21 1

I

IRZ

10

Active Load pull set-up: RF implementation

VDD

RFC

VGS

RF Load

(Power meter)

F

PowerAmp

Phaseshifter Attenuator

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11

Load Pull methodology features

• It is possible to enter instability regions of the DUT

• Measurement procedure is long and tedious if manual, expensive if automated

• It is required to de-embed parasitic elements (wire bond inductance, electrical

length of test fixture, …)

• When a new device is developed, load-pull measurements are the most

powerful tool to forecast non-linear device performance

12

Computer-assisted design of power amplifiers

• If an accurate non-linear model of the device is available, it is possible to

exploit for design:

– “Harmonic Balance” simulators, to achieve steady-state solution in

frequency domain

– “Time-domain” simulators, that allow to derive also transient response till

steady-state condition

• Even if non-linear simulators are a powerful design tool, a fully automated

design flow is still not possible

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13

Load-line Cripps theory

• Load-line Cripps theory can be used with linear models and simulators

• It is able to take into account of main limitations to output power delivery

(limitations on voltage and current dynamic)

• Output power prediction is often very accurate

14

Comparison of compression curves for maximum GT and for maximum POUT

A

A’B

B’ C’

C

PIN (dB)

PO

UT

(dB)

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15

“Linear” approximation for load-pull locus drawing

• Points A and A’ of previous slide are the maximum power in linear condition

• Points B and B’ of previous slide are the -1 dB compression point

• Matching for maximum GT produces a -1 dB compression point 2-3 dB lower

than matching for maximum POUT

16


• Matching for maximum power POUT shows different benefits:

– increase of maximum power in linear condition (points A e A’);

– increase of -1 dB compression point (points B e B’);

– increase of saturation power (points C e C’).

• The hypothesis is made that output power increase obtained by switching from

gain matching condition to power matching condition (A-A’, B-B’, C-C’) is

the same

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• Cripps theory of load-line is based on linear approximation, i.e. the maximum

power in linear condition (point A’) is evaluated

• It is assumed that the termination that allows maximization of power in linear

condition, is the same for maximum P-1dB and PSAT

• Very good agreement is found between load-pull measurements and Cripps

theory

18


VDD

RFC

ZL

VGS

VDS

ZL=ROPT

Device parasitics at output side are included into the load

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Load-line Cripps theory: ideal models for FET devices

IDVGS

VK VDSmax

VGS

(linear

steps)

ID

Transconductance is linear, except for interdiction and saturation

20


VK

2VDD-VK

VDSpeak

IDpeak

0

IF

t

tROPT

F

Kdd

Dpeak

DSpeakOPT

I

)VV(2

I

VR

2

FI

VDD

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• If we assume that RF trajectories in output plane of voltage and current

waveforms are the same of DC ones (quasi-static approximation);

• If we assume perfectly symmetric waveforms (harmonics are neglected);

• for maximum power in linear condition we get:

• and:

F

KddOPT

I

)VV(R

2

2

I)VV(

2

1P F

KddOPT

22


• In order to draw the “Load Pull” locus, let’s see what happens when real and

imaginary parts of ZL are varied with respect to the optimum value

• The goal is to derive the locus of constant output power as a function of ZL

• For each value of p coefficient (p > 1) we get a “Load pull” locus where POUT

is constant: this locus is not a circle!

p

PP OPTOUT

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• For a given p value, 2 resistance values exist that produce an output power

equal to:

• Such resistance values are one greater and one lower than ROPT:

p

PP OPTOUT

OPTHi RpR p

RR OPT

Lo

24


• In case of lower resistance:

– the FET device shows full current dynamic;

– voltage dynamic is reduced for a factor p

• In case of higher resistance :

– the FET device shows full voltage dynamic;

– current dynamic is reduced for a factor p

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ROPT

RHIRLOExample case p=2 (-3 dB)

Two points of the -3dB locus are drawn

In order to complete the locus drawing, we need to consider also complex terminations that allows to obtain an output power equal to POPT/2 (i.e. to add the proper reactive parts to RLO and to RHI)

26

Load-line Cripps theory: series reactance added to RLO

• Let’s consider also reactive part of the load:

– if |ZL|<ROPT, linear power is reduced due to a lower voltage dynamic

– the maximum current dynamic can be considered, and voltage dynamic

can be increased by adding a series reactance: however, output power is

not affected, as it depends only on resistive part

22LL

OPT

KDDLLL XR

R

VVZIV

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• The maximum value of added reactance is the one that allows maximum

voltage dynamic:

KDDLL

OPT

KDDL VVXR

R

VVV

22

222LOPTL

RRX p

RR OPT

L

mLm XXX 2

11

pRX OPTm

28


• The first half of load pull locus is obtained: it is a part of R=RLO circle,

comprised between -Xm and Xm values

ROPT

RHIRLO

Xm

-Xm

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Load-line Cripps theory: parallel susceptance added to RHI

• In this case:

– if |ZL|>ROPT, linear power is reduced due to a lower current dynamic

– the maximum voltage dynamic can be considered, and current dynamic

can be increased by adding a parallel susceptance: however, output power

is not affected, as it depends only on resistive part

22LLKDDLLL BGVVYVI

30


• The maximum value of added susceptance is the one that allows maximum

current dynamic:

222LOPTL

GGB

OPTOPT

RG

1

mLm BBB 2

11

pGB OPTm

22

22 FLLOPT

FL

IBGR

II

p

GG OPT

L

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• The second half of load pull locus is obtained: it is a part of G=GHI circle,

comprised between -Bm and Bm values

It can be demonstrated that the impedance RLO+jXm

corresponds just to the admittance GHI+jBm

ROPT

RHIRLO

RLO+jXm

RLO-jXm

32

Drawing of “load Pull contours” on Smith chart

• In order to draw “Load Pull” contours we need to:

– Evaluate ROPT and POPT according to expressions presented above;

– Choose p coefficient according to design requirements;

– Evaluate RLO and RHI (locus points on real axis);

– Starting from RLO, consider constant-R circle (R= RLO) up to +/- Xm

values;

– Starting from RHI , consider constant-G circle (G= GHI) up to +/- Bm

values;

– Repeat the same procedure for different p values

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Comparison between “load Pull contours” and mismatch circles on

Smith chart

Load pull locus does not show circular behavior; moreover, -X dB region is smaller than the corresponding region for mismatch circles

34

Package effects: Load-line Cripps theory improvements

• Load-Pull loci of previous slide are not dependent on frequency

• Indeed, measured loci are strongly dependent on frequency

• Dependence on frequency is related to the choice of reference plane for

impedance measurement

• In order to have a meaningful comparison between theory and measurements,

effects of device output impedance and package effects have to be considered

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• The proposed approach permit evaluation of loci at reference plane A

• In order to allow evaluation at plane B, de-embedding of parasitics (XC) has to

be made

• De-embedding is made by considering a transformation in the admittance

plane:

ID

“A” “B”

XC ZL

CAL

BL

YYY

36


De-embedding of device output

capacitance is obtained by means of a

rotation around the parallel

conductance circle

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“A”

COUT

ZL

“B”LOUT

Package

- Firstly, rotation due to COUT (see previous slide)

- Then, de-embedding of wire bond inductance is

obtained by means of a rotation around the series

resistance circle

Also packageeffects

38


• Good agreement between theory

and measurements

• Theory is more pessimistic with

respect to measurements

• Theory is a good initial point also

for broad-band design

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Accuracy and limitations of the proposed approach

• For methodology practical implementation, we need:

– Static curves of active device

– Knowledge of device output impedance and package parasitics (a

model of package can be extracted from measured S parameters)

• Even if different approximations have been made, the proposed

methodology is a good starting point for power amplifier design

• Availability of both a non-linear model and a non-linear simulator

permits refinements and optimization of the design

40

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Matching networks - 1

In RF amplifier design, matching networks are used to provide

fulfillment of gain/power requirements. Design methodology is

quite different from the one used or low-frequency amplifiers

(for instance OPAMP and audio amplifiers)

Review: at low frequency, matching is obtained by:

•Zg<<Zl Voltage matching

•Zg>>Zl Current matching

42


Example: ideal transformer with given coil number ratio n

g2

2LOAD

Rn'Rg

nVg'Vg

n

RZin

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Ideal transformer and, in general, loss-less networks are able

to preserve the available power:

g2

22

Rn'Rg

Rg8

Vg

'Rg8

'VgPavnVg'Vg

The same available power is referred to a different internal

source impedance

44

Narrow-band Matching networks

• Requirements: f0, Q, transform ratio RS / RL

• L-shape (2 elements)

• Tapped resonant, T-shape and -shape (3 elements)

• Transformer-based networks

– Single-tuned transformers

– Tapped coil transformers

– Double-tuned transformers

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L-shape networks /1

• The matching network is composed of 2 elements:

the first one allows impedance transformation, the

second one provides tuning to f0

• WARNING: It is not possible independent choice

of Q and f0

46

L-shape networks /2

Configurations for downward resistance transformation

RL RLR’ R’

LR'R

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47

LR'R

RL RLR’ R’

L-shape networks /3

Configurations for upward resistance transformation

48

L-shape networks /4

• Design example:

– Transformation from a 50 load to 250 at 50 MHz

50

S->P transformation

250

4Q)Q1(R'R 22

H318.0LR/LQ

pF5.25)'L/(1C 2

0

H3975.0)Q/11(L'L 2

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• The matching network is composed of 3 elements, the first

2 ones allow load transformation, the third one tuning to f0

• It is possible independent choice of Q and f0

• The resistance is transformed two times (both downward

and upward

49

Tapped resonant, T-shape and -shape

R” R”R R

T-shape -shape

B2 B1B3

X1 X2X3

50

-shape networks /1

R” RB1B3

X2

R’ - j / B1’

R’ - j / B3’

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51

-shape networks /2

• A first P->S transformation allows R decrease, the second

one (S->P) resistance increase

)Q1/(R'R 2

1

)Q1('R"R 2

2

)Q1(

)Q1(R"R

2

1

2

2

• In case of downward transformation: Q1 > Q2

• In case of upward transformation: Q2 > Q1

52

-shape networks /3

• Q1 is related to R and to the first element B1 of the network:

• The impedance seen at the right side is:

• where:

• and therefore the reactance seen at the right side is:

RBQ 11

)Q/11(B'B 2111

11

1 Q'R'B

1'X

R’ + j X1’= R’ - j / B1’

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53

-shape networks /4

• Q2 is related to R” and to the third element B3 of the network:

• and therefore the reactance seen at the left side is:

• For matching at the tuning frequency f0 we get:

"RBQ 32

)Q/11(B'B 2233

23

3 Q'R'B

1'X

0'XX'X 321 )QQ('RX212

54

-shape networks /5

• In case of upward transformation, maximum Q is equal to Q2. In case of downward transformation, maximum Q is equal to Q1

• In both cases we have: Qmax = 2Q (loaded Q is given) where approximation is made that loaded Q is equal to Qmax / 2

DESIGN PROCEDURE

R"R 2max QQ

R"R 1max QQ

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55

-shape networks /6

• The intermediate resistance R’ is chosen:

• The other Q value is then

chosen from transform ratio:

• B1 and B3 are determined: B1 = Q1 / R B3 = Q2 / R”

• X2 is found: X2 = R’·(Q1 + Q2)

DESIGN PROCEDURE

)Q1(

)Q1(R"R

2

1

2

2

R"R

R"R )Q1/(R'R 2

1

)Q1/("R'R 22 The maximum

Q is chosen

56

-shape networks /7

DESIGN EXAMPLE

• Matching of a 50 load to a 2.5 source termination at a 10.0 MHz

frequency, with loaded Q equal to 2.5

• Transformation produces resistance decrease, and therefore:

Qmax = Q1 = 2·2.5

• A network with a capacitor as a first element is chosen:

0C1 = Q1/R => C1 = 1.59 nF

• Q2 is chosen starting from Q1 and from transform ratio: Q2 = [12.5 / 50

·(1 + 5 2)] 0.5 = 2.35

• Reactance of the 2nd element is chosen:

X2 = 50 (5 + 2.35) / (1 + 52) = 14.13 = 0L2 => L2 = 225 nH

• Tuning capacitance is chosen: 0C3 = Q2/R” => C3 = 3 nF

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57

-shape networks /8

DESIGN EXAMPLE

58

-shape networks /9

DESIGN EXAMPLE

Q = 3.1

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59

T-shape networks /1

R” R

X1X3

B2G’ - j / X1’G’ - j / X3’

60

T-shape networks /2

• A first S->P transformation allows R increase, the second

one (P->S) resistance decrease

• In case of downward transformation: Q1 < Q2

• In case of upward transformation: Q2 < Q1

)Q1(R'R 2

1

)Q1/('R"R 2

2

)Q1(

)Q1(R"R

2

2

2

1

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61

T-shape networks /3

• Q1 is related to R and to the first element X1 of the network:

• The susceptance seen at the right side is:

R/XQ11

)Q/11(X'X 2

111 'R/Q

'X

1'B 1

11

62

T-shape networks /4

• Q2 is related to R” and to the third element X3 of the network:

• and therefore the susceptance seen at the left side is:

• For matching at the tuning frequency f0 we get:

"R/XQ32

)Q/11(X'X 2

233 'R/Q

'X

1'B 2

33

0'BB'B 321 'R/)QQ(Y212

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63

T-shape networks /5

• In case of upward transformation, maximum Q is equal to Q1. In case of downward transformation, maximum Q is equal to Q2

• In both cases we have: Qmax = 2Q (loaded Q is given) where approximation is made that loaded Q is equal to Qmax / 2

DESIGN PROCEDURE

R"R 1max QQ

R"R 2max QQ

64

T-shape networks /6

• The intermediate resistance R’ is chosen:

• The other Q value is then

chosen from transform ratio:

• X1 and X3 are determined: X1 = Q1·R X3 = Q2·R”

• B2 is found: B2 = (Q1 + Q2) / R’

DESIGN PROCEDURE

The maximum

Q is chosen

)Q1(

)Q1(R"R

22

21

R"R

R"R )Q1("R'R 22

)Q1(R'R 21

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65

Tapped resonant circuits /1

b) Tapped-capacitor circuita) Tapped-inductor circuit

C1

L1RSRL

C2

L2

RL

C L

RS

66


• A first Parallel->Series transformation (resistance is

lowered):

22C

L2

2C

LLS

222C

22C

2S2

Q

R

Q1

1RR

CQ

Q1CC

C1

RLS

C2SL

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67


• A second Series -> Parallel transformation

(resistance is enhanced):

RTOTCL

2

2C

2C

L22C

2C

L2CLSTOT

S21

S21

2C

2C

S21

S21

Q

QR

Q1

Q1RQ1RR

CC

CC

Q1

Q

CC

CCC

68


• The 2nd transformation produces a parallel resonant circuit, where

input resistance is just the matching resistance at resonance

• If we consider Q expressions we find;

• The matching network produces multiplication of load resistance for a

factor depending on the ratio of capacitances

2

1

2L

2

1

21LTOT

C

C1R

C

CCRR

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69


• Qtot = 2Q = 2f0 / BW is chosen (in order to account for partition due to

matched load).

• C value is calculated:

• L value is calculated :

• QC2 value is calculated :

Design procedure

S0

tot

R

QC

C

1L

20

1R/R

Q1Q

LS

2tot

2C

70


• C2 value is calculated :

• C2S value is calculated :

• C1 value is calculated :

Design procedure

CC

CCC

S2

S21

L0

2C2

R

QC

22C

22C

2S2Q

Q1CC

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71


• We need to match a 50 load to a 4K source resistance at 3.0 MHz

resonance frequency, with a loaded Q = 7.5.

• Unloaded Q value is: Qtot = 2·7.5 = 15.

• Overall capacitance is: C = 15 / (0RS) = 200 pF.

• Tuning inductance is: L = 1 / (02 C) = 14 uH.

• If the other expressions previously presented are applied, we find:

– QC2 = 1.34

– C2 = 1.4 nF

– C2S = 2.2 nF

– C1 = 0.22 nF

DESIGN EXAMPLE

72


DESIGN EXAMPLE

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73


DESIGN EXAMPLE

Q = 7.14

74


A first Parallel->Series transformation is done (resistance is

lowered):

and we get:

22L

L2

2L

LLS

222L

22L

2S2

Q

R

Q1

1RR

LQ1

QLL

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75


A second Series -> Parallel transformation is done: resistance

is enhanced, and Q value is unchanged

.

2

2L

2L

L22L

2L

L2LLSTOT

S21TOT

Q

QR

Q1

Q1RQ1RR

LLL

Under high-Q (Q<10)

hypothesis we get:

2

2

1L

2

2

21LTOT

L

L1R

L

LLRR

76

Design with complex termination

• At a first step, reactive parts of both load and source

terminations are neglected: the network is designed for

pure resistive transformation

• Then, the 1st and the 3rd element are modified to account

for reactive parts

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77

T-shape networks

DESIGN WITH COMPLEX

TERMINATIONS

RL

X1 XL

X3

Xin X3’

R” + j XinB2 ZL

"RQ'X23

LL11XRQX

78

T-shape networks

DESIGN EXAMPLE WITH COMPLEX TERMINATIONS

• A matching network is designed at 5 MHz in order to match a load ZL =

10 + j 10 to a source ZS = 50 - j 40 , with a 2.5 loaded Q

• Q of the circuit is: Qmax = 2·2.5 = 5.

• Resistance increase is produced: Qmax = Q1.

• Overall reactance at load side is X1 + XL = 5·10 = 50 , and we get:

X1 = 40 L1 = 1.27 uH.

• Q2 is determined: 1 + Q22 = (1 + 52) ·10 / 50 Q2 = 2.05.

• Overall reactance at source side (that sets resonance) is X3 = 2.05·50 =

103 , from which: L3 = 3.3 uH. A reactance equal to -XS = 40 is

added

• Finally, tuning parallel capacitor is evaluated:

C2 = (5 + 2.05) / [(2·5 MHz)·10 ·(1 + 52)] = 0.86 nF

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79

T-shape networks


80

T-shape networks


Q = 2.63

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81

-shape networks

DESIGN WITH COMPLEX

TERMINATIONS

"R/Q'B23

LL11

BR/QB

RLB1 BL

B3

Bin B3’G” + j Bin

X2

YL

82

Transformer-based matching networks

:

BW

Matched transformer at f0

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83

Tapped coil with mutual coupling /1

Matching to the amplifier input or output impedance

84


1) V1 = j (L1 + L2 + 2 M) I1 + j (M + L2) I2

2) V2 = j (L2 + M) I1 + j L2 I2 = - I2 R0 (only R0 at a first step)

Matching to the amplifier output impedance

I1

I2

M

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85


By substituting 2 into1, the input impedance Zin() is obtained:

3) Zin() = jL + (R0 - j L2) (L2 + M)2 2 / |R0 + j L2|2=

jL + (R0 - j L2) (L2 + M)2 / [L22 (1 + QL2

2)]

where:

L = L1 + L2 + 2M

QL2 = R0 / L2


86


Transformer expressions:

1] L1 = N12 / (N1 + N2)

2 L 2] L2 = N22 / (N1 + N2)

2 L

where N = (N1 + N2) / N2 is the transform ratio

3] Mutual inductance M = k (L1 L2)1/2, k is the coupling factor

By using 1]-2]-3] with k = 1 (approximation) we get:

4) (L2 + M)2 / L22 = N2

That can be substituted into 3) in order to evaluate the input impedance:

5) Zin() = jL + (R0 - j L2) N2 / (1 + QL2

2)


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87



By using 2] we get:

6) Zin() = jL QL22 / (1 + QL2

2)+ R0 N2 / (1 + QL22)

For usual Q values (QL2 >> 1) the input impedance is:

7) Zin() = jL + R0 N2 / QL22

and therefore on the primary coil we see the series connection of L (the total

primary coil inductance) and a resistance R’0 equal to:

8) R’0 = R0 N2 / QL22

The related Q factor is just:

9) Q = L / R’0 = L QL22 / (R0 N2) = QL2

where expression 2] has been used

88



A Series -> Parallel transformation allows to get at the primary coil:

10) L0 = L (1 + Q2) / Q2 L

11) Rin0 = R’0 (1 + Q2) R’0 Q2 = R0 N2

where 8 and 9 have been used.

Also C is transformed at the same way:

12) Cin0 = C0 / N2

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89



The equivalent circuit at the primary side is:

- We need Cin0 << Cp so that the tuning is mainly due to Cp: high transform

ratio N helps us to reduce effects of parasitic capacitance

- High Rino means high Q

Rin0 = R0 N2

Cin0 = C0 / N2

90

Single-tuned transformer /1

Matching to the amplifier input or output impedance

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91


Matching to the amplifier input impedance

13) V1 = j L I1 + j M I2

14) V2 = j L3 I2 + j M I1 = - I2 Rin2 (only Rin2 at a first step)

92



By substituting 14 into 13 the input impedance Zin() is obtained :

15) Zin() = jL + (Rin2 - j L3) ( M)2 / |Rin2 + j L3|2 =

jL + (Rin2 - j L3) M2 / [L32 (1 + QL3

2)]

where QL3 = Rin2 / L3

Again M2 / L32 is just the transform ratio N’2 and therefore we get:

16) N’ = N1 / N3

and:

17) Rin0 = Rin2 N’2 Cin0 = Cin2 / N’2

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93



The equivalent circuit at the primary side is:

- We need Cin0 << Cp so that the tuning is mainly due to Cp: high transform

ratio N helps us to reduce effects of parasitic capacitance

- High Rin0 means high Q

Rin0 = Rin2 N’2

Cin0 = Cin2 / N’2

94

Interstage matching network /1

Tapped coil with mutual coupling and Single-tuned transformer

are used together to match the output of the first stage and the

input of the 2nd stage to a common tuning capacitance at the

primary side

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95


- Results for Tapped coil with mutual coupling can be used

- Results for Single-tuned transformer can be used with:

L = L1 + L2 + 2M

N’ = (N1 + N2) / N3

96


N and N’ have to be chosen suitably high, so that:

- C1 and C2 are small with respect to Cp, and resonance frequency is

mainly determined by Cp value

- R1 and R2 don’t lower the coil Q factor

Equivalent circuit at the primary side

Coil

Rin2 N’2

Cin2 / N’2

R0 N2

C0 / N2

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97

Double-tuned transformer

98

Equivalent scheme

2secsec1L

2

sec

2

2

21prpr1

I)Cj/1Lj(MIj)RC/(I

MIjI)Cj/1Lj(V

At resonance we have:

1L

2

sec

3

2

21

IRCjMI

MIjV

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99

Maximum power transfer

secpr

crS

2

pr

2

0in

QQ

1k)RC/(1)(Z

Input impedance at resonance:

Maximum power transfer condition:

L

2

sec

24

0in RCM)(Z

100

Insertion loss at resonance

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101

Transmission line trasformers /1

lcosIlsinZ

jVI

lsinIZjlcosVV

20

21

2021

Equations of a loss-less transmission line:

where Z0 is the characteristic impedance and is the (real) propagation

constant

If the output termination is just Z0, the input impedance is equal to Z0 for

any value of length l

102


A Balanced-to-Unbalanced (Balun) converter can be obtained: it works as a

broadband 1:1 transformer

:

This kind of transormers is widely used in broadband RF power amplifiers in

Class A and Class B and AB push-pull

+

V1

-

+

V2

-

I1 I2

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103


Another widely used topology in power amplifiers is the 1:4 impedance

transformer

I the two transmission lines show characteristic impedance Z0, and the

termination load is ZL =2 Z0, at the input the parallel connection of two Z0

impedances is seen and therefore ZIN =1/2 Z0

Moreover, if the input termination is ZS =1/2 Z0, at the input the series

connection of two Z0 impedances is seen, and therefore ZOUT = 2 Z0

Both the balanced and the unbalanced version of 1:4 impedance transformer

can be found: the former is used in push-pull amplifiers

104


Single-ended

transformer

Balanced

transformer

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105


RF transmission line trasformers are usually made with handformable or

semi-rigid coaxial cables, available with different characteristic impedance

values (www.micro-coax.com)

Vbias

106


The external conductor shows magnetic loss, modelled by means of a parallel

inductor

Such inductance produces a low-frequency pole-zero couple: the bandwidth is

reduced, as a low-frequency cut-off frequency is introduced

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107


Inductance is found by integrating the magnetic density flux B created by a

perfect cylindrical conductor (with length Len and radius c) in which current I

flows, in the region surrounding the coaxial cable itself

The expression of flux B(y0,R0) in a point y0 in the interval [-Len/2,Len/2] on

y axis, and in a point R0 on an axis orthogonal to y, is:

20

20

0

20

20

0

0

00

)y2Len(R4

y2Len

)y2Len(R4

y2Len

R4

I)R,y(B

108


If c << Len and ferrite is not used, L is obtained by integration of B (and by

considering that the integral is equal to LI) in an unlimited volume with

length Len and radius comprised in the interval [c , ):

If length Len is partially surrounded by ferrite, the integral in this region has

to consider the complex permeability (’ + j ”) of the ferrite itself:

1

c

Len2lnLen

2L

ferriteferrite L'j'

''LLjZ

Integral in ferriteIntegral in air

The real part

causes resistive

loss: heat

dissipation issue

Also ferrites

are placed on

dissipator

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109


Circuital implementation in CAD Keysight ADS: Parasitic

impedance due

to magnetic loss

Parasitic inductance

of internal conductor

portion uncovered

for soldering

110


Push-pull amplifier based on 1:4 transmission line transformers:

VbiasIN VbiasOUT

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111


Photo of a 20-500MHz 100W Push-pull amplifier:

A lossy input matching network (not shown) is put at the input side in broadband

amplifiers for gain slope adjust

A local parallel-parallel

feedback on each transistor

is often used

reti risonanti - 1mwl.diet.uniroma1.it/people/pisa/rfelsys/l05_power_amp_2.pdf• measurement...

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