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RESISTIVE SWITCHING MEMORY FOR NON-VOLATILE STORAGE AND
NEUROMORPHIC COMPUTING
A DISSERTATION
SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING
AND THE COMMITTEE ON GRADUATE STUDIES
OF STANFORD UNIVERSITY
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
Shimeng Yu
July, 2013
http://creativecommons.org/licenses/by-nc/3.0/us/
This dissertation is online at: http://purl.stanford.edu/xh257vm1382
© 2013 by Shimeng Yu. All Rights Reserved.
Re-distributed by Stanford University under license with the author.
This work is licensed under a Creative Commons Attribution-Noncommercial 3.0 United States License.
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I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Philip Wong, Primary Adviser
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
Yoshio Nishi
I certify that I have read this dissertation and that, in my opinion, it is fully adequatein scope and quality as a dissertation for the degree of Doctor of Philosophy.
S Simon Wong
Approved for the Stanford University Committee on Graduate Studies.
Patricia J. Gumport, Vice Provost Graduate Education
This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file inUniversity Archives.
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Abstract
As CMOS scaling will soon approach its physical limit, it is necessary to consider new
computing paradigms that continue to improve computing system performance. We are
entering the “Big Data” era which puts data sets remotely at the data center for
computing, and the size of data sets is rapidly exceeding exascale. The functionality and
performance of today’s computing system are increasingly dependent on the
characteristics of the memory sub-system. Conventional memories technologies such as
SRAM, DRAM, and FLASH are facing formidable device scaling challenges. Emerging
memory technologies may bring enormous opportunities for architecture evolution or
revolution of the computing system in the future.
Among various emerging memory technologies, oxide based resistive switching
memory (RRAM) stands out due to its simple structure, low switching voltage (<3 V),
fast switching speed (<10 ns), excellent scalability (<10 nm), and great compatibility
with the CMOS technology. The observation that oxides can switch between an
insulating state and a conductive state can be dated back to 1960s. Research activities
have revived since 2004 with more complete data sets of the memory characteristics
reported such as device reliability and array integration. Through years’ efforts from both
academia and industry, Gb-scale prototype RRAM chip has been demonstrated so far.
During the development of the RRAM technology, key challenges include unclear
physics of resistive switching in oxides, relatively poor uniformity and large variability of
v
the switching parameters. And at this moment today, the central question should be what
application spaces are for the RRAM technology to play a disruptive role. The works in
this dissertation aim to address those issues above.
The physical mechanism of resistive switching is generally attributed to the
conductive filament (made up of oxygen vacancies) formation and rupture in the oxide
due to field assisted oxygen ion migration. As a model system for device physics study,
HfOx based RRAM devices were fabricated and characterized. To identify the conduction
mechanism, various electrical characterization techniques such as I-V measurements at
various temperatures, low-frequency noise measurements, and AC conductance
measurements were employed. It was suggested that the trap-assisted-tunneling is the
dominant conduction mechanism. In order to explore the oxygen ion migration dynamics,
pulse switching measurements were performed. An exponential voltage-time relationship
was found between the switching time and the applied voltage.
To obtain a first-order understanding of the variability of resistive switching, a Kinetic
Monte Carlo (KMC) numerical simulator was developed. The
generation/recombination/migration probabilities of oxygen vacancies and oxygen ions
were calculated, and the conductive filament configuration was updated stochastically
according to those probabilities. The KMC simulation can reproduce many experimental
observations in the DC I-V sweep, pulse switching, endurance cycling, and retention
baking, etc. The tail bits in the resistance distribution are attributed to the oxygen vacancy
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left over in the gap region due to a competition between the oxygen vacancy generation
and recombination. To enable circuit and system development using RRAM, a compact
device model was developed, which can be employed in many commonly available
circuit simulators using the SPICE engine.
One promising application for the RRAM technology is to serve as the synaptic device
for the hardware implementation of neuromorphic computing. The gradual resistance
modulation capability in RRAM was utilized for emulating analog synapses, and the
stochastic switching behavior in RRAM was utilized for emulating binary synapses. In
order to evaluate the effectiveness of analog synapses and binary synapses, a simulation
of winner-take-all network was performed based on the parameters extracted from the
experiments. The simulation suggests that the orientation classification can be effectively
realized using both analog synapses and binary synapses. The system functionality is
found to be robust against the RRAM device variability due to the adaptive algorithm and
parallelism of the neural network.
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Acknowledgments
First and foremost, I would like to express my deepest gratitude to my advisor, Prof.
H.-S. Philip Wong, who is a great mentor and guided me through my PhD journey. He
always encourages me to explore new ideas, and I truly appreciate the degrees of freedom
that he offered on conducting the research. During my four years at Stanford, Prof. Wong
has influenced me in many aspects with his optimistic attitude and passionate personality.
Not only I learn from him how to do the research, but also I learn from him to how to
manage a group. Prof. Wong has provided me with many great opportunities such as
research collaborations and summer internships. And he is very supportive of my pursuit
of the academic career path and helps me a lot in my faculty position applications, from
editing my research statement to writing a strong recommendation letters, from offering
interview tips to submitting joint proposal to funding agencies. Without his unselfish
support, I cannot achieve my success so far.
I would like to acknowledge my other dissertation reading committee members: Prof.
Yoshio Nishi and Prof. Simon Wong, for their valuable suggestions and advises on my
work. Prof. Nishi is very kind and amiable and always willing to help when I meet
problems. Prof. Simon Wong is always sharp at the key issues in the research and
provided me a lot of feedbacks on my work.
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I would like to acknowledge other faculty in Stanford as well. I wish to thank Prof.
Ada Poon and Prof. Subhasish Mitra for serving as my oral defense committee. And
especially I would like to thank Prof. Mitra for his support in my future academic career.
I would also like to thank Prof. Roger Howe and Prof. Krishna Saraswat for their help in
my study at Stanford.
I am grateful to my collaborators, Prof. Jinfeng Kang and his group at Peking
University, on many joint projects: Prof. Kang is my undergraduate research advisor,
who brought me to the field of my study a few years ago. The technical discussions with
Dr. Bin Gao are always inspiring and rewarding. Yexin Deng is a diligent undergraduate
researcher who works with me on the 3D cross-point array analysis.
I am grateful to my mangers and mentors during my summer internships: Dr. Jurczak
Malgorzata, Dr. Jorge Kittl, and Dr. Yangyin Chen at IMEC, and Dr. Mark Ritter, Dr.
Kailash Gopalakrishnan, Dr. Jing Li at IBM. They either wrote recommendation letters
for me or helped me settle down at new places and guided me on intern projects.
I am grateful to my references who wrote recommendation letters for my faculty
position applications: Prof. Wei Lu at University of Michigan, Prof. Daniele Ielmini at
Politecnico di Milano, and Dr. Fred Chen at ITRI in Taiwan;
I also wish to thank my colleagues at Stanford for their indispensable assistance on my
projects: Ximeng Guan on the device modeling, Yi Wu, Hong-Yu Chen and Yang Chai
on the device fabrication, Jiale Liang and Zizhen Jiang on the cross-point array analysis,
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Rakesh Jeyasingh on the device testing, Duygu Kuzum on the synaptic device design, etc.
Without them, I would not have been able to accomplish my PhD work so smoothly. And
I am thankful for the useful discussions with the lab mates in other groups: Suyog Gupta,
Zhiping Zhang, Liang Zhao, etc. I would also thank our group secretary: Fely Barrera,
who helps me with all kinds of financial and administrative issues.
I truly appreciate my friends who make my life at Stanford so colorful and wonderful,
and I will treasure those beautiful moments forever: Ze Yuan, Yu Zhao, Jieying Luo,
Weiruo Zhang, Yangsen Kang, Mengying Zhang, Hangyu Li, Chao Ni, Yutian Lu,
Liangliang Zhang, Lan Wei, Xiangyu Chen, Chi-Shuen Lee, He Yi, Hai Wei, Xiao Zhang,
Chen Chen, and Nuo Xu. Special thanks are to my long-time old friends: Cong Xu,
Xiaomu Wu and Zhaoyi Kang, they have stood by my side throughout all the peaks and
valleys in my past years.
Last but not least, I would like to express my deepest love to my family members: my
father and mother, my grandfather and grandmother, my uncles and aunts, my cousins.
They have shown me unconditional and unbounded love, and they always encourage me
to pursue my dream. Their support is the strongest driving force for me to go forward.
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Table of Contents
List of tables ...................................................................................................................... xii
List of figures ................................................................................................................... xiii
Chapter 1 Introduction .........................................................................................................1
1.1 Motivation for Emerging Memory Technologies ....................................................1
1.2 Resistive Switching Phenomenon in Oxides ...........................................................4
1.3 Development and Applications of RRAM technology ..........................................10
1.4 Thesis overview .....................................................................................................19
Chapter 2 Characterization of Resistive Switching in Oxides ..........................................22
2.1 Physical Mechanism of Resistive Switching in Binary Oxides .............................22
2.2 HfOx Based RRAM Device Fabrication and Characterization ..............................28
2.3 Electron Conduction Process in HfOx Based RRAM ............................................38
2.3.1 I-V Measurements at Various Temperatures ................................................38
2.3.2 Low Frequency Noise (LFN) Measurement .................................................43
2.3.3 AC Conductance Measurement ....................................................................52
2.4 Ion Dynamics in HfOx Based RRAM ....................................................................60
2.4.1 Voltage-Time Relationship in Switching Dynamics ....................................60
2.4.2 Energy-Efficient Programming Scheme for Multi-bit Operation .................63
2.5 Summary ................................................................................................................68
Chapter 3 RRAM Device Modeling and Simulation .......................................................69
3.1 Kinetic Monte Carlo (KMC) Modeling .................................................................69
3.1.1 TAT solver ....................................................................................................71
3.1.2 Resistor Network ..........................................................................................75
3.1.3 KMC Module for Ionic Process ....................................................................78
3.1.4 Simulation of Current Overshoot ..................................................................81
3.1.5 Simulation of Variability ..............................................................................86
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3.1.6 Simulation of Reliability ...............................................................................91
3.2 Compact Modeling.................................................................................................94
3.3 Discussions and Summary .....................................................................................98
Chapter 4 Oxide Based Synaptic Device for Neuromorphic Computing .......................103
4.1 Background ..........................................................................................................103
4.2 Synaptic Plasticity and Learning .........................................................................105
4.3 Analog Synapse and Binary Synapse for WTA Network ....................................113
4.3.1 Analog Synapse for Depression Learning ..................................................114
4.3.2 Binary Synapse for Stochastic Learning .....................................................117
4.3.3 Winner-Take-All Network Simulation .......................................................123
4.4 Performance Metrics for Synaptic Device ...........................................................134
4.5 Summary ..............................................................................................................138
Chapter 5 Conclusion and Outlook .................................................................................139
5.1 Summary of contribution .....................................................................................139
5.2 Future work ..........................................................................................................141
Bibliography ....................................................................................................................143
Author’s Biography .........................................................................................................171
Publications ......................................................................................................................172
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List of tables
Number Page
Table 1.1 Device Characteristics of conventional and emerging memory technologies .....4
Table 1.2 Summary of the materials that have been used for binary oxide RRAM.
Metals of the corresponding binary oxides used for the resistive switching
layer are colored in yellow. Metals used for the electrodes are colored in
blue. ....................................................................................................................6
Table 1.3 The switching modes for various metal oxide RRAM devices with different
electrode combination. .......................................................................................9
Table 1.4 Representatives of selection devices for RRAM in the literature ......................14
Table 2.1 The characteristics of the HfOx/AlOx RRAM device. .......................................38
Table 4.1 Summary of the desirable performance metrics for synaptic devices. ............137
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List of figures
Number Page
Figure 1.1 The memory hierarchy in today’s system, which has a pyramid structure.
SRAM, DRAM, FLAH are the mainstream technologies serving for
caches, main memory, and solid-state-drive, respectively. ...............................2
Figure 1.2 (a) Schematic of metal-insulator-metal structure for oxide RRAM, and
schematic of metal oxide memory’s I-V curves, showing two modes of
operation: (b) unipolar and (c) bipolar. ..............................................................8
Figure 1.3 The cross-point memory architecture a) without cell selection elements and
(b) with cell selection elements........................................................................12
Figure 1.4 Schematic of the proposed 3D cross-point architecture using the vertical
RRAM cell. The vertical RRAM cells are formed at the intersections of
each pillar electrode and each plane electrode: the resistive switching
oxide layer surrounds the pillar electrode and is also in contact with the
plane electrode. To enable the random access of each memory cell, three-
dimensional decoding is needed through WL (decoding in z-direction), BL
(decoding in y-direction) and SL of the gate of the vertical MOSFET
(decoding in x-direction)..................................................................................17
Figure 2.1 Schematic of the possible electron conduction paths through a
metal/oxide/metal stack. (1) Schottky emission; (2) F-N tunneling; (3)
direct tunneling; (4) tunneling from cathode to traps; (5) emission from
trap to conduction band, which is essentially the Poole-Frenkel emission;
(6) F-N like tunneling from trap to conduction band; (7) trap to trap
hopping or tunneling; and (8) tunneling from traps to anode. .........................26
Figure 2.2 Schematic of the switching mechanism of oxide RRAM. ...............................28
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Figure 2.4 The HRS and LRS resistance distribution in (a) and the switching voltage
distribution in (b) of the HfOx/AlOx bi-layer samples and the HfOx single
layer samples obtained by 200 DC sweep cycles. ...........................................32
Figure 2.5 The transient voltage/current waveform during (a) RESET transition and
(b) SET transition. ............................................................................................34
Figure 2.6 The HRS and LRS resistance degradation during the SET/RESET cycling. ...36
Figure 2.7 The I-V characteristics after 5×105 cycles........................................................36
Figure 2.8 The stability of the device for different resistance states measured at an
elevated temperature (100 °C). ........................................................................37
Figure 2.9 Poole-Frenkel emission model fitting results: (a) In(I/V) vs. sqrt(V) for
electron injection from TiN under a negative bias. (b) In(I/V) vs. 1/kT to
extract the activation energy (Ea) (c) Extrapolating Ea to zero bias, the trap
energy (~0.08 eV) is extracted from the intersection on the y-axis, and the
dielectric constant (~79) is extracted from the slope. These two parameters
are unreasonable compared to their known values. .........................................41
Figure 2.10 Temperature dependency (In(I/V) vs. 1/kT) for multi-level resistance
states at both positive and negative biases. ......................................................42
Figure 2.11 Schematic of the LFN measurement set-up. ...................................................44
Figure 2.12 The RRAM device noise, measurement system’s noise, and equivalent
resistor’s thermal noise for LRS (a) and HRS (b). ...........................................46
Figure 2.13 The relative noise current fluctuation in the time domain for different
resistance states. ...............................................................................................47
Figure 2.14 The normalized PSD (Si/I2) in the frequency domain for different states. .....48
Figure 2.15 The PSD (Si) as a function of the squared DC bias for LRS (the inset) and
HRS respectively. ............................................................................................48
Figure 2.16 The normalized PSD (Si/I2) as a function of the DC bias voltage. .................49
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Figure 2.17 Lorentzian function 4τ/(1 + ω2τ2) for different τ. Single Lorentzian is
1/f 2, and the envelope of multiple Lorentzian is 1/f. The cutoff frequency
corresponding to a shortest electrode-to-trap tunneling gap distance (~2
nm) is shown (the dash line). ...........................................................................52
Figure 2.18 The Nyquist plot (-Im(Z) vs Re(Z)) for HRS and LRS. .................................54
Figure 2.19 The total conductance spectrum in LRS and HRS under various DC
biases. ...............................................................................................................55
Figure 2.20 The total conductance spectrum in different resistance levels in HRS. .........55
Figure 2.21 The AC conductance spectrum (a) for various DC biases at a particular
HRS level and (b) for different HRS levels at a particular DC bias. ...............57
Figure 2.22 Schematic of the DC and AC conduction processes in RRAM device. .........60
Figure 2.23 Measured voltage-time relationship: pulse amplitudes needed to
successfully trigger the SET/RESET switching at the some fixed pulse
widths. The success of the trigger is defined to meet pre-defined target
LRS/HRS resistances (20 kΩ/1 MΩ). ..............................................................63
Figure 2.24 The DC I-V characteristics of HfOx/AlOx RRAM by a different RESET
stop voltages (-2.1 V, -2.7 V, and -3.3 V). ......................................................64
Figure 2.25 (a) Three levels of HRS obtained by fixed pulse width (50 ns) but
different pulse amplitudes (-2.3 V, -2.6 V, -2.9 V). (b) Similar three levels
of HRS obtained by fixed pulse amplitude (-2.3 V) but different pulse
widths (50 ns, 500 ns, 5 µs). ............................................................................66
Figure 2.26 Transient voltage/current waveform for the two RESET programming
schemes. The first scheme: -2.3 V/50 ns; The second scheme: -2 V/500 ns.
The initial resistance is ~10 kΩ, and the final resistance is ~50 kΩ. The
energy consumption for the first scheme (-2.3 V/50 ns) is about 7.4 pJ and
for the second scheme (-2 V/500 ns) is about 60.9 pJ. ....................................67
Figure 3.1 The KMC simulation flow................................................................................70
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Figure 3.2 The TAT process in the oxide RRAM. ............................................................71
Figure 3.3 I-V of 1D Vo chain for different gap distances simulated by TAT solver.
The inset shows current exponentially decreases with increasing gap
distance, which is the main cause of the HRS variation. .................................73
Figure 3.4 The electron occupancy probability in the traps in the 1D Vo chain (a) for
a complete Vo chain connecting both electrodes (representing LRS) and
(b) for a ruptured Vo chain with a gap (representing HRS). ...........................74
Figure 3.5 Schematic of the resistor network: each node in the network represent an
atom site in the oxide matrix. The node can be a red Vo site or a blue
lattice oxygen (OL) site. ...................................................................................75
Figure 3.6 An example of the simulated local electric potential in HRS with a gap
between top electrode and residual CF. ...........................................................76
Figure 3.7 An example of the simulated local temperature in LRS when CF connects
both electrodes. ................................................................................................77
Figure 3.8 Simulated I-V curve of a 1D Vo chain in RRAM cell with 1 nm tunneling
gap considering multiple conduction mechanisms. .........................................78
Figure 3.10 Simulated I-V with overshoot: 1) FORMING with RC time constant
τ=100 ns; 2) FORMING with τ=10 ns; 3) SET with τ=100 ns. The
compliance is 10 µA. .......................................................................................82
Figure 3.11 Simulated voltage drop on the RRAM as a function of time during the
overshoot period...............................................................................................82
Figure 3.12 Simulated current during the overshoot period. The compliance is 10 µA. ...83
Figure 3.13 The evolution of the CF shape for the FORMING/RESET/SET cycles
using KMC simulator for (a) fresh sample; (b) Onset moment of
FORMING with τ=100 ns; (c) LRS after FORMING with τ=100 ns; (d)
Onset moment of FORMING with τ=10 ns; (e) LRS after FORMING with
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τ=10 ns; (f) RESET with τ=100 ns; (g) Onset moment of SET with τ=100
ns; (h) LRS after SET with τ=100 ns. Pink dots are Vo. Blue dots are O2-. ....86
Figure 3.14 Simulated I-V curves during the repeated 100-cycle DC sweep. ...................87
Figure 3.15 Simulated (a) resistance distribution and (b) switching distribution during
the repeated 100-cycle DC sweep. ...................................................................88
Figure 3.16 An example of the existence of Vo (highlighted by red circle) in the gap
region which causes a tail bit in HRS. .............................................................90
Figure 3.17 The transient current waveform measured during the RESET with the last
current jump indicating a Vo left-over in the gap region. ................................91
Figure 3.18 Simulated endurance cycling at 125 °C. .........................................................92
Figure 3.19 The Vo configuration for the final failure state (stuck at LRS). ....................92
Figure 3.20 Statistically simulated LRS retention of 100 RRAM cells @150 °C. ............93
Figure 3.21 Simulated LRS failure time distribution at three baking temperatures. .........94
Figure 3.22 Schematic of conductive filament with oxygen vacancies. The tunneling
gap distance g determines the device resistance. .............................................95
Figure 3.23 The I-V fitting of multi-level resistance states by varying the gap
tunneling distance in the compact model. ........................................................97
Figure 3.24 The gradual RESET transition curves by pulse train with different
amplitudes. .......................................................................................................98
Figure 4.1 An analogy between the biological synapse and the artificial oxide
synaptic device. The vision is that the parallel neural network can be
emulated by the cross-point RRAM array for large-scale integration. ..........105
Figure 4.2 The asymmetric form of STDP states that the synaptic weight depends on
the relative timing of pre- and post-synaptic spikes [135]. ΔG = (Gafter-
Gbefore)/Gbefore. Gbefore is the conductance before the pre and post spike pair,
and Gafter is the conductance after the pre and post spike pair. ......................107
xviii
Figure 4.3 The up-down cycling of the HfOx/AlOx synaptic device for (a) the first 100
cycles and for (b) the 100 cycles after 105 endurance testing cycles. The
pulse widths were fixed to be 50 ns. The pulse sequence is 5 pulses
increased from -2.2 V to -2.6 V with a step -0.1 V and then 5 pulses with
increased from 1.4 V to 1.8 V with a step 0.1 V............................................109
Figure 4.4 The HfOx/AlOx synaptic device resistance modulation by the pulse
amplitude starting from an initial state with an intermediate resistance
value (200 kΩ ~ 300 kΩ, the shaded region in the plot). Each error bar
consists of 50 independent tests. ....................................................................111
Figure 4.5 Spike-timing-dependent plasticity (STDP) realization schemes developed
with time-division multiplexing and pulse amplitude modulation. The
pulse amplitudes for the pre-spike are -1.4 V, 1 V, 0.9 V, 0.8 V, 0.7 V, 0.6
V, consecutively, and for the post-spike are -1V, 1.4 V, 1.3 V, 1.2 V, 1.1
V, 1V, consecutively. .....................................................................................112
Figure 4.6 The STDP-like curve calculated with the data in Figure 4.4 employing the
signaling schemes in Figure 4.5 .....................................................................112
Figure 4.7 The DC I-V characteristic of the TiOx/HfOx/TiOx/HfOx synaptic device. .....114
Figure 4.8 The depression learning process by 400 consecutive identical RESET
pulses for 5 different devices. The initial resistance states are chosen to be
~500 Ω and ~20 kΩ, respectively. .................................................................115
Figure 4.9 The depression learning process at several milestones during the 1000
cycle endurance cycling test. 1 cycle includes 400 consecutive identical
RESET pulses. ...............................................................................................116
Figure 4. 10 Dependence of the energy per spike on the initial resistance states for the
training process. If starting at ~ 20 kΩ, the maximum energy per spike
drops below 1 pJ. ...........................................................................................116
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Figure 4.11 Simulated depression learning process starting from ~500 Ω by varying
the pulse amplitudes, mimicing the the experimental data in Figure 3.24. ...117
Figure 4.12 Measured SET/RESET continuous cycling with different SET pulse
amplitudes (a) +1.9 V/10 ns, (b) +1.6 V/10 ns, (c) +1.3 V/10 ns,
respectively. The SET process becomes stochastic under weak
programming conditions. ...............................................................................120
Figure 4.13 Measured statistical distribution of pulse amplitude required for
triggering the SET switching from the off-state. In (a), the probability of
SET switching is measured from one representative device for 100 cycles.
In (b), 50 different devices on the wafer were measured with one type of
symbol in the figure representing the data from one device. .........................122
Figure 4.14 The WTA architecture implemented by integrate-and-fire neurons and
oxide synaptic devices. ..................................................................................125
Figure 4.15 A spiking scheme for implementing the unsupervised competitive
learning algorithm designed for (a) binary synapse and for (b) analog
synapse. ..........................................................................................................126
Figure 4.16 Simulated normalized conductance map between the input layer neurons
and the output layer neurons utilizing binary synapse with stochastic
learning (a)-(c) and analog synapse with depression learning (d)-(f). The
normalization is done with respect to a reference that is the highest
conductance in the synapse array before the training. ...................................128
Figure 4.17 Simulated system performance metrics as a function of programming
conditions. Network orientation selectivity and orientation storage
capacity for binary synapse in (a) and for analog synapse in (c); Energy
consumption of the synaptic devices during the whole training (200
training images) for binary synapse in (b) and for analog synapse in (d).
The average values through 100 independent simulation runs are shown. ....132
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Figure 4.18 Simulated orientation selectivity as a function of the analog synapse
variability δR/R. At each error bar, 100 independent simulations are
performed. ......................................................................................................133
1
Chapter 1 Introduction
1.1 Motivation for Emerging Memory Technologies
As CMOS scaling will soon approach its physical limit, it is necessary to consider new
computing paradigms that continue improving the computing system performance. We
are entering the “Big Data” era which puts data sets remotely at the data center for
computing, and the size of data sets is rapidly exceeding exascale [1]. The functionality
and performance of today’s computing system are increasingly dependent on the
characteristics of the memory sub-system. The current memory sub-system has a well-
known pyramid-like hierarchy (Figure 1.1): SRAM, DRAM, and FLASH are the
mainstream technologies serving as caches, main memory, and solid-state-drive,
respectively. Going up of the pyramid, the latency decreases, and going down of the
pyramid, the capacity increases. From an architecture perspective, the multi-core
processors on the chip require more data to be fed in time to support the high computing
throughput. It means that memories need either lower latency or larger capacity to
increase the bandwidth. Meanwhile, low-power applications call for a non-volatile
memory on chip to minimize the standby leakage power. As a summary, the conventional
memory technologies are hard to satisfy the memory requirement with device scaling.
Therefore, emerging memory technologies have been actively pursued both in industry
and academia in hopes of finding solutions for future information storage needs.
2
Figure 1.1 The memory hierarchy in today’s system, which has a pyramid structure.
SRAM, DRAM, FLAH are the mainstream technologies serving for caches, main
memory, and solid-state-drive, respectively.
The ideal characteristics for a memory device include fast programming speed (<ns),
low operation voltage (<1 V), low power/energy consumption (~fJ/bit for write), long
retention time (>10 years), long write/read endurance (>1016 cycles), and excellent
scalability (<10 nm). Nevertheless, it is challenging to satisfy the entire ideal
characteristic in a single “universal” memory [2], several emerging memory technologies
have been pursued towards to achieving part of those ideal characteristics. Those
candidates are spin-transfer-torque magnetoresistive random access memory (STT-
3
MRAM) [3], phase change random access memory (PCRAM) [4], and resistive random
access memory (RRAM) [5]. These emerging memory technologies share some common
features: they are non-volatile two-terminal devices, and they differentiate their states by
the switching between a high resistance state (HRS) and a low resistance states (LRS).
The transition between the two states can be triggered by electrical inputs. However, the
detailed switching physics is quite different for different memories: STT-MRAM relies
on difference in resistance between the parallel configuration (corresponding to LRS) and
anti-parallel configuration (corresponding to HRS) of two ferromagnetic layers separated
by a thin tunneling insulator layer; PCRAM relies on chalcogenide material to switch
between the crystalline phase (corresponding to LRS) and the amorphous phase
(corresponding to HRS); and RRAM relies on the formation (corresponding to LRS) and
the rupture (corresponding to HRS) of conductive filament between two electrodes. Due
to the different underlying physics, the device characteristics are also different among
emerging memory technologies. Table 1.1 compares the device characteristics between
various emerging memory technologies with various conventional memory technologies.
As it is seen from Table 1.1, as compared with SRAM, STT-MRAM has the advantage of
a smaller cell area, while STT-MRAM has maintained low programming voltage, fast
write/read speed and long endurance, thus STT-MRAM is attractive for embedded
memory on chip, e.g., the SRAM replacement in caches [6]. As compared with FLASH,
RRAM is attractive due to its lower programming voltage and faster write/read speed,
4
thus the initial target of RRAM technology development is to replace FLASH for mass-
storage application. Besides replacing the existing technologies, those emerging memory
technologies hold the potential to revolutionize today’s memory hierarchy by adding
more levels in the hierarchy, e.g. creating a storage class memory level between the main
memory and the storage memory [7]. It should be mentioned that different emerging
memories may have different application spaces due to their various characteristics, and
hybrid system with emerging memory and conventional memory is also attractive [8].
Table 1.1 Device Characteristics of conventional and emerging memory technologies
Conventional Memories Emerging Memories
SRAM DRAM FLASH STT-
MRAM PCRAM RRAM
NOR NAND
Cell area 140F2 6F2 10F2 <4F2 ~20F2 4F2 <4F2 if 3D
Multi-bit 1 1 1 3 1 3 2
Voltage <1V <1V >20V >20V <2V <3V <3V
Read time <1ns ~10ns ~10ns ~0.1ms <10ns ~10ns <10ns
W/E time <1ns ~10ns 1µs/10ms 1/0.1ms <10ns ~50ns <10ns
Retention N/A ~64ms >10y >10y >10y >10y >10y
Endurance >1E16 >1E16 >1E5 >1E4 >1E15 >1E9 >1E6~1E12
Write
Energy
(J/bit)
<fJ ~10fJ ~100pJ <0.1fJ ~0.1pJ ~10pJ ~0.1 pJ
F: feature size of the lithography used for patterning the cell
1.2 Resistive Switching Phenomenon in Oxides
The resistive switching phenomenon in oxides was firstly reported in the 1960s [9].
Recent work on the oxide based resistive switching memory can be traced back to the
5
discovery of hysteresis I-V characteristics in perovskite oxides such as Pr0.7Ca0.3MnO3
[10][11], SrZrO3 [12], SrTiO3 [13], etc. in the late 1990s and the early 2000s. Since
Samsung demonstrated NiO memory array integrated with the 0.18 µm silicon CMOS
technology in 2004 [14], research activities have been focused on binary oxides such as
NiOx [15], TiOx [16], CuOx [17], ZrOx [18], ZnOx [19], HfOx [20], TaOx [21], AlOx [22],
etc., because of the simplicity of the material and good compatibility with silicon CMOS
fabrication process. Note that the oxides here are often non-stoichiometric, thus we use
subscript “x” for the oxygen composition in this thesis.
Generally speaking, there are two types of resistive switching memory. One type is
based on the conductive filaments (CF) of oxygen vacancies (Vo); the other type is based
on the CF of metal atoms, which is also called conductive-bridge RAM (CBRAM).
CBRAM relies on the fast-diffusive Ag or Cu ions migration into the oxide (or
chalcogenide) to form a conductive bridge. In this thesis, we focus our discussion within
the Vo based binary oxide memory1. For the perovskite oxide memory, it can be referred
to the review by R. Waser et al. [23]. For the CBRAM, it can be referred to the review by
I. Valov et al. [24].
So far, tens of binary oxides have been found to exhibit resistive switching behavior.
Most of them are transition metal oxides, and some are lanthanide series metal oxides.
1 If not specifically noted, the term “RRAM” refers to the Vo based binary oxide memory
in this thesis.
6
The materials for the resistive switching oxide layer and the electrodes are summarized in
Table 1.2. Besides metal electrode, conductive nitrides, e.g. TiN, TaN are also commonly
used as electrode materials.
Table 1.2 Summary of the materials that have been used for binary oxide RRAM. Metals
of the corresponding binary oxides used for the resistive switching layer are colored in
yellow. Metals used for the electrodes are colored in blue.
Before starting the following discussion, we first introduce some basic concepts and
terminologies about oxide RRAM. The switching event from HRS to LRS is called the
7
“SET” process. Conversely, the switching event from LRS to HRS is called the “RESET”
process. Usually for the fresh samples in its initial resistance state, a voltage larger than
the set voltage is needed to trigger on the resistive switching behaviors for the subsequent
cycles. This is called the “FORMING” process. The switching modes of the oxide
RRAM can be broadly classified into two switching modes: unipolar and bipolar. Figure
1.2 shows a sketch of the I-V characteristics for the two switching modes. Unipolar
switching means the switching direction depends on the amplitude of the applied voltage
but not on the polarity of the applied voltage. Thus SET/RESET can occur at the same
polarity. If the unipolar switching can symmetrically occur at both positive and negative
voltages, it is also referred as a non-polar switching mode. Bipolar switching means the
switching direction depends on the polarity of the applied voltage. Thus SET can only
occur at one polarity and RESET can only occur at the reverse polarity. For either
switching modes, to avoid a permanent dielectric breakdown in the FORMING/SET
process, it is recommended to enforce a compliance current, which is usually provided by
the semiconductor parameter analyzer, or more practically, by a memory cell selection
transistor/diode or a series resistor that is either on-chip or close to the memory cell. To
read the data from the cell, a small read voltage is applied that does not affect the state of
the memory cell to detect whether the cell is in HRS or LRS.
8
Figure 1.2 (a) Schematic of metal-insulator-metal structure for oxide RRAM, and
schematic of metal oxide memory’s I-V curves, showing two modes of operation: (b)
unipolar and (c) bipolar.
It is observed that the electrode materials have a significant effect on the switching
modes of the oxide RRAM. Table 1.3 summarizes the switching modes for various oxide
RRAM devices with different electrode combinations. Even with the same oxide material
but with different electrode materials, the switching modes can be different. Therefore, it
is inferred that the switching mode is not an intrinsic property of the oxide itself but a
property of the both the oxide material and the electrode/oxide interfaces. In most cases,
the unipolar mode is obtained with a noble metal such as Pt or Ru as both top and bottom
electrodes. With one of the electrodes replaced by oxidizable materials such as Ti or TiN,
the bipolar mode is obtained. For bipolar switching, it was suggested that the reversed
field is required for a successful RESET because an interfacial oxygen barrier (e.g., TiON)
9
exists [25]. If both electrodes are oxidizable, there should be some asymmetry in the
oxygen gettering capability for bipolar switching. A typical structure is
TiN/metal/oxide/TiN 2 , e.g. TiN/Ti/HfOx/TiN [20], TiN/Hf/HfOx/TiN [26], where the
metal capping layer function as an oxygen gettering layer. Generally, the unipolar
switching needs a higher reset current than bipolar switching, probably due to the
requirement of thermally enhanced filament dissolution. In the following discussion, we
will focus on the bipolar switching.
Table 1.3 The switching modes for various metal oxide RRAM devices with different
electrode combination.
Unipolar Bipolar
Pt/NiOx/Pt [15] Pt/NiOx/SrRuO3 [27]
Pt/TiOx/Pt [28] Pt/TiOx/TiN [29]
Pt/ZnOx/Pt [30] TiN/ZnOx/Pt [31]
Pt/ZrOx/Pt [32] Ti/ZrOx/Pt [32]
Pt/HfOx/Pt [33] TiN/HfOx/Pt [34]
Pt/AlOx/Ru [35] Ti/AlOx/Pt [36]
2 If not specifically noted, the stack sequence is from the top to the bottom in this thesis.
10
1.3 Development and Applications of RRAM technology
The development of oxide RRAM has progressed rapidly in the last several years. In
particular, binary oxides that use materials that are familiar to the semiconductor industry
has seen intense research and development in both industry and academia. The vision for
oxide RRAM is a non-volatile memory that is fast, high-density, and compatible with
integration with conventional silicon CMOS technology. The early RRAM had large
device areas (>>µm2), large programming currents (mA), long programming times (µs),
low endurance (<103 cycles), and requires a cell selection transistor which was limited in
device density. Today, many of these deficiencies have been overcome. Device sizes
down to 10 nm × 10 nm have been demonstrated [26], programming currents are now in
the order of µA or tens of µA [26], write/read speed is in the order of ns or tens of ns [26],
write/read endurance cycles are up to 1012 [37], retention time is up to 3000 hours at
150 °C [21], and the FORMING process can be eliminated [22], although these
characteristics are yet to be simultaneously demonstrated in the same material system.
Chip-scale RRAM array from Mb to Gb size with peripheral circuitry were demonstrated
[38][39][40]. Demonstrations of multi-bit operation have also been made [41][42].
At memory array level, the device density is mostly determined by the memory cell
selection device and not the memory cell itself. A common architecture is similar as the
random accessible NOR FLASH architecture: each RRAM cell is connected with a cell
selection transistor, which is referred as 1 transistor-1 resistor (1T1R). By controlling the
11
selection transistor’s gate voltage through the word line, varying current can be provided
to control the switching characteristics of RRAM cell. The 1T1R cell area can range from
6F2 (F: feature size of the lithography used for patterning the cell) using aggressive
DRAM-like design rules with borderless contacts and zero gate to source/drain spacing to
8F2 (with F/2 gate to source/drain spacing) and 18F2 (contacts with borders).
For high-density integration, a cross-point architecture with 4F2 area is preferred. The
simplest way is to connect the word and bit lines at each node by a RRAM cell. A sneak
path problem with this simple cross-point architecture may arise (Figure 1.3): if the cell
to be read out happens to be in HRS with surrounding cells in LRS, the reading current
can easily flow through the surrounding cells in the LRS and thus a LRS data will be
mistakenly read out. Further discussions about the sneak path problem and the
interconnect effect on the cross-point architecture design can be referred to these works
[43][44][45]. The conclusions from these works indicate that in order to magnify the
write/read margin of the memory array, larger ratio of the RRAM resistance over the
interconnect resistance is desired, thus increasing the LRS resistance is helpful. In order
to further suppress the sneak paths, a cell selection element with strong I-V non-linearity
is desired to be added at each node. The cell selection element can be a diode for unipolar
switching RRAM as the 1 diode-1 resistor (1D1R) architecture, or a bi-directional
selector (with a strong non-linear I-V characteristics in both polarities) for bipolar
switching RRAM as the 1 selector-1 resistor (1S1R) architecture. The diode or the
12
selector effectively cuts off the leakage current paths at reversed bias or low bias, thus the
interference between neighboring cells is prevented.
Figure 1.3 The cross-point memory architecture a) without cell selection elements and (b)
with cell selection elements.
Here we briefly discuss the cell selection element materials. For unipolar switching, a
p–n diode is the most common device for the cell selection element. Although high
performance p–n diode is easily fabricated with current epitaxial silicon technology for
the planar device structures, it is not feasible to implement epitaxial silicon-based p–n
diode with the RRAM array at the back-end-of-line (BEOL) because it is difficult to
grow epitaxial silicon on a metal layer and high processing temperatures are required. On
13
the other hand, amorphous silicon allows for lower processing temperatures. But it does
not meet the requirement for current density for memory cell programming. Therefore,
new materials need to be explored for the cell selection element, which should both allow
for low processing temperatures and also provide high current drivability. Compared with
silicon p-n diode, oxide p-n diode is more attractive because it offers better flexibility in
processing technology because it can be fabricated during BEOL processing even at room
temperature. If the oxide material is oxygen deficient with sufficient amount of oxygen
vacancies, it is n-type; while if the oxide material is metal deficient with sufficient
amount of metal vacancies, it is p-type. Thus a combination of p-type oxide and n-type
oxide essentially forms a p-n diode. Recently, several kinds of oxide p-n diodes [46],
such as p-NiO/n-TiO2, p-NiO/n-ZnO, p-NiO/n-InZnO, p-CuO/n-InZnO, have been
demonstrated and stacked with Pt/NiO/Pt RRAM in series, among which p-CuO/n-InZnO
is regarded as the best candidate in terms of current drivability. Besides the p-n oxide
diode, through oxide/electrode or oxide/oxide interface band engineering, rectifying I-V
in uni-direction for unipolar switching or non-linear I-V in bi-direction for bipolar
switching can also be achieved. For examples, Schottky diode with Pt/TiO2/Ti/Pt stack
has been integrated with Pt/TiO2/Pt unipolar RRAM [47], Ni/TiO2/Ni bi-directional
selector has been integrated with Ni/HfOx/Pt bipolar RRAM [48], Pt/TaOx/TiO2/TaOx/Pt
bi-directional selector has been integrated with Cu/HfOx/Pt bipolar RRAM [49]. In
addition, some metal-insulator-transition materials (MIT) such as VO2, NbO2 can be used
14
for selector as well. Unlike RRAM devices, the resistive switching behavior in MIT
materials is not bistable, and it is referred as threshold switching. The threshold switching
is non-polar dependent, thus it is suitable for bipolar switching RRAM. The sharp
increase of current by magnitude of orders when reaching the threshold voltage provides
an ideal behavior as selector device. Pt/VO2/Pt selector has been integrated with NiO
unipolar RRAM [50] and ZrOx/HfOx bipolar RRAM [51]. However, the VO2 has a
transition temperature around 67 oC beyond which the threshold switching behavior
disappears [52], which is a major drawback for the practical application. Alternatively,
NbO2 has a transition temperature around 800 oC, thus it is more attractive due to its
thermal stability. W/NbO2/Pt selector has been integrated with WOx [53] and NbOx [54]
bipolar RRAM respectively. Last but not least, Cu ion motion in the Cu-containing
Mixed Ionic Electronic Conduction (MIEC) materials also shows a good selector
behavior for bipolar switching RRAM [55].
Table 1.4 compares several selection element candidates mentioned above in aspects
of voltage range, current drivability, rectifying ratio. Although substantial progress has
been made in the past few years, the development of selection element is still a key
challenge for implementing cross-point memory architecture today. Although the
reported diodes or selectors show a promising current drivability and rectifying ratio,
many of them use Pt in the stacks, which is not CMOS fabrication process-friendly.
Table 1.4 Representatives of selection devices for RRAM in the literature
15
Type Stack Voltage Range Current Drivability Ratio
p-n diode p-CuO/n-InZnO
[46]
-2V~+2V 3×104 A/cm2 3×104
Schottky
diode
Pt/TiO2/Ti/Pt [47] -2V~+2V 3×105 A/cm2 2.4×106
Bi-directional
selector
Ni/TiO2/Ni [48] -4V~+4V 105 A/cm2 103
Bi-directional
selector
Pt/TaOx/TiO2/TaOx
/Pt [49]
-2.5V~+2.5V 3.2×107 A/cm2 104
MIT Pt/VO2/Pt [51] -0.5V~+0.5V 6×106 A/cm2 50
MIT W/NbO2/Pt [54] -1.5V~+1.5V 2×106 A/cm2 50
Bi-directional
selector
MIEC [55] -0.5V~+0.5V 5×104 A/cm2 * 3×103
The voltage range is the max voltage where the current density is measured; For diode,
the ratio is defined as the forward/reverse current at the max voltage; For bi-directional
and MIT selector, the ratio is defined as the current at max voltage over half of the max
voltage; *MIEC has a higher current drivability ~50×106 A/cm2 at pulse mode (1.6V).
16
The major remaining challenge is device variability. Switching parameter variation is a
major barrier for using RRAM in large memory arrays as well as multi-bit operation.
There is still substantial cycle-to-cycle variation as well as device-to-device variation of
the device characteristics such as the switching voltages, resistance distributions, etc. To
make progress in this area, it is necessary to have a more complete understanding of the
conduction and resistive switching mechanism. This thesis aims to address this issue. At
the end of the day, the solutions to the variability problem may come from a combination
of materials engineering, device structure optimization, as well as innovations in
addressing/readout circuitry and programming algorithm.
The primary target of RRAM is to replace the FLASH technology, as FLASH is facing
scaling limitations beyond 10 nm technology node [56]. For mass-storage application, a
key challenge for RRAM is improving the integration density in terms of cost per bit (bit-
cost), so it can compete with the multi-bit storage NAND FLASH. State-of-the-art
NAND FLASH has been scaled down to sub-20 nm regime, and the 3D stackable NAND
FLASH is emerging [57][58][59]. To achieve similar device density as the 3D NAND
FLASH, a technology path toward the 3D stackable RRAM is required. There are two 3D
integration approaches for RRAM available: one is the planar RRAM stacked layer by
layer [60], however, it does not save lithography steps or masks because in each layer a
lithography step is needed to pattern the features and therefore the bit-cost remains high;
the other one is the vertical RRAM sandwiched between the pillar electrodes and multi-
17
layer plane electrodes [61][62][63], which requires only one critical lithography step or
mask thus it is a more promising approach for reducing the bit-cost. We initiated the 3D
RRAM research and proposed a cost-effective technology path towards 3D integration
(Figure 1.4). As a proof of concept work, two-layer vertical HfOx RRAM structure were
fabricated and characterized [64]. Programming schemes for random access in the 3D
array were proposed and the 3D array operation was experimentally demonstrated [65].
Furthermore, the scaling trend of the 3D vertical RRAM array was analyzed by
experiments and 3D circuit simulation [65]. Due to the space limit, these works [64] [65]
are not included in this thesis.
Figure 1.4 Schematic of the proposed 3D cross-point architecture using the vertical
RRAM cell. The vertical RRAM cells are formed at the intersections of each pillar
electrode and each plane electrode: the resistive switching oxide layer surrounds the pillar
electrode and is also in contact with the plane electrode. To enable the random access of
18
each memory cell, three-dimensional decoding is needed through WL (decoding in z-
direction), BL (decoding in y-direction) and SL of the gate of the vertical MOSFET
(decoding in x-direction).
While RRAM has the potential to be a stand-alone, high-capacity non-volatile memory
technology, it may be even more suitable for embedded applications. This is because it
offers the low programming voltage that FLASH does not offer and the non-volatility
that DRAM does not offer and yet has a speed that is comparable to DRAM. For
examples, a 8T2R nonvolatile SRAM cell with 2 RRAM at two storage nodes of SRAM
has been demonstrated for dynamical power management [66]. The use of RRAM as
reconfiguration memory enables a 3D reconfigurable field programmable gate array
architecture (FPGA) design [67]. Another emerging application is using RRAM as
artificial synaptic device for the hardware implementation of neuromorphic computing.
Owing to RRAM’s multi-level capability and low power/energy consumption, it can
behave like an analog memory emulating the function of plastic synapses in a neural
network. And part of this thesis research aims to explore the design space of RRAM
synaptic device. Although the early vision for RRAM is to strive for a 4F2 cross-point
architecture (and even with multi-bit operation and 3D integration), it is not entirely clear
that these goals continue to make sense generally, given the many diverse potential
applications of RRAM. For example, for embedded applications, improving the
19
endurance of RRAM appears to be more important, and then the design trade-offs
between the endurance and retention may be utilized. The ability to put an RRAM at the
contact vias of the MOSFET without extensive process steps [20] is also an attractive
device feature, especially for embedded applications where only a low memory capacity,
multiple-time programmable, non-volatile memory is required. Therefore, there is an
enormous opportunity to completely rethink the design of the system to gain new
functionalities and even orders of magnitude improvements in speed and/or power
consumption.
1.4 Thesis overview
This thesis addresses the key challenges of the RRAM technology development,
including the physics of resistive switching in oxides, the origin of the relatively poor
uniformity and large variability of the switching parameters. And also one promising
application of RRAM technology: emulating synapse for neuromorphic computing, is
explored.
Chapter 1 gives an overview of the background of the work in this thesis, including
the motivation of the emerging memory technologies, the basics and terminologies of
resistive switching phenomenon in oxides, the current status and challenges of RRAM
technology development.
Chapter 2 discusses the physical mechanism of resistive switching phenomenon in
binary oxides. The resistive switching is attributed to the conductive filament (made up of
20
oxygen vacancies) formation and rupture in the oxides. As a model system for device
physics study, HfOx based RRAM devices were fabricated and characterized. The trap-
assisted-tunneling was identified to be the dominant conduction mechanism. An
exponential voltage-time relationship was found between the switching time and the
applied voltage, suggesting the oxygen ion migration dynamics. Inspired by the voltage-
time relationship, an energy efficient programming scheme was also proposed for multi-
level operation.
Chapter 3 reports a Kinetic Monte Carlo (KMC) numerical simulator and a compact
model of RRAM. In order to gain more insights into the device physics such as the origin
of the switching variability, a physics-based KMC model was developed. The KMC
simulation can reproduce many experimental observations in the DC I-V sweep, pulse
switching, endurance cycling, and retention baking, etc. The tail bits in the resistance
distribution are attributed to the oxygen vacancy left over in the gap region due to a
competition between the oxygen vacancy generation and recombination. In addition, for
circuit/system-level simulations, a compact device model was developed, and the
compact model can be implemented in a SPICE simulator.
Chapter 4 explores the potential of the RRAM technology as synaptic device for the
hardware implementation of neuromorphic computing. Programming schemes were
proposed for realizing spike-timing dependent plasticity in the RRAM devices. The
gradual resistance modulation capability in RRAM was utilized for emulating analog
21
synapses, and the stochastic switching behavior in RRAM was utilized for emulating
binary synapses. In order to evaluate the effectiveness of analog synapses and binary
synapses, a simulation of winner-take-all network was performed based on the
parameters extracted from the experiments. The simulation suggests that the orientation
classification can be effectively realized using both analog synapses and binary synapses.
The system functionality is found to be robust against the RRAM device variability due
to the adaptive algorithm and parallelism of the neural network.
Chapter 5 summarizes the results and contribution of this thesis. Future work is also
proposed in this chapter.
22
Chapter 2
Characterization of Resistive Switching in
Oxides
2.1 Physical Mechanism of Resistive Switching in Binary
Oxides
The physical mechanism for resistive switching in oxide RRAM has been a
complicated topic. We need to first differentiate two types of switching mechanisms:
electronic-effect and ionic-effect. The electronic-effect mechanism conjectures that
injected charges are trapped by interface defects. These trapped charges modify the
Schottky barrier height between electrodes and oxides and thereby changing the
conductance through the stack [68][69]. Ionic-effect mechanism conjectures that the
migration of ions with related electrochemical reactions to form a conducting channel
between electrodes [23][70], which also referred as redox (reduction/oxidation) effect. In
this thesis, we focus the discussion on the ionic-effect mechanism, which is the prevailing
theory for the switching mechanism for the binary oxide RRAM.
The conduction of LRS current in the oxide RRAM is usually filamentary.
Conductive atomic force microscopy (C-AFM) measurements scanning the top surface of
the oxide [16][71] revealed that conductive filaments (CF) with nanoscale diameters are
formed after the FORMING/SET process, and conducting current passes through these
CF in LRS. The first direct observation of CF in the cross-section fashion was done by
D.-H. Kwon et al. [72], in which the nanoscale (~10 nm in diameter) CF in TiOx RRAM
was seen by high-resolution transmission electron microscopy (HR-TEM). Typically, CF
23
are sparsely and non-homogeneously distributed across the device. This means that the
conducting area in LRS is an extremely small portion of the entire electrode area, which
is typically quite large in most experiments. A usual experiment that aims at
distinguishing filamentary or bulk conduction is to measure the trend of the HRS/LRS
resistance ratio versus the cell area. If the ratio goes up when the cell area is scaled down,
filamentary conduction prevails. If the ratio remains almost constant when the cell is
scaled down, bulk conduction prevails. It should be noted that when the device size
scaled to the size that is comparable to the CF diameter (e.g. < 20 nm), a single CF may
dominate the conduction.
The nature of CF is usually conjectured to be oxygen vacancies (Vo) in many oxide
RRAM devices. It is well known that Vo can act as an effective donor in n-type metal
oxides. Taking HfOx RRAM as an example, ab-initio calculation of the monoclinic and
amorphous HfOx electronic structure [73] indicated that Vo can produce a defect state
within the band gap. Ordered Vo chain can form a transmission channel between two
metal contacts. Experimentally, HR-TEM measurements [74] on HfOx RRAM show that
the CF extends ~20 nm diameter with morphological changes and local atomic disorder.
The electron energy loss spectroscopy (EELS) on oxygen K-edges spectrum revealed the
presence of Vo associated with localized states in the band gap inside the CF region.
However, the composition of CF is not limited to Vo. Sometimes, the CF can be metallic
as well. Another study [75] using HR-TEM and EELS reported observation of a few nm
24
wide metallic CF dominated by metallic Hf in HfOx RRAM. We believe that the nature
of CF depends on the density of Vo. If the density of Vo is low, then the CF may show a
semiconducting nature as electrons are still in localized states in the band gap. If the
density of Vo is sufficiently high, then the CF may show a metallic nature as electrons
are now in extended states forming a sub-band in the band gap. A simple way to
distinguish whether the CF are metallic or semiconducting is to measure the LRS
resistance temperature dependency. If the LRS resistance goes up with the increase of
temperature, the CF are metallic and may consist of metal precipitates. On the contrary, if
the LRS resistance drops with the increase of temperature, CF are semiconducting and
may consist of Vo.
There are many efforts to fit the I-V characteristics of current conduction in the oxide
RRAM in the literature. Most reports show a linear or an Ohmic relationship in the LRS.
However, the conduction characteristics in HRS are quite diverse: Poole-Frenkel
emission (log(I/V)~V1/2) [30][33], Schottky emission (log(I)~V1/2) [21][76], the space
charge limited current (SCLC) characteristic (the Ohmic region I~V, and the Child’s
square law region I~V2) [77][78], were observed in various oxide RRAM devices.
We think that a simple I-V fitting with the aforementioned established model may not
be sufficient to ascertain the conduction in the oxide RRAM. In general, Figure 2.1
shows all the possibilities for an electron transport from cathode to anode [79]: (1)
Schottky emission: thermally activated electrons injected over the barrier into the
25
conduction band; (2) Fowler-Nordheim (F-N) tunneling: electrons tunnel from the
cathode into the conduction band, usually occurs at high field; (3) direct tunneling:
electron tunnel from cathode to anode directly, usually occurs when the oxide is thin
enough (<3 nm). If the oxide has substantial number of traps (e.g., Vo), trap-assisted-
tunneling (TAT) contributes to additional conduction, including the following steps: (4)
tunneling from cathode to traps; (5) emission from trap to conduction band, which is
essentially the Poole-Frenkel emission; (6) F-N like tunneling from trap to conduction
band; (7) trap to trap hopping or tunneling, maybe in the form of Mott hopping when the
electrons are in the localized states or maybe in the form of metallic conduction when the
electrons are in the extended states depending on the overlap of the electron wave
function; and (8) tunneling from traps to anode. Whether any one particular process
above dominates is determined by its transition rate; electrons would seek the fastest
transition (or least resistive) paths among all the possibilities. Therefore, various oxide
RRAM devices may have different dominant conduction mechanisms depending on the
dielectric properties (band gap or trap energy level, etc.), the fabrication process
conditions (annealing temperature, annealing ambient, etc.), and the properties of the
interface between the oxides and the electrodes (interfacial barrier height). The I-V
relationship at the low bias regime is mainly determined by the electron conduction
process for a given configuration of the CF, while at the high bias regime, the motion of
26
atoms (such as oxygen ions/vacancies) would change the configuration of the CF and
trigger a change of the resistance.
Figure 2.1 Schematic of the possible electron conduction paths through a
metal/oxide/metal stack. (1) Schottky emission; (2) F-N tunneling; (3) direct tunneling;
(4) tunneling from cathode to traps; (5) emission from trap to conduction band, which is
essentially the Poole-Frenkel emission; (6) F-N like tunneling from trap to conduction
band; (7) trap to trap hopping or tunneling; and (8) tunneling from traps to anode.
The detailed physical mechanism for resistive switching phenomenon in oxides is still
an active research area. Here we aim to give a general physical picture for the simple
binary oxide RRAM (Figure 2.2). The FORMING process for the fresh samples is similar
as a dielectric soft breakdown [80]. Initially, the Vo density is low. Under the high
27
electric field (>10 MV/cm), the oxygen atoms are knocked out of the lattice, and becomes
oxygen ions (O2-) drift toward the anode, where they are discharged as neutral non-lattice
oxygen if the anode materials are noble metals or react with the oxidizable anode
materials to form an interfacial oxide layer. Thus the electrode/oxide interface behaves
like an “oxygen reservoir” [81]. Meanwhile, Vo in the bulk oxide are generated. The
localized deficiency of oxygen leads to the formation of CF. Usually the as-deposited
RRAM oxide thin films are amorphous or poly-crystalline, and the CF are preferentially
generated along the grain boundaries as revealed by C-AFM [82]. Then the RRAM
device switches to the LRS. During the RESET process, O2- migrate back from the
interface to the bulk oxide either to recombine with the Vo or to oxidize the metallic CF
precipitates and thus partially rupture the CF. For the unipolar switching, Joule heating
by the current thermally activates the O2- diffusion. And O2- diffuse from the interface or
the region around the CFs [83] due to the concentration gradient. Usually the unipolar
switching requires a relatively higher reset current to raise the local temperature around
CF. For the bipolar switching, the interfacial layer may present a significant diffusion
barrier and pure thermal diffusion is not sufficient, thus O2- migration needs to be aided
by the reverse electric field [25]. Nevertheless, in both cases the CF is partially ruptured,
and a Vo-poor region forms and causes a tunneling gap for electrons. Then the RRAM
device switches to the HRS. The residual CF with Vo-rich region is referred as the
“virtual electrode”. In the next SET process, the soft-breakdown occurs in the gap region
28
and the CF reconnect both electrodes. And such SET/RESET loop can repeat for many
cycles. This picture can at best be viewed as a phenomenological description of the
experimental observations for many binary oxide RRAM devices. And the details of the
electron transport and ion dynamics will be discussed in the following sections.
Figure 2.2 Schematic of the switching mechanism of oxide RRAM.
2.2 HfOx Based RRAM Device Fabrication and
Characterization
As a model system, we chose HfOx based RRAM for the study in this thesis simply
because HfOx is one of the most mature RRAM materials explored so far. For example,
H.-Y. Lee et al. [20] reported a TiN/Ti/HfOx/TiN stack with superior performances such
29
as switching speed (~5 ns), switching voltage (<1.5 V), reset current (~25 µA), HRS/LRS
ratio (>100), endurance (>106 cycles), retention (>10 hr @200 °C). Based on this stack,
S.-S. Sheu et al. [38] reported a 4 Mb RRAM chip with 7.2 ns read/write random-access
time and 160 ns 2bit/cell operation time. Recently, B. Govoreanu et al. [26] reported an
ultra-scaled 10 nm×10 nm TiN/Hf/HfOx/TiN stack with superior performances such as
switching speed (~10 ns), switching voltage (<1.5 V), reset current (~50 µA), HRS/LRS
ratio (>10), endurance (>5×107 cycles), retention (>30 hr @250 °C).
We fabricated RRAM devices with TiN/HfOx/AlOx/Pt stack and TiN/HfOx/Pt stack (as
control sample) at Stanford Nanofabrication Facility. The fabrication process flow is as
follows: 50 nm Pt was first deposited by e-beam evaporation on silicon substrate as the
bottom electrode layer. Then 5 nm AlOx was deposited by ALD using TDMA-Al
(tetrakis dimethylamido aluminum Al[N(CH3)2]4) and H2O as precursors at 300 °C, and
then 5 nm HfOx was deposited by ALD using TEMA-Hf (tetrakis ethylmethylamino
hafnium Hf[N(C2H5)(CH3)]4) and H2O as precursor at 220 °C. For control sample, 10 nm
HfOx single layer was deposited using the same process conditions. Then the patterns
with 0.5 µm×0.5 µm ~ 10 µm×10 µm active cell area were defined by photolithography
with photoresist. Then 50 nm TiN was deposited by reactive sputtering and was lifted-off
as top electrode layer. Then the electrical measurements were performed on these
samples, Agilent 4156C semiconductor parameter analyzer was used for DC
measurements and Agilent 81101A pulse generator was used for pulse measurements.
30
The bottom electrode was grounded and the signals were applied to the top electrode in
all the measurements.
The fabricated RRAM devices show the typical bipolar switching behavior. The initial
resistances of these samples are very high (>10 GΩ), and a forming voltage (~8 V) is
needed to trigger the subsequent switching events. Figure 2.3 shows the typical DC I-V
characteristics of the HfOx/AlOx bi-layer samples and HfOx single layer samples. The
devices can SET by a positive bias with 100 µA compliance current was enforced, and
they can RESET by a negative bias. Figure 2.4 shows the HRS and LRS resistance
distribution in (a) and the switching voltage distribution in (b) of the HfOx/AlOx bi-layer
samples and the HfOx single layer samples obtained by 200 DC sweep cycles. The bi-
layer samples show less variation of the HRS resistance and switching voltages. It has
been suggested that the diffusion of Al atoms into HfOx could stabilize the CFs by the
experiments and the ab-initio principle calculation prediction [84], thus it is speculated
that the inter-diffusion of Hf and Al atoms in HfOx/AlOx bi-layer samples may help
improve the switching uniformity. Since the bi-layer samples shows less variation, in the
following part of this chapter, the study was performed on the HfOx/AlOx bi-layer
samples.
31
Figure 2.3 Typical DC I-V characteristics of the HfOx/AlOx bi-layer samples and HfOx
single layer samples. The devices show a bipolar switching behavior.
32
Figure 2.4 The HRS and LRS resistance distribution in (a) and the switching voltage
distribution in (b) of the HfOx/AlOx bi-layer samples and the HfOx single layer samples
obtained by 200 DC sweep cycles.
(a)
(b)
33
In order to assess the switching speed of our RRAM device, we performed the pulse
measurement by connecting the RRAM device in series with the 50 Ω input impedance
of the Tektronix DPO 4054 oscilloscope. The response current waveform was calculated
using the voltage waveform monitored in the oscilloscope divided by 50 Ω. Figure 2.5
shows the transient voltage/current waveform during (a) RESET transition and (b) SET
transition. In (a), the RESET starts with a LRS ~10 kΩ, and then a -2.5 V/50 ns RESET
voltage pulse is applied. The current drops after a wait time around 10 ns, indicating the
RESET event occurs at that moment. At the end, the cell switches to HRS ~1 MΩ. In (b),
the SET starts with a HRS ~1 MΩ, and then a +1.5 V/50 ns SET voltage pulse is applied.
The current increases after a wait time around 30 ns, indicating the SET event occurs at
that moment. At the end, the cell switched to LRS ~8 kΩ. It should be noted that the
SET/RESET speed is actually a function of the applied pulse amplitude as we will
discuss in Section 2.4. If increasing the pulse amplitude, the switching speed can be faster
than the limitation of our measurement set-up (~10 ns). In addition, we can obtain the
energy consumption per SET/RESET programming by integrating the voltage, current,
and time from these waveforms. According to Figure 2.5, the SET energy is ~5.9 pJ and
the RESET energy is ~6 pJ. The energy dissipated in the RESET process is necessary for
the switching because we start with a high LRS current, thus it is unavoidable. On the
contrary, the energy dissipated in the SET process is unnecessary because ideally we can
withdraw the pulse right after the SET occurs. However, considering the variation in the
34
switching time, a SET pulse that is longer than the actual SET time is needed which
causes the waste of energy in the SET process.
Figure 2.5 The transient voltage/current waveform during (a) RESET transition and (b)
SET transition.
(a)
(b)
35
The reliability of our RRAM device is examined. First, the pulse cycling test was
performed. Figure 2.6 shows the HRS and LRS resistance degradation during the
SET/RESET cycling. During the cycling, the HRS resistance keeps decreasing, and about
106 cycles have been obtained before the resistance window collapses. Figure 2.7 shows
the I-V characteristics after 5×105 cycles, and it is clear that the HRS resistance has
decreased significantly as compared with the initial state. The I-V curve becomes non-
linear in LRS and the LRS resistance gets increased as compared with the initial state.
This degradation trend indicated during the cycling more and more Vo are generated in
the oxide making the HRS resistance decrease, meanwhile more and more O2- migrated
towards the TiN electrode where an interfacial TiON tunneling layer may form causing
the non-linear I-V in the LRS. The final failure is stuck at LRS, indicating that there are
eventually too many Vo in the oxide that not sufficient O2- can come back from TiN.
36
Figure 2.6 The HRS and LRS resistance degradation during the SET/RESET cycling.
Figure 2.7 The I-V characteristics after 5×105 cycles
37
Then the retention property of our RRAM device was studied. Figure 2.8 shows the
stability of the device for different resistance states measured at an elevated temperature
(100 °C). The resistance states are monitored by a 0.1 V read voltage every 10 s, and no
significant change of the states is observed for a period of 7200 s (2 hours).
Table 2.1 summarizes the characteristics of our HfOx/AlOx RRAM device. The
characteristics are not the best in the literature, but more than enough for the device
physics study in the next two sections.
Figure 2.8 The stability of the device for different resistance states measured at an
elevated temperature (100 °C).
38
Table 2.1 The characteristics of the HfOx/AlOx RRAM device.
Switching Voltage <3 V
Reset Current ~100 µA
Switching Speed ~10 ns
HRS/LRS ratio 10 kΩ/1 MΩ
Endurance ~106 cycles
Retention >2 hours @100 °C
2.3 Electron Conduction Process in HfOx Based RRAM
2.3.1 I-V Measurements at Various Temperatures
In previous studies of high-k gate materials [85], the leakage current through HfO2 was
usually attributed to Poole-Frenkel emission. Therefore, we first investigated this
possibility as follows. Figure 2.9 shows the Poole-Frenkel fitting results. Figure 2.9 (a)
shows the relation of ln(I/V) versus √V in HRS under the negative bias for different
temperatures. The DC sweep stops at 0.5 V (<the switching voltage) to avoid any
changes to the resistance state unintentionally. At the low bias regime (<0.2 V), the
experimental data deviates significantly from the Poole-Frenkel model prediction. Figure
39
2.9 (b) shows ln(I/V) versus 1/kT for different biases, and if we extract the activation
energy (Ea) from the slope of Figure 2.9 (b), we can plot Ea as a function of √V in Figure
2.9 (c). Extrapolating the curve of Figure 2.9 (c) to the zero bias point, the trap energy
(Et) is extracted to be around 0.08 eV, and from the slope of Figure 2.9 (c), the dielectric
constant (εr) for HfO2 is extract to be about 79. The value of Et~0.08 eV below the
conduction band is too shallow and is not corroborated with the ab-initio calculation
results (~1.2 eV - 2.1 eV) [86], experimental data (~1.5 eV) obtained by Poole-Frenkel
fitting [85] or (~1.2 eV) obtained by spectroscopic ellipsometry [87]. The value of the
extracted dielectric constant εr ~79 is much higher than the known value ~20 for HfO2.
Therefore, both of these two key parameters determined by fitting to a Poole-Frenkel
model are unreasonable. Figure 2.10 shows the temperature dependency of different
resistance states. The current is found to be insensitive to the temperature change, and
similar trends were observed in HfOx RRAM by others [34][88] as well. Therefore, we
suggest that the conduction may be dominated by the tunneling.
40
(b)
(a)
41
Figure 2.9 Poole-Frenkel emission model fitting results: (a) In(I/V) vs. sqrt(V) for
electron injection from TiN under a negative bias. (b) In(I/V) vs. 1/kT to extract the
activation energy (Ea) (c) Extrapolating Ea to zero bias, the trap energy (~0.08 eV) is
extracted from the intersection on the y-axis, and the dielectric constant (~79) is extracted
from the slope. These two parameters are unreasonable compared to their known values.
(c)
42
Figure 2.10 Temperature dependency (In(I/V) vs. 1/kT) for multi-level resistance states at
both positive and negative biases.
Our measured current is neither a strong function of the temperature (ruling out the
possibility of Schottky emission) nor of the electric field (ruling out the possibility of F-N
tunneling). And direct tunneling for a 10 nm thick oxide should be negligible. This leaves
the TAT path (the steps (4)(7)(8) in Figure 2.1) as a most probable conduction
mechanism. Poole-Frenkel emission is essentially one step of the TAT processes (step (5)
in Fig. 1 (b)), which rises from the barrier lowering effect due to the Coulomb attraction
between the positively charged trap center and negatively charged conduction electron
into the conduction band. It should be noted that the Poole-Frenkel model implicitly
assumes that the electron injection from cathode is easy and that there are plenty of
43
electrons available in the filled traps for the subsequent emission. However, this
assumption may not be valid when the electron injection is limited by a significant
interface potential barrier or when the trap density is very high which requires more
electrons to fill the traps than provided [89]. Whether any one particular process
dominates is determined by its transition rate (ν), and the step with the smallest transition
rate limits the whole conduction process. The first step for TAT is step (4), and among
the subsequent de-trapping steps (5)-(7), step (7) has the largest rate. This is because the
rate for thermal activation from the deep trap energy in HfO2 (Et~1.2-2 eV) with ν=
ν0exp(−Et/kT) is much smaller than the rate for the tunneling from trap to trap with ν =
ν0exp(−2R/ξ). Here ν0~1013 Hz, ξ is the electron wavefunction localization length (~0.3
nm), R is the distance between traps (~0.3-0.6 nm) since the trap density is expected to be
very high in the CF. In order to further characterize the TAT process, low frequency
noise (LFN) measurement and AC conductance measurement were performed in the
following.
2.3.2 Low Frequency Noise (LFN) Measurement
LFN measurement is a technique that can electrically characterize the trap-assisted
conduction process in dielectrics [90]. A 1/f α –like power spectral density (PSD) has
been observed for TiO2 RRAM [91], NiO RRAM [92], etc. Here we perform LFN
measurement on our HfOx/AlOx RRAM. The LFN measurement set-up is as follows
(Figure 2.11): Agilent 4156C semiconductor parameter analyzer was used to provide the
44
DC bias. The noise current was fed into in a Stanford Research System SR 570 low noise
current to voltage amplifier, and the output signals were analyzed by a Stanford Research
System SR 760 spectrum analyzer. The electrical measurement was done in a shielded
environment. The SR 570 amplifier has a bandwidth of 1 MHz, and adjustable gain, to
measure LRS current, a gain of 105 Ω was used, and to measure HRS current, a gain of
108 Ω was used. The SR 760 spectrum analyzer was set to analyze the spectrum with 500
times averaging.
Figure 2.11 Schematic of the LFN measurement set-up.
To determine the background noise level of the measurement system, we measured the
noise level of the measurement set-up by applying zero bias on the device. The system
45
noise is introduced by the 60 Hz of the power supply. The measurement system’s power
spectral density (PSD) level is measured around 10-22~10-24 A2/Hz. The system noise
level actually depends on the gain amplitude used in the amplifier: for measuring LRS, a
lower gain 105 was used, leading to a PSD level ~10-22 A2/Hz; for measuring HRS, a
higher gain 108 was used, leading to a PSD level ~10-24 A2/Hz. In either case, the
measured memory device noise is about 3 orders larger than the measurement system’s
noise. Therefore, the effect of the measurement set-up is negligible. The theoretical value
of the equivalent resistors’ thermal noise (4kBT/R) is even below the measurement
system noise level. Figure 2.12 shows the RRAM device noise, measurement system’s
noise, and equivalent resistor’s thermal noise for LRS (a) and HRS (b).
(a)
46
Figure 2.12 The RRAM device noise, measurement system’s noise, and equivalent
resistor’s thermal noise for LRS (a) and HRS (b).
Figure 2.13 shows the relative noise current fluctuation in the time domain for
different resistance states. The higher HRS levels can be obtained by increasing the reset
stop voltages in a DC sweep. Generally, the higher the resistance state is, the larger the
relative fluctuation is. Figure 2.14 shows the normalized PSD (Si/I2) in the frequency
domain for different resistance states. Here the normalization is done by dividing the PSD
value (Si) by the square of the average current (I2). It is seen that the higher the resistance
state is, the larger the normalized PSD is, which is in agreement with the data in the time
domain. Also it is seen that for LRS the slope index α is close to 1, while for HRS there is
(b)
47
a cutoff frequency above which α changes from 1 to 2. Similar LFN behavior that shows
a slope index change was also observed in other RRAM devices [91]. Figure 2.15 shows
the PSD (Si) as a function of the squared DC bias for LRS (the inset) and HRS
respectively. It is seen that the PSD (Si) in LRS follows a linear relation with the squared
DC bias while that in HRS follows a super-linear relation with the squared DC bias,
which is consistent with the I-V characteristics. As a result, the normalized PSD (Si/I2)
for both HRS and LRS are almost independent of the DC bias as shown in Figure 2.16,
suggesting that there is no optimal bias point for maximum signal to noise ratio (SNR)
for the read operation.
Figure 2.13 The relative noise current fluctuation in the time domain for different
resistance states.
48
Figure 2.14 The normalized PSD (Si/I2) in the frequency domain for different states.
Figure 2.15 The PSD (Si) as a function of the squared DC bias for LRS (the inset) and
HRS respectively.
49
Figure 2.16 The normalized PSD (Si/I2) as a function of the DC bias voltage.
In the following, we discuss the conduction mechanism that is revealed by the above
LFN characterization. In general, the electron trap/detrap processes give rise to noise
current on the top of the steady state current of the RRAM devices. In the three steps in
TAT, the tunneling between the electrode and traps is the bottleneck of the DC
conduction process (especially in HRS) because: 1) the electron injection/ejection is
limited by a significant interfacial potential barrier as the case of metal/oxide interface,
leading to a slow tunneling rate between the electrode and traps; 2) the trap density of the
remaining un-ruptured section of the CF is high, leading to a fast trap-to-trap tunneling
rate within the residual CF. The relaxation time τ in the trap/detrap process, is then
determined by the transition time of the bottleneck: tunneling between the electrode and
50
traps. The Wentzel-Kramers-Brillouin (WKB) approximation is used to calculate this τ as
Eq. 2.1.
τ = τ0/fFermi−Dirac(Eb − Et) ∙ exp(γ ∙ d) (2.1)
where d is the distance from electrode to trap, τ0 is the pre-exponential time factor
(~10-14 s [93]), γ = 2√2m∗Et/ℏ is the WKB approximation factor for the transmission
probability at low bias, trap energy Et=1.6 eV [85] in HfO2, TiN/HfO2 interface potential
barrier Eb=1.9 eV [94], and effective mass m*=0.1m0 for HfO2 [85]. For a specific τ, the
PSD of the noise current Si(ω) can be expressed in a Lorentzian function as Eq. 2.2 [90].
Si(ω) = (ΔI)2 ∙4τ
1+ω2τ2 (2.2)
where ω=2πf is the angular frequency, (ΔI)2 is the root mean square (RMS) value of
the noise current. And if the τ has a probability distribution p(τ), the PSD form is
modified to be Eq. 2.3.
Si(ω) = ∫ (ΔI)2 ∙4τ
1+ω2τ2∙ p(τ)dτ
τ(max)
τ(min) (2.3)
where τ(min) is the relaxation time determined by the shortest tunneling distance, and
τ(max) can be considered to be infinite if we consider the direct tunneling from one
electrode to another across entire 10 nm thick oxide is negligible.
51
Figure 2.17 shows the Lorentzian function for different tunneling distances between
the electrode and traps. In LRS, CF connect both electrodes, thus electrons can tunnel
from the electrode to all the traps nearby with various relaxation times. If we assume a
spatially uniform distribution of traps in LRS, p(R) = nt ∙ 4πR2, with a trap density nt,
by changing the integration variable: p(τ) = p(R)dR/dτ , we can complete the
integration at the limit when τ(min) is approaching zero for the case of LRS, and obtain
the result of Eq. 2.4.
Si(ω) = (ΔI)2 ∙ 8π2nt/γ ∙ Rω2 /ω (2.4)
where Rω = 1/γ ∙ ln(1/ωτe−t0 ) is the characteristic tunneling distance at frequency ω,
which has only a weak dependence on ω. With respect to the frequency, Si(ω)~1/ωα, here
the slope index 𝛼 = 1 + 2/ln(1/ωτ), sinceωτ ≪ 1at the LFN regime (f < 3 kHz), α
approaches 1. Intuitively speaking, in LRS the electrons have multiple choices when
they tunnel from the electrode to the traps nearby, and the contribution from all these
transitions will smooth the 1/f 2 Lorentzian function thus the envelope leads to 1/f α-like
(α~1) LFN behavior. In HRS, the CF is partially ruptured and the shortest distance
between the first trap and the electrode causes a minimum τ, thus ω=1/τ(min) corresponds
to the cutoff frequency in the Lorentizian. Therefore, the cutoff frequency becomes an
indicator of the ruptured CF length. For a typical HRS range (500 kΩ-50 MΩ), the
ruptured CFs length is estimated to be 1.5 nm-2 nm.
52
Figure 2.17 Lorentzian function 4τ/(1 + ω2τ2) for different τ. Single Lorentzian is 1/f 2,
and the envelope of multiple Lorentzian is 1/f. The cutoff frequency corresponding to a
shortest electrode-to-trap tunneling gap distance (~2 nm) is shown (the dash line).
2.3.3 AC Conductance Measurement
In addition to LFN measurement, we also performed the impedance spectroscopy on
our RRAM device. Impedance spectroscopy is a technique that can separate the electrical
components for electronic conduction in dielectrics, including resistance, inductance, and
capacitance and reveals the dielectric dispersion in the frequency domain [95].
Impedance spectroscopy has been employed to characterize NiO RRAM [96], and TiO2
RRAM [97], etc. Here we perform impedance spectroscopy on the HfOx/AlOx RRAM.
53
We further extract the AC conductance as a function of applied small signal frequency to
investigate the conduction mechanism. Impedance (Z) spectroscopy was carried out by
applying a 10 mV AC small signal (100 Hz to 1 MHz) to the RRAM device through
Agilent 4284 LCR-meter. Figure 2.18 shows the Nyquist plot (-Im(Z) vs Re(Z)) for HRS
and LRS. A semicircle in the Nyquist plot suggests the RRAM cell in HRS can be
modeled as a resistor (R) and a capacitor (C) in parallel:
Z =R
1+ωR2C2− j
ωR2C
1+ωR2C2 (2.5)
Note that in the Nyquist plot, the diameter of the semicircle is the resistance R, and at
the characteristic frequency ω=1/RC, the locus of the data points in the Nyquist plot
reaches the maximum value (-Im(Z)=R/2) of the negative imaginary impedance axis. C is
measured to be 1.15 pF for our oxide stack (10 nm thick and 10×10 µm2 in size), and C is
found to be independent on the resistance states. As an estimate, the characteristic
frequency for HRS=30 MΩ is about 4.6 kHz. In the inset of Figure 2.18, the points that
cluster near the Re(Z) axis suggests the RRAM cell in LRS is shunted by CF of a low
resistance ~20 kΩ. The characteristic frequency in this case becomes 6.9 MHz, which is
beyond the measurement frequency range limit (<1 MHz). Therefore, the locus of the
data points in the Nyquist plot cannot reach the maximum value (-Im(Z)=R/2).
54
Figure 2.18 The Nyquist plot (-Im(Z) vs Re(Z)) for HRS and LRS.
We further extract the conductance as a function of the small signal frequency from the
impedance spectroscopy. Figure 2.19 shows the total conductance spectrum in LRS and
HRS obtained under various DC biases. It is seen that LRS conductance is independent of
frequency, while HRS conductance has a corner frequency beyond which the
conductance rises. Figure 2.20 shows the total conductance spectrum in different
resistance levels in HRS. It is seen that the higher the HRS resistance is, the lower the
corner frequency is.
55
Figure 2.19 The total conductance spectrum in LRS and HRS under various DC biases.
Figure 2.20 The total conductance spectrum in different resistance levels in HRS.
56
The AC conductance in the HRS is obtained by subtracting the DC component from
the total conductance. Figure 2.21 shows the AC conductance spectrum (a) for various
DC biases at a particular HRS level and (b) for different HRS levels at a particular DC
bias. It is seen that a universal f β-like (with β~2) AC conductance is observed
independent of the DC bias and also independent of the resistance of the different HRS
states.
57
Figure 2.21 The AC conductance spectrum (a) for various DC biases at a particular HRS
level and (b) for different HRS levels at a particular DC bias.
58
Next, we discuss the conduction mechanism that is revealed by the AC conductance
measurement. The key observation is a rise of conductance beyond a certain corner
frequency for the HRS. In general, the increase of conductance with AC small signal
frequency can be attributed to the dielectric relaxation process, which typically has
several origins: electronic polarization, ionic polarization, dipolar polarization [98].
However, all of the aforementioned processes occurs at very high frequency (>1 GHz).
Therefore, the only possibility that can cause the rise of AC conductance in the medium
frequency range (kHz-MHz) is the electron hopping (trap-to-trap tunneling) contribution
[98]. This relaxation is often described in terms of the following Debye form [99]:
σ(ω) = 𝛼 ∙ω2τ
1+ω2τ2(2.6)
where σ(ω) is the AC conductance as a function of the angular frequency ω, 𝛼 =
e2d2/12kT is the polarizability due to electron hopping between a pair of sites [99], here
e is the electronic charge, and d is the hopping distance. τ is the transition time for
electron hopping between a pair of sites. As a rough estimate, for hopping (trap-to-trap
tunneling), τ = t0exp(2d/ξ) = 2 × 10−12s . Here t0~10-13 Hz, ξ is the electron
wavefunction localization length (~0.3 nm), d is the distance between traps (assuming
d~0.5 nm for traps in CFs). Therefore, in the AC conductance measurement regime (kHz-
MHz), ωτ≪1, thus σ(ω) ~ ωβ with a slope index β~2. It is noted that the trap-to-trap
tunneling that contributes to the AC conductance should be those hoppings that are
59
confined within the nearest neighbor traps with a single τ, otherwise the trap-to-trap
tunneling with different τ would smooth Eq. (2.6) to be σ(ω) ~ ωβ with a slope index β~1.
We have to point out that the measured f β -like (β~2) AC conductance in our device is
not a result of the lead series resistance as suggested in [100], because we did not observe
the saturation of AC conductance or the cutoff frequency due to the lead series resistance
that were observed in [100].
To summarize, Figure 2.22 shows a schematic of the DC and AC conduction processes
in RRAM device. In HRS, the CF is partially ruptured and a gap region lack of traps is
formed near one electrode, leaving behind the residual CF that is rich in traps. The
electrode-to-trap tunneling across the gap region causes the DC noise current. Unlike DC
conduction that is associated with conducting paths extending to both electrodes, AC
conduction is based on the pair approximation of the transition between two sites
responding to the external AC field. As long as the traps within the residual CF can
interact with each other, no matter how long the ruptured CF is (which determines for the
DC resistance level), the AC conductance (and the value of β) should be independent on
the DC bias or the HRS resistance (see Figure 2.21). However, for AC conductance to be
observable, it must be larger than its DC component above a certain corner frequency.
Since AC conductance is independent of the resistance of the multi-level states, a lower
corner frequency correlates with a longer transition time for electron tunneling between
60
the electrode and traps for DC conduction, which corresponds to a larger tunneling gap in
higher HRS.
Figure 2.22 Schematic of the DC and AC conduction processes in RRAM device.
2.4 Ion Dynamics in HfOx Based RRAM
2.4.1 Voltage-Time Relationship in Switching Dynamics
What has been discussed in Section 2.3 is related to the electronic process in either
HRS or LRS, the resistive switching between the HRS and LRS should be related to the
ionic process. There is a well-known voltage-time dilemma of the requirement for fast
switching (~ns) and long time retention (~years) in the RRAM devices [70], which means
that the switching mechanism has a very strong nonlinearity in the electric field
dependence. Here we measure the voltage-time relationship for our HfOx/AlOx RRAM
61
device during both SET and RESET process, and discuss the physical origin of such
nonlinearity which is caused by the ion dynamics.
Figure 2.23 shows the pulse amplitudes needed to successfully trigger the SET/RESET
switching at fixed pulse widths. The trigger is successful if the device meets the pre-
defined target LRS/HRS resistances. Although the switching variations are noticeable,
the general trend is that the switching time for both SET and RESET exponentially
decreases with the increase of the pulse voltage. Similar exponential voltage-time
relationship has been observed in several other RRAM devices, e.g. ZnOx [101], TaOx
[102]. The origin of this universal relationship in the switching dynamics can be
attributed to the ion migration process through the potential wells of the oxide matrix
[103]. The drift velocity of the ion migration is given by [103]:
v = a0 ∙ f ∙ exp (−Em
kT) ∙ sinh (γ ∙
a0
L∙qV
kT)(2.7)
where f is the atomic attempt-to-escape frequency (~1013 Hz [103]), Em is the ion
migration energy (~1.5-1.9 eV for HfOx RRAM [100][104]), a0 is the atom spacing in
oxides (~0.25 nm), L is oxide thickness, q is electron charge, k is Boltzmann constant.
The local field acceleration parameter γ is introduced due to the strong polarizability in
high-k dielectrics [105]. Since the ion migration velocity has a hyperbolic-sinusoidal
dependence on the electric field, the corresponding growth/rupture evolution rate of CF
also has a hyperbolic-sinusoidal dependence on the electric field. When the electric field
is large (typically during switching F>1 MV/cm), the hyperbolic-sinusoidal dependence
62
reduces to the exponential dependence, leading to the universal voltage-time relationship
observed above. It should be noted that although this exponential relationship is observed
in the typical programming timescales (~ns to ~ms), it does not hold under certain
extreme conditions. When the electric field is much smaller compared to the
characteristic field F0 = 2kT/qa0 (~10 kV/cm), the hyperbolic-sinusoidal dependence
reduces to the linear dependence. That means without bias the retention time should be
infinite if only the drift component of the ion migration is considered. However, in reality
the retention time is finite due to the diffusion component of the ion migration. When the
electric field is sufficiently large, it may be difficult to further increase the switching
speed because the limiting factor of the switching time is no longer the ion migration
process but the electrochemical reaction process, e.g. there are already plenty of O2-
available for recombination with Vo during the RESET.
63
Figure 2.23 Measured voltage-time relationship: pulse amplitudes needed to successfully
trigger the SET/RESET switching at the some fixed pulse widths. The success of the
trigger is defined to meet pre-defined target LRS/HRS resistances (20 kΩ/1 MΩ).
2.4.2 Energy-Efficient Programming Scheme for Multi-bit Operation
In general, the RRAM devices can show multi-bit operation capability. It was found
that modulation of LRS resistances by varying set compliance current was not repeatable
in the single RRAM cell without the selection transistor. The reason may be the transient
current overshoot problem during the sharp transition in the SET process. Therefore, here
we focus on the modulation of HRS resistances by controlling the RESET programming
conditions. Figure 2.24 shows the DC I-V characteristics of HfOx/AlOx RRAM by
64
different RESET stop voltages (-2.1 V, -2.7 V, and -3.3 V). Three levels of HRS were
achieved.
Figure 2.24 The DC I-V characteristics of HfOx/AlOx RRAM by a different RESET stop
voltages (-2.1 V, -2.7 V, and -3.3 V).
Then we further explore this multi-level capability in the context of pulse cycling for
practical applications (Figure 2.25). Figure 2.25 (a) shows three levels of HRS can be
obtained by fixed pulse width (50 ns) but different pulse amplitudes (-2.3 V, -2.6 V, -2.9
V). Figure 2.25 (b) shows that similar three levels of HRS can also be obtained by fixed
pulse amplitude (-2.3 V) but different pulse widths (50 ns, 500 ns, 5 µs). The equivalence
of the above two programming schemes suggests that the final states are not only
65
determined by the applied voltage but also the duration time of the RESET programming.
Therefore, two programming schemes are available to achieve multiple HRS: 1) linearly
increase the programming pulse amplitude; 2) exponentially increase the programming
pulse width. Both schemes can effectively achieve target resistance, and their
equivalence is essentially caused by the exponential voltage-time relationship as
discussed above.
(a)
66
Figure 2.25 (a) Three levels of HRS obtained by fixed pulse width (50 ns) but different
pulse amplitudes (-2.3 V, -2.6 V, -2.9 V). (b) Similar three levels of HRS obtained by
fixed pulse amplitude (-2.3 V) but different pulse widths (50 ns, 500 ns, 5 µs).
The next question is which programming scheme is a better scheme in terms of energy
efficiency. To address this question, transient voltage/current waveforms were measured
for these two programing schemes. Figure. 2.26 shows that to achieve a target resistance
~50 kΩ from an initial resistance ~10 kΩ, two pulse schemes were used: one is applying -
2.3 V/50 ns; the other is applying -2 V/500 ns. Both transient current starts from similar
value and end with similar value, indicating the effect of the two schemes is the almost
same on the cell resistance. By integrating the voltage, current and time, we obtain the
(b)
67
energy consumption for the first scheme (-2.3 V/50 ns) is about 7.4 pJ and for the second
scheme (-2 V/500 ns) is about 60.9 pJ. Therefore, using larger but shorter pulse is
preferred to achieve both faster and more energy-efficient programming.
Figure 2.26 Transient voltage/current waveform for the two RESET programming
schemes. The first scheme: -2.3 V/50 ns; The second scheme: -2 V/500 ns. The initial
resistance is ~10 kΩ, and the final resistance is ~50 kΩ. The energy consumption for the
first scheme (-2.3 V/50 ns) is about 7.4 pJ and for the second scheme (-2 V/500 ns) is
about 60.9 pJ.
68
2.5 Summary
In this chapter, we investigated the physical mechanism of resistive switching
phenomenon in binary oxides. The resistive switching is attributed to the conductive
filament (made up of oxygen vacancies) formation and rupture in the oxides. As a model
system for device physics study, HfOx based RRAM devices were fabricated and device
performances such as switching voltage and resistance distribution, switching speed,
endurance and retention were characterized. By techniques such as I-V measurement at
various temperature, LFN measurement, AC conductance measurement, the TAT was
identified to be the dominant conduction mechanism. An exponential voltage-time
relationship was found between the switching time and the applied voltage, suggesting
the oxygen ion migration dynamics. Inspired by the voltage-time relationship, an energy-
efficient programming scheme was also proposed for multi-level operation.
69
Chapter 3
RRAM Device Modeling and Simulation 3
3.1 Kinetic Monte Carlo (KMC) Modeling
In the previous chapter, we have obtained understandings of the RRAM device physics
through a series of experiments, which sets a solid foundation for our modeling work in
this chapter. As illustrated in Section 2.1, for the typical bipolar switching RRAM, during
the FORMING/SET process, O2- are pulled out from lattice and Vo are generated and the
CF forms connecting both electrodes. Then the current flow through the CF. During the
RESET process, the CF is partially ruptured by the recombination of Vo with the O2- that
migrate from the oxygen reservoir at the electrode/oxide interface, thus a tunneling gap is
formed between the electrode and the residual CF. In order to simulate the above physical
picture, our strategy is to decouple the electronic process and the ionic process. For the
electronic process, we consider that TAT is the dominant conduction mechanism at low
bias regime in both HRS and LRS, in which case the electrons are in the localized states
where Vo are far away from each other. Two additional conduction mechanisms are
taken into account as well: the F-N tunneling at high bias regime in HRS, and the
metallic conduction in LRS, in which case the electrons are partially in the extended
states where Vo are very close to each other. The metallic conduction is implemented by
3 The work in this chapter was done in part by collaboration with Dr. Ximeng Guan, who
was a post-doctoral researcher at Stanford.
70
a resistor network model composed of non-linear resistors with resistance that
exponentially depends on the distance between adjacent Vo. For the ionic process, we
discrete the oxide matrix and track the evolution path of every Vo and O2- stochastically.
Figure 3.1 shows the developed KMC simulation flow: Starting from an initial Vo
configuration, the total current consisting of TAT current, F-N current, and metallic
current is first calculated. Then the local field and local temperature are calculated by the
resistor network and the Fourier heat transfer equation, respectively. Finally, the Vo
configuration is updated using a Monte Carlo method by calculating the event probability
of the Vo generation/recombination and O2- migration based on the activation energy of
these processes. The local temperature and local field play an important role for
determining the CF shape because these event probabilities are both field and temperature
dependent. The simulations are performed on a 2D matrix, and the parameters are
calibrated with the experimental data from our HfOx based RRAM.
Figure 3.1 The KMC simulation flow
71
3.1.1 TAT solver
Figure 3.2 shows the TAT process in the oxide RRAM.
Figure 3.2 The TAT process in the oxide RRAM.
The electron current continuity equation for TAT is given by Eq. 3.1 [106]:
dfn dt⁄ = (1 − fn)∑ rnmfmm − fn ∑ (1 − fm)rmn + Rcn(1 − fn) − Rnafnm (3.1)
where fn is the nth trap’s electron occupancy probability, rmn is the hopping rate from
the mth trap to the nth trap, rnm is the hopping rate from the nth trap to the mth trap, Rcn is
the tunneling rate from the cathode to the nth trap, Rna is the tunneling rate from the nth
trap to the anode, and ∑m stands for the summation over all the traps except the nth trap.
Here the hopping rate between traps takes the Mott hopping form [107] of Eq. 3.2:
rhopping = ν0exp(−2d/ξ + q∆V/kT) (3.2)
72
d is the distance between the two traps, ξ is the electron wavefunction localization
length ~0.3 nm, ν0~1013 Hz, q is the electron charge, ΔV is the voltage difference
between the two traps, kT is the thermal energy. Here the tunneling rate from the cathode
to the trap (Rc) and from the trap to the anode (Ra) is calculated by the WKB
approximation form in Eq. 3.3 and Eq. 3.4:
Rc = ν0 ∫ Ffermi(E)exp(−2/ℏ∫ √2m∗(Eb − E − qV(x)L
0)dx)
∞
Et−qV(L)dE (3.3)
Ra = ν0 ∫ (1 − Ffermi(E))exp(−2/ℏ∫ √2m∗(Eb − E + q(V − V(x)L
0)dx)
Et−qV(L)
−∞dE
(3.4)
E is the energy with respect to the Fermi-level in the electrode, Eb is the
electrode/oxide interface barrier height, Et is the trap energy below the conduction band
of the oxide, L is the distance between the trap and the electrode, m* is the effective mass
for HfO2 ~ 0.1 m0 , ν0~1014 Hz, ℏ is the reduced Planck’s constant, V(x) is the voltage
potential at the distance x from the electrode, V is the external applied voltage.
At the steady state, dfn dt⁄ = 0, and we need to self-consistently solve the m non-
linear equations like Eq. 3.1 (m is the total number of the traps in the oxide). The
Newton-Raphson iteration scheme was used for solving such series of non-linear
equations. After solving these equations, we obtain the electron occupancy probability at
each trap. Then the current flowing through the cell can be calculated by evaluating the
electron flux through a cross section, e.g. from the cathode to all the traps in the oxide:
I = −q∑ (Rcn(1 − fn)n − Rnafn) (3.4)
73
First let us apply the TAT solver for a 1D Vo chain. Consider the case in which there is
only one chain of Vo between the two electrodes of an RRAM cell. Assuming that the Vo
chain is connected with the anode, while it is disconnected from the cathode with a
tunneling gap. The electron from the cathode must tunnel through the gap before it hops
through the Vo chain to the anode on. Therefore the tunneling from the cathode to the
first Vo in the Vo chain across the gap becomes the bottleneck of the conduction. Since
the tunneling probability depends on the gap size exponentially, the current through the
cell has an exponential dependence on the gap distance, which is verified by the
simulation results of the TAT-solver (Figure 3.3). Therefore, any variation in the gap
distance is expected to have a significant impact on the HRS resistance.
Figure 3.3 I-V of 1D Vo chain for different gap distances simulated by TAT solver. The
inset shows current exponentially decreases with increasing gap distance, which is the
main cause of the HRS variation.
74
Furthermore, we examined the electron occupancy probability of the traps for this 1D
Vo chain case. Figure 3.4 shows the electron occupancy probability in the traps (a) for a
complete Vo chain connecting both electrodes (representing LRS) and (b) for a ruptured
Vo chain with a gap (representing HRS). It is observed that an increasingly negative bias
on the cathode drives the electrons to the anode. In other words, the traps near the
cathode tend to be electron-depleted in order to accept sufficient electron flux from the
cathode to maintain the current continuity. The depleted Vo becomes more positively
charged, hence it increases the capture cross-section with O2-, thus the recombination
becomes more favorable. Therefore the Vo near the cathode have a higher probability to
be recombined during the RESET, thus the CF tends to rupture near the cathode [107].
Figure 3.4 The electron occupancy probability in the traps in the 1D Vo chain (a) for a
complete Vo chain connecting both electrodes (representing LRS) and (b) for a ruptured
Vo chain with a gap (representing HRS).
(b)
(a)
75
3.1.2 Resistor Network
A resistor network model was developed to calculate the metallic component of the
current and also to estimate the local field and local temperature profile. Figure 3.5 shows
the schematic of the resistor network: each node in the network represents an oxygen
atom site in the oxide matrix. The node can be a red Vo site or a blue lattice oxygen (OL)
site. Then the resistors between the two nodes are defined in this exponential way:
R =R0
n∙ exp(n ∙
a0
d0) (3.5)
where R0 (105 Ω) and d0 (0.15 nm) are fitting parameters for characteristic resistance
and distance, a0 is the atom spacing (0.25 nm), and n stands for the nearest Vo at the nth
atom spacing away. After constructing the network, the Kirchhoff Voltage Law (KVL) is
solved on the network, which gives the metallic current and the local field profile.
Figure 3.5 Schematic of the resistor network: each node in the network represent an atom
site in the oxide matrix. The node can be a red Vo site or a blue lattice oxygen (OL) site.
76
Based on the resistor network’s local voltage/current profile, the local power
dissipation map P(x,y) can be constructed by calculating the local Joule heating on the
resistors. Then the local temperature profile (T) can be solved by the Fourier heat
equation:
dT
dt= κ(
∂2T
∂x2+
∂2T
∂y2) +
P(x,y)
Cth (3.6)
where κ is the thermal diffusivity, and Cth is the thermal capacitance. At steady state,
dT/dt=0. The 2D simulation was done in a 20 nm (wide) × 10 nm (thick) cell. Figure 3.6
shows an example of the simulated local electric potential in HRS with a gap between top
electrode and residual CF. The field is enhanced at the gap region, thus the CF tends to
reconnect there during the next SET cycle. Figure 3.7 shows an example of the simulated
local temperature in LRS when CF connects both electrodes. The elevated temperature
due to Joule heating enhances the O2- migration during the next RESET cycle. The
temperature rise is only noticeable in LRS and the heat generation in HRS is negligible.
Figure 3.6 An example of the simulated local electric potential in HRS with a gap
between top electrode and residual CF.
77
Figure 3.7 An example of the simulated local temperature in LRS when CF connects both
electrodes.
The local potential profile is forwarded as an input to the TAT solver. Figure 3.8
shows the simulated I-V curve for a device with gap ~1 nm considering multiple
conduction mechanisms contribute to the total current. The F-N current only plays a role
at a high negative bias.
78
Figure 3.8 Simulated I-V curve of a 1D Vo chain in RRAM cell with 1 nm tunneling gap
considering multiple conduction mechanisms.
3.1.3 KMC Module for Ionic Process
What we described above is how we model the electronic process in the RRAM. In
order to model the ionic process, we discretize the oxide into a grid and track the
evolution path of every Vo and every O2- in this grid. The event probability (P) of the Vo
generation/recombination and O2- migration is calculated based on the activation energy
(Ea) of these processes and the local field (F) and local temperature (T) in this way:
P(F, T, t) =t
t0exp(−
Ea−γa0F
kT) (3.7)
79
where t is the simulation time step (the time step should be small enough to ensure that
the P <<1), t0 is the atomic vibration time constant (~10-13 s [103]). Ea is the activation
energy, and it may have different values for Vo generation/recombination and for O2-
migration with the typical range 0.5 eV~2 eV, a0 is the atom spacing in oxides (~0.25
nm), k is Boltzmann constant. The local field acceleration parameter γ is introduced due
to the strong polarizability in high-k dielectrics [105]. To determine these probabilities,
the local field and local temperature profile obtained from the resistor network model is
used as an input to the KMC module. Then a Monte Carlo method is used to determine
the success of these events, and the Vo configuration is updated accordingly. Since we
trace every Vo and every O2-, we need to set up and maintain a list of the Vo’s
coordinates and a list of the O2- coordinates in the oxide grid. Figure 3.9 shows the
algorithm of KMC module.
80
Figure 3.9 The algorithm of KMC module.
1. Determine new Vo generation: Scan the oxide grid, if there is no Vo on the site,
calculate the Vo generation probability Pg, and then throw in a random number R
ranging (0,1), if R falls into (0, Pg), then a new Vo is generated; add this Vo into
the list of Vo. Meanwhile a new O2- is also generated; then determine the O2-
migration according the algorithm in the footnote below, and add this O2- into the
list of O2-.
2. Determine Vo and O2- recombination: Scan the list of O2-, and check the list of
Vo to see if they share the same coordinate; if yes, calculate the Vo
recombination probability Pr, and then throw in a random number R ranging
(0,1); if R falls into (0, Pr), then this Vo and this O2- annihilates, delete them in
the list of Vo and the list of O2-; if R falls into (Pr, 1), determine the O2- migration
according the algorithm in the footnote below, and update the list of O2-.
3. Determine O2- migration: Scan the list of O2-, and check the list of Vo to see if
they share the same coordinate; if no, determine the O2- migration according
algorithm in the footnote below, and update the list of O2-.
Footnote: calculate the O2- migration probabilities toward 4 directions (Pleft, Pright,
Pup, Pdown), throw in a random number R ranging (0,1), if R falls into (0, Pleft), O2-
migrates to the left adjacent site; if R falls into (Pleft, Pleft+ Pright), O2- migrates to the
right adjacent site; if R falls into (Pleft+ Pright, Pleft+ Pright+ Pup), O2- migrates to the up
adjacent site; if R falls into (Pleft+ Pright+ Pup, Pleft+ Pright+ Pup+ Pdown), O2- migrates to
the down adjacent site; if R falls into (Pleft+ Pright+ Pup+ Pdown, 1), O2- remains at the
current site.
81
By integrating the TAT solver, resistor network, and KMC module, our KMC
simulator can simulate many experimental observations. In the following, we utilize our
simulator to study the current overshoot, variability, and reliability problems in RRAM
device.
3.1.4 Simulation of Current Overshoot
Current overshoot in RRAM refers to the experimental observation that the RESET
current is larger than the FORMING/SET compliance current [108]. Figure 3.10 shows
the simulated I-V with overshoot effect for three cases: 1) FORMING with a RC time
constant τ=100 ns; 2) FORMING with τ=10 ns; 3) SET with τ=100 ns. (Note 1 pF
parasitic capacitance and 100 kΩ LRS can lead to 100 ns τ). Figure 3.11 shows the
simulated voltage drop on the RRAM as a function of time during the overshoot period.
Due to the parasitic capacitance, the voltage dropped on RRAM cannot follow the abrupt
resistance change. Instead, it exponentially decays after the compliance current is
reached. Figure 3.12 shows the simulated current during the overshoot period. It is seen
that the transient current of case 1) overshoot to a level higher than the pre-defined
compliance current.
82
Figure 3.10 Simulated I-V with overshoot: 1) FORMING with RC time constant τ=100
ns; 2) FORMING with τ=10 ns; 3) SET with τ=100 ns. The compliance is 10 µA.
Figure 3.11 Simulated voltage drop on the RRAM as a function of time during the
overshoot period.
83
Figure 3.12 Simulated current during the overshoot period. The compliance is 10 µA.
To understand what happens inside the RRAM cell during the overshoot period, the Vo
configuration of the three cases are tracked. Figure 3.13 shows the evolution of the CF
shape for the FORMING/RESET/SET cycles using KMC simulator. For a fresh sample, a
few intrinsic Vo (in pink color) exist at the grain boundary (subfigure a). Then we apply
FORMING conditions on the RRAM cell. At the onset moment for case 1), the O2- (in
blue color) start migrating towards the top electrode which is positively biased (subfigure
b). At the end of the overshoot period, the CF grows wider laterally (subfigure c),
suggesting that more Vo are undesirably generated due to the high voltage and high
temperature during the overshoot period. At the onset moment for case 2), similarly the
O2- (in blue color) start migrating towards the top electrode (subfigure d). At the end of
84
the overshoot period, the lateral growth of CF is limited (subfigure e), suggesting that the
smaller τ effectively shortens the high voltage and high temperature period, thus the
overshoot effect is suppressed. For case 1), we apply the RESET conditions on the
RRAM cell. O2- at the interface migrate back and partially rupture CF (subfigure f). Then
we continue applying SET conditions on the RRAM cell, which is the case 3). At the
onset moment for case 3), only a portion of the CF tip is connected to the electrode
(subfigure g). At the end of the overshoot period, the lateral growth of CF is also limited
(subfigure h), suggesting that the overshoot in the SET process is also suppressed as
compared with the FORMING process due to a lower voltage across the RRAM cell
during the overshoot transient period, although the overshoot period length is the same as
case 1). To summarize, eliminating the FORMING process and decreasing the parasitic
capacitance by integrating the RRAM cell with a selection transistor or a current limiter
with a saturating I-V characteristics is helpful for overcoming the overshoot problem.
85
(a) (b)
(c) (d)
(e) (f)
86
Figure 3.13 The evolution of the CF shape for the FORMING/RESET/SET cycles using
KMC simulator for (a) fresh sample; (b) Onset moment of FORMING with τ=100 ns; (c)
LRS after FORMING with τ=100 ns; (d) Onset moment of FORMING with τ=10 ns; (e)
LRS after FORMING with τ=10 ns; (f) RESET with τ=100 ns; (g) Onset moment of SET
with τ=100 ns; (h) LRS after SET with τ=100 ns. Pink dots are Vo. Blue dots are O2-.
3.1.5 Simulation of Variability
Our KMC simulator can continuously cycle the RRAM devices to obtain the statistics
of the switching. Figure 3.14 shows the simulated I-V curves during the repeated 100-
cycle DC sweep. The switching variations are well reproduced. Figure 3.15 shows (a) the
simulated resistance distribution and (b) switching distribution during the repeated 100-
cycle DC sweep. The simulation data here aims to reproduce the experimental data in
Figure 2.4.
(g) (h)
87
Figure 3.14 Simulated I-V curves during the repeated 100-cycle DC sweep.
88
Figure 3.15 Simulated (a) resistance distribution and (b) switching distribution during the
repeated 100-cycle DC sweep.
(b)
(a)
89
In the experimental data in Figure 2.4 (a) and the simulation results in Figure 3.15 (a),
it is observed that the LRS variation is less than the HRS variation. This is probably
because in HRS the current is exponentially dependent on the ruptured CF length, thus
any small variation of the tunneling gap distance may be magnified to be a large variation
of the HRS resistance. Therefore, we see remarkable tail bits (bits with lower resistance)
in the HRS resistance distribution as highlighted in Figure 3.15 (a). We correlate these
tail bits with their corresponding Vo configuration in the KMC simulator, and reveal that
the tail bits correspond to the existence of Vo in the gap region. Figure 3.16 shows an
example of the existence of Vo in the gap region which causes a tail bit in HRS.
Experimentally, we found the evidence of new Vo generation in the gap region during the
RESET. Figure 3.17 shows the transient current waveform measured during the RESET.
It is seen that a significant current fluctuation is present in the transient waveform, which
is caused by a competition between the simultaneous Vo generation and recombination
processes. Although the CF is partially ruptured, the high electric field present in the gap
region may also induce Vo generation. This is especially prominent at the beginning
stage of the current drop when the gap size is small and the field and temperature are both
high. The generated Vo in the gap tends to reconnect the ruptured filament with the
electrode, giving rise to a current jump. If the Vo generation occurs in the middle of a
programming pulse, it has the chance to be recombined again with the mobile oxygen
ions. But if the Vo generation occurs just before the end of a programming pulse, it has
no chance to be recombined again since the pulse is withdrawn afterwards (see the
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experimentally observed last current jump in Figure 3.17). Therefore Vo are left in the
gap region and act as a bridge for the electron tunnel from the electrode to the residual of
the CF. To reduce the tail bits in HRS, the write-verify technique (write the cell first and
then read, if the cell resistance does not meet the resistance criterion, write it again) is
usually used [109].
Figure 3.16 An example of the existence of Vo (highlighted by red circle) in the gap
region which causes a tail bit in HRS.
91
Figure 3.17 The transient current waveform measured during the RESET with the last
current jump indicating a Vo left-over in the gap region.
3.1.6 Simulation of Reliability
Our KMC simulator is also capable of simulating the reliability. Figure 3.18 shows the
simulated endurance cycling at 125 °C. The reason that we chose an elevated temperature
is to accelerate the endurance degradation thus shorten the simulation time. During the
SET/RESET cycling, the HRS resistance decreases with cycling, which reflects the
experimental trend in Figure 2.6. Figure 3.19 shows the Vo configuration for the final
failure state (stuck at LRS). It shows there are insufficient O2- for recombining Vo at the
interface. During each SET cycle, O2- rushes towards the top electrode (TiN in our case),
92
and O2- that leak to the top electrode such as TiN may bond with the TiN to form TiON
layer thus cannot migrate back [110].
Figure 3.18 Simulated endurance cycling at 125 °C.
Figure 3.19 The Vo configuration for the final failure state (stuck at LRS).
93
Our simulator can also project the retention behavior versus time. Figure 3.20 shows
the statistically simulated LRS retention of 100 RRAM cells @150 °C. The resistance
gradually increases due to the gradual dissolution of CF. Figure 3.21 shows the LRS
failure time distribution at three baking temperatures. The LRS resistance increases
gradually during a high temperature baking test. The slope of extracted mean failure time
vs. 1/kT agrees well with O2- migration barrier parameter (~1.3 eV) used in the
simulation, which suggests that the LRS retention failure is caused by the O2- migration
from the interfacial oxygen reservoir. When the LRS fails, the tip of CF is ruptured by
O2- migration back from the interface.
Figure 3.20 Statistically simulated LRS retention of 100 RRAM cells @150 °C.
94
Figure 3.21 Simulated LRS failure time distribution at three baking temperatures.
3.2 Compact Modeling
Although the KMC simulator can reproduce many experimental observations, the
simulation is quite time-consuming since it is a numerical simulator. In order to enable
circuit/system level simulation, a compact model that can run fast while maintaining the
essential physics is useful. Therefore, we simplify the physical picture to be 1D filament
as shown in Figure 3.22.
95
Figure 3.22 Schematic of conductive filament with oxygen vacancies. The tunneling gap
distance g determines the device resistance.
The tunneling gap distance (g) determines the device resistance because quantum
tunneling through this gap region is the dominant conduction mechanism and the
resistance exponentially increases with the gap g. And g can be viewed as the average
tunneling gap distance, representing a state variable for the device. Therefore, the device
I-V relationship can be empirically expressed as:
I = I0 ∙ exp(−g g0⁄ ) ∙ sinh(V/V0) (3.8)
Here the “sinh” function is chosen to fit the linear dependence at low bias and
exponential dependence at high bias typically observed in experiments. The experimental
data from TiN/TiOx/HfOx/TiOx/HfOx/Pt RRAM device [111] was used for parameter
calibration. Fitting parameters I0 (~1 mA), g0 (~0.25 nm) and V0 (~0.25 V) are
determined by fitting with I-V curves at multiple resistance states (Figure 3.23). The
frontline of filament or the gap g evolves obeying the O2- migration velocity, which
96
originates from the O2- migration from one potential well to other in the following way
[103]:
dg
dt= −v0 ∙ exp(−
Em
kT) ∙ sinh(γ ∙
a0
L∙qV
kT) (3.9)
where Em is the O2- migration energy (~0.6 eV), a0 is the atom spacing (~0.25 nm), L is
the oxide thickness (~12 nm), q is the electron charge, k is the Boltzmann constant, and
v0 is a fitting parameter (~10 nm/ns). The local field acceleration parameter γ is
introduced due to the strong polarizability in high-k dielectrics as mentioned before, and
it is empirically fitted to be g dependent: γ = γ0 − β ∙ g3 where γ0 (~16) and β (~0.8) are
fitting parameters. In this way, γ increases as the frontline of filament gets closer to the
electrode and vice versa, thus it causes a positive feedback of the filament growth and a
negative feedback of the filament dissolution, leading to an abrupt SET process and a
gradual RESET process. T is the local temperature around filament due to Joule heating,
and the simplified heat equation follows:
dT
dt=
T−T0
τth+
V∙I
Cth (3.10)
where T0=298 K, τth is the thermal time constant, and Cth is the thermal capacitance.
Here we assume steady state, and then Rth= τth×Cth is equivalent thermal resistance
(~2000 K/W). The parameters in Eq. 3.9 and Eq. 3.10 are fitted by gradual RESET
transition curves by pulse train with different amplitudes (Figure 3.24). To capture the
stochastic RESET process, a Gaussian random number (δg) that accounts for the
randomness of oxygen ion migration is introduced:
dg = dg(ideal) + δg (3.11)
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dg(ideal) is the gap distance calculated by Eq. 3.9, and the relative resistance
variability is given by δR R⁄ = δg g0⁄ , to match the experimentally measured variability
in Figure 3.24, δg ~0.0224 nm, leading to δR/R ~9%.
Figure 3.23 The I-V fitting of multi-level resistance states by varying the gap tunneling
distance in the compact model.
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Figure 3.24 The gradual RESET transition curves by pulse train with different amplitudes.
With these analytical equations, we have the capability to implement the compact
model by MATLAB code or through the use of the SPICE engine in the form of
equivalent circuits [112] or Verilog-A codes for circuit/system level simulations 4.
3.3 Discussions and Summary
In this section, we discuss the comparison of our RRAM device model with other
models in the literature. Our model was developed for typical bipolar switching RRAM,
4 The RRAM compact models in the Verilog-A format can be downloaded from
https://nano.stanford.edu/model.php
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and was calibrated with the experiments from HfOx based RRAM. We believe with
appropriate parameter fitting and adjustment, our model can also apply to other bipolar
RRAM devices, such as AlOx, ZrOx, etc. In the literature, there are many other RRAM
device models. Here we briefly review these models:
For unipolar switching, Ielmini’s group at Politecnico di Milano did a series of early
works on NiO RRAM based the thermal dissolution model [113][114][115]. The thermal
dissolution model postulates that the RESET of unipolar switching is driven by the self-
accelerated dissolution of the CF due to the Joule heating. This suggests that the lateral
shrinking of the diameter of the CF is caused by the Vo diffusion at raised temperature.
Later, the Kang group at Peking University proposed that thermal decomposition of O2-
from oxygen-rich clusters around CF and their recombination with Vo causes the rupture
of the CF in the unipolar NiO RRAM [83][116]. Ielmini’s model was the first one that
highlights the role of Joule heating in the switching, and indeed all the ionic processes are
thermally enhanced by the Joule heating in the RESET. Kang’s model revealed the role
of the oxygen source in the unipolar switching, and it could be unified with the bipolar
switching under the same general physical picture.
For bipolar switching, especially the HfOx bipolar RRAM, there are three major
models in the literature, the first one is our model (developed in collaboration with
Kang’s group at PKU), the second one is Larcher’s model from Universita di Modena
(with collaboration with SEMATECH) [117][118], and the third one is Degraeve’s model
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from IMEC [119]. Below we discuss the common features and differences between these
three models.
For the electron conduction, our model assumes that in the HRS there is a bottleneck of
tunneling gap in a region near the top electrode with the residual CF conduction carried
by TAT; and in the LRS, the TAT and metallic conduction mechanisms co-exist.
Larcher’s model also assumes that in the HRS, TAT dominates the conduction with the
residual CF assumed to be metallic; and in the LRS, Larcher’s model assumes that the
conduction is purely metallic. Both models calculate the TAT current in the HRS, the
difference is that our model calculates the contribution of all the traps to the current,
while the Larcher’s model only considers the slowest trap/detrap process; in other words,
there is a dominant trap. For this dominant trap, the inelastic tunneling contribution
through phonon capture and emission is calculated. Degraeve’s model adopts a quantum
point contact (QPC) approach to describe conduction, in which the two electrodes are
separated by a constriction with variable width. The I-V relation in HRS and LRS are
fitted by changing the potential barrier’s parameters at the constriction. Although this
QPC approach may fit well with the I-V relation, it lacks a clear link with the physical
dimensions or shape of the CF.
For the ionic process and the interpretation of resistive switching, both our model and
Larcher’s model speculate that during the SET, Vo are generated and O2- migrate towards
the top electrode which is positively biased during SET, and during the RESET, the O2-
migrate back from the electrode/oxide interface to recombine with the Vo and rupture the
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filament. The difference between the two is that our model predicts that the CF is
ruptured near the top electrode, because the traps near the cathode (which is the top
electrode during RESET) tend to be electron-depleted as indicated by the TAT solver
(and discussed earlier in Fig. 3.4). Thus the depleted Vo becomes more positively
charged, leading to an increase of the capture cross-section with O2-, thus the
recombination becomes more favorable in this region. In contrast, Larcher’s model
assumes that the CF is ruptured near the bottom electrode, because according to their
simulation the trap density near the bottom electrode is lower based on the argument that
the phonon energy is mostly released in the region near the top electrode when the
electrons are injected from the bottom electrode. This lower trap density leads to a higher
resistance in this region and causes a higher temperature during the RESET. Therefore,
the CF tends to rupture at this high temperature region. Degraeve’s model is very
different than the other two models. In this model, there is no generation/annihilation of
Vo, and Vo just migrate inward and outward of the constriction region, which is in the
middle of the oxide layer. SET is a lateral growth of CF and RSET is a lateral shrink of
CF. Therefore, it is referred as an “hour glass” model.
So far, there is no solid evidence to support any of these above models. Dedicated in-
suit TEM study with EELS analysis may help identify the rupture location of the CF
during the RESET. Nevertheless, we have established a platform of a KMC numerical
simulator and a compact model of RRAM, which can reproduce many experimental
observations, gain more insights about the RRAM device physics and provide guidelines
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for future RRAM optimization. The KMC model can simulate the DC I-V sweep, pulse
switching, endurance cycling, and retention baking, etc. The tail bits in the resistance
distribution are attributed to the oxygen vacancy left over in the gap region due to a
competition between the oxygen vacancy generation and recombination. The compact
device model captures the essential device physics, but remains analytical for fast
simulations in the SPICE simulator for the circuit/system level design.
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Chapter 4
Oxide Based Synaptic Device for
Neuromorphic Computing
4.1 Background
In the memory hierarchy of today’s von Neumann digital system, the increasing gap
between the caches and the non-volatile storage devices in terms of write/read speed has
become the performance bottleneck of the whole system. Bio-inspired neuromorphic
computing breaks this von Neumann bottleneck because it takes the advantage of massive
parallelism that comes from the distributed computing and localized storage in networks
[120][121]. Neuromorphic computing is also inherently error-tolerant, thus it is especially
attractive for applications such as image or speech recognition which involve a huge
amount of correlated input data in a changing and indeterministic enviroment [122]. The
most advanced neuromorphic computing systems today are implemented by artificial
neural netwoks in software. For example, the IBM team performed a cortical simulation
at the complexity of the cat brain on Blue Gene supercomputer, which required huge
amount of computation resources:147,456 microprocessors and 144 TB of memories
consuming a power of 1.4 MW [123]. The parallelism of a multi-core computer pales in
comparison to the highly distributed computing in 1011 neurons and 1015 synapses in the
human brain. As an alternative approach, the hardware implementation of neuromorphic
computing may physically reproduce the parallelism on chip. Previously, neuromorphic
system in hardware with both neurons and synapses was implemented by CMOS circuits
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[124]. The scaling-up of these systems are mainly constrained by the device density and
energy consumption of the synapses since there are thousands of synapses connecting to
one neuron. Previously, each synapse was implemented with quite a few transistors, e.g.
the 8-T SRAM cells [125] that occupies a huge area (>100 F2, F is the minimum feature
size of the lithography technology) and consumes substantial static power. Recently, two-
terminal emerging memory devices that show electrically-triggered resistive switching
phenomenon have been proposed as artificial synapse [126]. These emerging memories
have the advantage of a small cell area (4F2, and 4F2/m if 3D stackable, m is the number
of 3D stack layer). In the literature, Ge2Sb2Te5 based PCRAM [127][128], Ag/a-Si [129],
Ag/Ag2S [130] based CBRAM, and TiOx [131], WOx [132] based oxide RRAM have
been reported showing synaptic behaviors. Among these candidates, oxide RRAM is
attractive for large-scale demonstration of a neuromorphic system due to a relatively
lower energy consumption (as compared to the phase change memory), the compatibility
with CMOS technology and the potential for 3D integration [64] [65]. Mb-scale to Gb-
scale prototype oxide RRAM chips have been demonstrated recently [38][39][40].
Therefore, a hybrid neuromorphic system with CMOS neurons and oxide RRAM
synapses integrated on top of CMOS neurons at the metal interconnect layers can be
envisioned. Figure 4.1 shows an analogy between the biological synapse and the artificial
oxide synaptic device: the biological synapse changes its conductance by
activating/deactivating ion channels between the membrane and the synaptic junction
when the action potential arrives, while the oxide synaptic device changes its resistance
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by generation and migration of the Vo and O2- when the programming voltage pulse is
applied. The vision is that the parallel neural network can be emulated by the cross-point
RRAM array for large-scale integration.
Figure 4.1 An analogy between the biological synapse and the artificial oxide synaptic
device. The vision is that the parallel neural network can be emulated by the cross-point
RRAM array for large-scale integration.
4.2 Synaptic Plasticity and Learning
The neurons and synapses are the two basic computational units in the brain. Neuron
computation is performed by integrating the inputs coming from other neurons and
generating spikes as a result. The synapses contribute to the computation by changing
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their connection strength as a result of neuronal activity, which is known as synaptic
plasticity. Synaptic plasticity is the mechanism that is believed to be underlying the
learning and memory formation of the brain [133]. The concept of synaptic plasticity
has been greatly influenced by Hebb’s postulate stating that the connection strength
between neurons are modified based on neural activities in pre-synaptic and post-synaptic
neurons [133]. The translation of the Hebbian learning rule into the hardware suggests
that the synaptic devices should serve as programmable weights between neurons [134].
In late 1990s, a form of Hebbian learning, spike-timing-dependent plasticity (STDP)
attracted tremendous interest in both experimental and computational fields of
neuroscience [134]. Figure 4.2 shows the asymmetric form of STDP which states that the
synaptic weight depends on the relative timing of arrival of the pre- and post-synaptic
spikes [135]: the synapse potentiates (increase in synaptic weight or conductance) if pre-
synaptic spike precedes post-synaptic spike repeatedly; and the synapse depresses
(decrease in synaptic weight or conductance) if post-synaptic spike precedes pre-synaptic
spike repeatedly. STDP can be generalized as a mechanism, which regulates the
connection strength of neurons depending on their co-activity and spike timing. Owing to
its simplicity, biological plausibility and computational power, STDP has been widely
used in computational neuroscience for pattern recognition, temporal sequence learning,
coincidence detection, navigation, and orientation selectivity.
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Figure 4.2 The asymmetric form of STDP states that the synaptic weight depends on the
relative timing of pre- and post-synaptic spikes [135]. ΔG = (Gafter-Gbefore)/Gbefore. Gbefore
is the conductance before the pre and post spike pair, and Gafter is the conductance after
the pre and post spike pair.
We are interested in how to realize the synaptic plasticity in the oxide RRAM based
synaptic device. The lowest requirement is that the RRAM device can act as
programmable weights for Hebbian learning. The programmable weights should have
multi-level resistance states. A higher requirement is to emulate the STDP learning rule,
thus the timing information should be incorporated into the plasticity by an appropriate
signaling scheme. In the following, we explore the multi-level capability of our
HfOx/AlOx RRAM device for serving the programmable weights, and we design a pulse-
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train with varying amplitudes for implementing the STDP learning. The fabrication of the
HfOx/AlOx RRAM can be referred to Section 2.2.
The practical application of synaptic devices would place the synaptic device under
spike communication. Therefore, we investigate the multi-level capability of the RRAM
under pulse programming. Figure 4.3 (a) shows the resistance evolution of the device for
the first 100 pulse cycles. The pulse widths were fixed to be 50 ns. Starting from the
LRS, the RESET process was first performed: 5 pulses with amplitudes consecutively
increased from -2.2 V to -2.6 V with -0.1 V step were applied. The RRAM resistance was
thus gradually increased from around 10 kΩ to several hundred kΩ. Then the SET
process was performed: 5 pulses with the amplitudes consecutively increased from 1.4 V
to 1.8 V with 0.1 V step were applied. The RRAM resistance was decreased from several
hundred kΩ to around 10 kΩ. After this 10-pulse sequence, the cell returned to the
original LRS. This up-down cycling could be repeated for many times. It is noted that
there are noticeable resistance variations in the cycling, and also the RESET process is in
general more gradual than the SET process (the SET has fewer intermediate states). This
observation is in agreement with the abrupt SET and gradual RESET in the DC I-V
characteristics (see Figure 2.3). Figure 4.3 (b) shows the similar up-down cycling after
the device underwent the 105- cycle endurance test (±3 V/50 ns for SET/RESET).
Although the highest resistance value tends to decrease a bit, the device still retains the
multi-level capability.
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Figure 4.3 The up-down cycling of the HfOx/AlOx synaptic device for (a) the first 100
cycles and for (b) the 100 cycles after 105 endurance testing cycles. The pulse widths
were fixed to be 50 ns. The pulse sequence is 5 pulses increased from -2.2 V to -2.6 V
with a step -0.1 V and then 5 pulses with increased from 1.4 V to 1.8 V with a step 0.1 V.
(a)
(b)
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In order to implement the STDP learning rule, we develop a signaling scheme that
utilizes the pulse amplitude to tune the resistance states. The generation of these specific
signals is done by the corresponding neuron circuit design in practical applications. Let
us first examine how the pulse amplitude in a single pulse can effectively tune the
resistance states. Figure 4.4 shows resistance modulation of 10 states achieved by varying
the amplitudes of positive pulses and negative pulses from an intermediate initial state
(200 kΩ ~ 300 kΩ, the shaded region in the plot). As we can see, for a linear increase of
positive pulse amplitude from 1.6 V to 2V, the resistance gradually decreases to around
30 kΩ. For a linear increase of the negative pulse amplitude from -2.4 V to -2.8 V, the
resistance gradually increases to around 3 MΩ. To exploit the capability of the pulse
amplitude modulation for STDP, the shape of the spike is designed as in Figure 4.5. The
spike consists of a series of single pulses in consecutive timeslots. A negative pulse
occupies the first timeslot; then positive pulses with decreasing amplitudes follow in
subsequent timeslots. The design principle is that the no single pulse in any timeslot can
affect the device’s resistance. Only when there is an overlap of the pre-spike and post-
spike, a programming pulse can be generated for which the amplitude is large enough to
modulate the resistance. The voltage dropped on the synapse is defined as the voltage of
the pre-spike minus the voltage of the post-spike. Thus, the negative pulse in the first
timeslot acts as an enabling function to determine which positive pulse could contribute
to the programming pulse. Closer spike timing means the negative pulse would overlap
positive pulse with larger amplitude, leading to a larger resistance change. If the pre-
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spike precedes the post-spike, a positive programming pulse (the red one in the figure) is
produced. Otherwise, a negative one (the blue one in the figure) is produced. An example
design of the spike is outlined here: The period for each pulse in one spike is designed to
be 1 µs. The duty cycle for each positive pulse can be very short, e.g. 50 ns. However, the
duty cycle for the first negative pulse should be relatively longer, e.g. 500 ns, since it acts
as an enabling function that must tolerate the timing variability caused by the RC delay
through the interconnect. Therefore the total time for one spike is 6 µs, corresponding to
a maximum operating frequency is 167 kHz. Using the signaling scheme explained
above, the STDP-like curve could be reproduced in the RRAM based synaptic devices as
Figure 4.6. The relative conductance changes were calculated with the data in Figure 4.4.
Figure 4.4 The HfOx/AlOx synaptic device resistance modulation by the pulse amplitude
starting from an initial state with an intermediate resistance value (200 kΩ ~ 300 kΩ, the
shaded region in the plot). Each error bar consists of 50 independent tests.
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Figure 4.5 Spike-timing-dependent plasticity (STDP) realization schemes developed with
time-division multiplexing and pulse amplitude modulation. The pulse amplitudes for the
pre-spike are -1.4 V, 1 V, 0.9 V, 0.8 V, 0.7 V, 0.6 V, consecutively, and for the post-
spike are -1V, 1.4 V, 1.3 V, 1.2 V, 1.1 V, 1V, consecutively.
Figure 4.6 The STDP-like curve calculated with the data in Figure 4.4 employing the
signaling schemes in Figure 4.5
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4.3 Analog Synapse and Binary Synapse for WTA Network
In the previous section, it was shown that by varying the pulse amplitude, up to 10
resistance states could be obtained in HfOx/AlOx synaptic devices; however, the pulse-to-
pulse variation was significant. Here we investigate a TiN/TiOx/HfOx/TiOx/HfOx/Pt stack
as synaptic device because it has better switching uniformity. This multi-layer stacked
device is also forming-free without requiring an initial large voltage to trigger the
subsequent switching events. The device fabrication and memory performance
characterization can be referred to [111]. It was shown that with this multiple oxide layer,
the cycle-to-cycle and device-to-device variation is significantly reduced [111]. Figure
4.7 shows the DC I-V characteristic of the TiOx/HfOx/TiOx/HfOx synaptic device. Multi-
level resistance states in this measurement were achieved by varying the RESET stop
voltages. It is seen that the SET process is abrupt while the RESET process is gradual.
This is because the SET process is a positive feedback between the Vo generation rate
and the temperature and local field strength, while the RESET process is a negative
feedback. Thus we utilized the gradual RESET process as analog synapse since it can
obtain multiple immediate states as the programmable weights in the neural network.
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Figure 4.7 The DC I-V characteristic of the TiOx/HfOx/TiOx/HfOx synaptic device.
4.3.1 Analog Synapse for Depression Learning
Since we utilize the gradual RESET process, we started the training from two initial
resistance states (~500 Ω and ~20 kΩ), and applied 400 identical RESET pulses (-1.1
V/10 ns and -1.3 V/10 ns), and the results collected from 5 different devices are shown in
Figure 4.8. During the depression learning process, the resistance gradually increases;
about 100 intermediate states were achieved although the variation is still present. To test
the device endurance, we repeated such training process for 1000 cycles (1 cycle includes
400 identical RESET pulses). After one RESET training cycle, we used DC sweep to
SET the device to ~500 Ω or ~20 kΩ by controlling the compliance current. Figure 4.9
shows the RESET training process at several milestone cycles in the endurance test. No
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significant degradation was found after 1000 cycles. The energy consumption per spike
depends on the initial resistance states. Figure 4.10 shows the training process starting
from 3 different initial states (~500 Ω, ~3 kΩ and ~20 kΩ). The higher resistance the
initial state is, the less the energy per spike the device consumes. For an initial resistance
state of ~20 kΩ, the energy per spike drops to ~0.85 pJ. It should be mentioned that here
the maximum energy consumption at the initial stage of the training is estimated. As the
training progresses, the resistance gets higher, and the energy consumption also
decreases. As far as we know, this is the first sub-pJ synaptic device reported in the
literature.
Figure 4.8 The depression learning process by 400 consecutive identical RESET pulses
for 5 different devices. The initial resistance states are chosen to be ~500 Ω and ~20 kΩ,
respectively.
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Figure 4.9 The depression learning process at several milestones during the 1000 cycle
endurance cycling test. 1 cycle includes 400 consecutive identical RESET pulses.
Figure 4. 10 Dependence of the energy per spike on the initial resistance states for the
training process. If starting at ~ 20 kΩ, the maximum energy per spike drops below 1 pJ.
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To capture the gradual RESET process, we employed our compact model that has been
calibrated with this TiOx/HfOx/TiOx/HfOx RRAM (see Section 3.2). Figure 4.11 show the
simulated depression learning process starting from ~500 Ω by varying the pulse
amplitudes, mimicing the the experimental data in Figure 3.24. In Section 4.3.3, we apply
this compact model of depression learning for the system-level simulation.
Figure 4.11 Simulated depression learning process starting from ~500 Ω by varying the
pulse amplitudes, mimicing the the experimental data in Figure 3.24.
4.3.2 Binary Synapse for Stochastic Learning
In the previous section, we explored an analog synapse utilizing depression learning.
The reason why we only utilized the depression is that the gradual RESET transition
offers hundreds of intermediate states while the abrupt SET transition only offers binary
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states. It is believed that the analog synapse generally outperforms the binary synapse for
neuromorphic computing because a limited number of synaptic states dramatically reduce
the storage capacity of a neural network [136]. If the synaptic strength cannot be changed
by an arbitrarily small amount as in the case of the binary synapse, the newly learned
patterns quickly overwrite the previously learned ones, thus the storage capacity is
limited. This problem can be overcome by a stochastic learning rule that changes only a
small fraction of synapses randomly chosen at each training cycle [136]. How can this
random choice be realized in an oxide binary synaptic device without increasing the
complexity of the CMOS neuron circuit design? Here we demonstrate that the SET
transition of the oxide RRAM becomes probabilistic under a weak programming
condition (applying a smaller voltage than the nominal switching voltage for a successful
programming event). We propose utilizing this inherent switching variability to realize
the stochastic learning rule in the binary synapse.
Figure 4.12 shows the measured SET/RESET continuous cycling with different SET
pulse amplitudes (+1.9 V/10 ns, +1.6 V/10 ns, +1.3 V/10 ns, respectively). It is seen that
with the decrease of the SET pulse amplitude, the SET success probability decreases as
well, thus the SET process becomes stochastic under weak programming conditions. The
resistive switching is inherently stochastic as suggested by our Kinetic Monte Carlo
simulation described before. The remarkable switching parameter variability is a well-
known technical challenge for the oxide RRAM array design and substantial research
efforts were spent to reduce the variability. Here we make use of this nominal
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disadvantage (from a digital memory perspective) to realize the stochastic learning rule
for the binary synapse.
(a)
(b)
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Figure 4.12 Measured SET/RESET continuous cycling with different SET pulse
amplitudes (a) +1.9 V/10 ns, (b) +1.6 V/10 ns, (c) +1.3 V/10 ns, respectively.
The SET process becomes stochastic under weak programming conditions.
To obtain the statistics for both cycle-to-cycle variation and device-to-device variation,
we measured the pulse amplitudes required for triggering the SET transition: In each
cycle, a strong RESET pulse (-1.9 V/10 ns) was applied to achieve a complete off-state
(~500 kΩ), then a weak SET pulse with amplitudes from +0.6 V to +3 V (with linearly
spaced steps with increasing amplitude) with a 10 ns width was applied to determine the
switching probability. Such cycle was repeated for 100 cycles for each device. Then 50
different devices on the wafer were measured. Figure 4.13 shows the measured statistical
distribution: (a) for a particular device, the pulse amplitude for a successful SET
operation roughly follows a Gaussian distribution with a standard deviation about 0.3 V;
(c)
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(b) across various devices, the medium pulse amplitude for a successful SET operation is
centered around 1.95 V with a standard deviation about 0.15 V (a straight line in this plot
indicates a Gaussian distribution). If we design the pulse amplitude applied to the device
to be 1.6 V, then on average, around 12% SET trials will be successful. Certainly, due to
device-to-device variation, some device may have success probability higher than 12%,
while others may have success probability lower than 12%. Nevertheless, the SET
transition becomes probabilistic under this weak programming condition. In the learning
simulation that follows, we use a weak SET condition (e.g. +1.6 V/10 ns) with a strong
RESET condition (e.g. -1.9 V/10 ns) for a stochastic learning rule. Here a strong RESET
is needed to switch the device to a complete off-state to avoid any unintentional
switching under a weak SET programming condition in the next cycle.
(a)
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Figure 4.13 Measured statistical distribution of pulse amplitude required for triggering
the SET switching from the off-state. In (a), the probability of SET switching is measured
from one representative device for 100 cycles. In (b), 50 different devices on the wafer
were measured with one type of symbol in the figure representing the data from one
device.
According to the measurement results in Figure 4.13, the stochastic switching behavior
is modeled as follows: the cycle-to-cycle variation of the binary synapse is modeled as a
Gaussian distribution of the threshold SET pulse amplitude (with a standard deviation 0.3
V); and the median value of the Gaussian distribution shifts from device to device,
reflecting the device-to-device variation, which is modeled as a Gaussian distribution
(b)
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centred around 1.95 V with a standard deviation 0.15 V. When this model was
implemented in the following simulation, each synapse in the network is randomly
assigned with a Gaussian distribution of SET threshold with the parameters extracted
aforementioned. In Section 4.3.3, we apply this model of stochastic learning for the
system-level simulation.
4.3.3 Winner-Take-All Network Simulation
For oxide RRAM devices to be used for emulating synapses, there are several general
open questions needed to be addressed at the system-level, e.g., why does a useful
learning algorithm require the multi-level intermediate states, how many resistance states
are needed, how does the inherently stochastic device variation affect system
performance, and can binary synapse be useful if a stochastic learning rule is used? In
order to answer these questions, we perform a simulation of a two-layer winner-take-all
(WTA) neural network [137] as a toy model, comparing binary synapse and analog
synapse implementations.
Figure 4.14 shows the WTA architecture implemented by integrate-and-fire neurons
and oxide synaptic devices: Every neuron in the output layer connects with all the
neurons in the input layer through excitatory synapses based oxide RRAM devices. Every
neuron in the output layer also connects to one another through inhibitory synapses based
on fixed resistors. The unsupervised competitive learning algorithm allows such two-
layer network to perform the orientation classification function [137]. Figure 4.15 shows
a spiking scheme for implementing the unsupervised competitive learning algorithm
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designed for (a) binary synapse and for (b) analog synapse: The input layer neurons fire
according to the light intensity of the input pattern; if the light intensity exceeds the
neuron firing threshold, the neurons send a relatively long but small positive pulse to all
the output layer neurons through the excitatory synapses. The output layer neurons sum
and integrate the input currents on the membrane capacitor independently, and the one
with the largest input current fires first (becomes the “winner”), then it discharges the
membrane capacitor of all the other output layer neurons and prevent them from firing
(“takes all”) through the inhibitory synapses. Meanwhile this winner neuron sends a short
two-phase pulse with a small negative pulse followed by a large positive pulse back to all
the input layer neurons for binary synapse, or it sends a positive pulse with amplitude of
the actual RESET programming pulse for analog synapse. Thus the excitatory synapse
strength gets modified according to the input pattern. For stochastic learning using binary
synapse under a weak programming condition (e.g. +1.6 V/10 ns), the update of the
synapse conductance map is an incremental process. For depression learning using analog
synapse (e.g. -1.1 V/10 ns), the update of the synapse conductance map is also an
incremental process. After a certain number of training images, a self-organized
conductance map is expected to emerge.
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Figure 4.14 The WTA architecture implemented by integrate-and-fire neurons and oxide
synaptic devices.
(a)
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Figure 4.15 A spiking scheme for implementing the unsupervised competitive learning
algorithm designed for (a) binary synapse and for (b) analog synapse.
In the following simulation, 32×32 neurons in the input layer are used and 2×2 neurons
in the output layer are used. Thus there are 4096 oxide synaptic devices between the two
layers. The neuron firing threshold is set to be 1 V, and the decay time constant of the
membrane voltage is set to be 1 µs. For binary synapse, the pre-synaptic forward spike
from the input layer neuron is designed to be a positive pulse (e.g. +0.8 V/500 ns) that is
half the amplitude of the actual SET programming pulse, and the post-synaptic backward
spike from the output layer neuron is designed to be a negative pulse (e.g. -0.8 V/10 ns)
that is half the amplitude of the actual SET programming pulse followed by a positive
pulse (e.g. +1.9 V/10 ns). For analog synapse, the pre-synaptic forward spike from the
(b)
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input layer neuron is designed to be positive pulse (e.g. +0.55 V/500 ns) that is half
amplitude of the actual RESET programming pulse, and the post-synaptic backward
spike is designed to be a positive pulse with amplitude of the actual RESET programming
pulse (e.g. +1.1 V/10 ns).
Initially, the resistances of all the oxide synaptic devices were randomized with a
distribution centered at the on-state (~500 Ω). During the training, 200 gray-scale testing
images with 32×32 pixels were presented into the input layer neurons. The input patterns
have the shape of a 2D Gaussian bar with random orientation. The decay length of the 2D
Gaussian bar in longitude direction is 16 pixels and the decay length in latitude direction
is 4 pixels. The input layer neuron fires if the relative intensity is larger than 0.5. These
200 test images have a non-uniform distribution in 4 orientations (centered at 0o, 45o, 90o,
and 135o with a standard deviation of 7.5o). The target of the network is to converge at
these 4 dominate orientations. When the training was completed after 200 training images
by definition, standard images of 2D Gaussian bar in 24 different orientations (0o to 180
with a step of 7.5o) were used for testing the orientation selectivity of the network.
Figure 4.16 shows the evolution of the normalized conductance map between the input
layer neurons and the output layer neurons for the binary synapse with stochastic learning
(a)-(c) and the analog synapse with depression learning (d)-(f). Initially, the resistances of
all the oxide synaptic devices were randomized with a distribution centered at an on-state
(~500 Ω), see (a) for binary synapse and (d) for analog synapse. After the training, the
resistances split into groups of the on-state and the off-state. With appropriate
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programming condition, the 4 distinct orientations emerge, see (b) for binary synapse
using +1.6 V/10 ns SET pulse and (e) for analog synapse using -1.1 V/10 ns RESET
pulse. It is noted that for the analog synapse, there are many noisy pixels caused by the
intermediate states. If the programming condition not optimized, only 3 distinct
orientations emerge, see (c) for the binary synapse using +2 V/10 ns SET pulse and (f)
for the analog synapse using -1.4 V/10 ns RESET pulse.
Figure 4.16 Simulated normalized conductance map between the input layer neurons and
the output layer neurons utilizing binary synapse with stochastic learning (a)-(c) and
analog synapse with depression learning (d)-(f). The normalization is done with respect
to a reference that is the highest conductance in the synapse array before the training.
129
To compare the system performance between the binary synapse and the analog
synapse, three metrics are used: 1) the orientation selectivity defined as the contrast of the
output layer neuron’s response intensity to the 1st preferred orientation over the 2nd
preferred orientation; 2) the orientation storage capacity defined as the number of distinct
orientations stored in the output layer (ideally, 4 distinct orientations will be detected); 3)
the energy consumed on the synaptic devices during the whole training, including the
read energy for summing the current through the synapses and the write energy for
programming the synapses. Figure 4.17 shows the average values of these metrics as a
function of programming conditions for the system with the binary synapse (a)-(b) and
the system with the analog synapse (c)-(d) through 100 independent simulation runs. The
trends can be explained as follows: For the binary synapse, increasing the SET pulse
amplitude means increasing the SET success probability. As a result, the selectivity
increases because more pixels are switched to “white” and the contrast is improved. The
orientation storage capacity can achieve the maximum value 4 at 1.6 V, thus +1.6 V/10 ns
is chosen as the optimized programming condition for the binary synapse, which
corresponds to a SET success probability ~ 12% on average. The loss of the orientation
storage capacity below 1.6 V SET pulse amplitude is due to insufficient SET success
probability, which limits the ability of the network to learn sufficient patterns for a fixed
(limited) set of training images (200 images in this case). On the other hand, the rapid
drop of the orientation storage capacity beyond 1.6 V SET pulse amplitude is due to
excessive SET success probability, which hastens the network’s forgetting process
130
(overwriting the learned patterns too frequently), thus only the final patterns are
remembered (see Fig. 4.16 (c) as an example). The total energy consumption (including
the read and write energy) increases with the increase of the SET pulse amplitude. The
energy consumption roughly follows the relationship ~ E = (V2/R)×t. For the analog
synapse, increasing the RESET amplitude means that the RESET transition becomes less
gradual and fewer intermediate states are available (see Figure 3.24). As a result, both the
selectivity and the orientation storage capacity decreases with increasing RESET pulse
amplitude (see Fig. 4.16 (f) as an example). Here -1.1 V/10 ns is chosen as the optimized
programming condition for the analog synapse. Under depression learning mode, the
learning becomes saturated as the devices quickly RESET to the completely off-state if
the number of possible intermediate states is insufficient. The write energy consumption
decreases with the increase of RESET pulse amplitude since the learning saturates faster.
The read energy has a turning point due to the competing trends of increasing voltage and
increasing resistance in the relationship ~E = V2/R×t. At the optimized programming
condition for the binary synapse and the analog synapse respectively, the same full
network storage capacity of 100% is achievable, the selectivity of the binary synapse is
14.2% and that of the analog synapse is 9.9%, and the total energy consumption of the
binary synapse is 156 µJ and the that of the analog synapse is 60 µJ. The feasibility of the
adaptive learning with either binary synapse or analog synapse is demonstrated through
this system-level simulation.
131
(a)
(b)
132
Figure 4.17 Simulated system performance metrics as a function of programming
conditions. Network orientation selectivity and orientation storage capacity for binary
synapse in (a) and for analog synapse in (c); Energy consumption of the synaptic devices
(c)
(d)
133
during the whole training (200 training images) for binary synapse in (b) and for analog
synapse in (d). The average values through 100 independent simulation runs are shown.
To study the impact of synaptic device variation on the robustness of the neuromorphic
system, we increase the variability (δR/R) for the analog synapse and perform 100
independent simulations for each variability level (for the binary synapse simulation, the
variation effect is already considered in the model). Figure 4.18 shows that up to the
experimental variability level (~9%), the system is robust, and there is only slight
degradation of the selectivity even at the variability level ~ 40%. This simulation
demonstrates the robustness of the neuromorphic computing against the device variation
at the system level thanks to the parallelism of the neural network.
Figure 4.18 Simulated orientation selectivity as a function of the analog synapse
variability δR/R. At each error bar, 100 independent simulations are performed.
134
4.4 Performance Metrics for Synaptic Device
The interest in building large-scale neuromorphic systems using synaptic devices has
motivated the device community to make significant progress in developing synaptic
devices mimicking the key characteristics of biological synapses. However, a clear
understanding of the performance metrics is still lacking, mainly due to the diversity of
the targeted application space. In this section, we discuss some general characteristics for
synaptic devices which are desirable for most of the applications. In order to evaluate
different synaptic device characteristics, a rule of thumb can be scalability to biological
levels. An ideal synaptic device should have characteristics such as size, energy
consumption, operation frequency, which are scalable to biological levels. The analysis
below is presented with that perspective in mind. Table 4.1 summarizes desirable
performance metrics for synaptic devices.
1) Synaptic Device Dimensions: The large-scale integration of neural network requires a
compact synaptic device with a small device footprint. Two terminal structures that
can enable 3D integration and potential scalability to nanometer regime are one of the
key guiding principles of synaptic devices research. The density of synapses in
human cortex is >~109/mm3 and the physical size of the synaptic cleft is <~20 nm
[133]. Thus synaptic devices with scalability down to sub-10 nm regime is preferred.
10 nm×10 nm HfOx RRAM devices has been demonstrated [26], showing a good
promise for scalability.
135
2) Energy Consumption: Among all performance metrics, energy consumption is the
most challenging and probably the most difficult to achieve considering the need for
energy efficient brain-inspired computational systems in the future. The number of
biological synapses is enormous (~1015) in the human brain [133]. As an order-of-
magnitude estimation, the synapses operate at about a frequency of 1~10 Hz [133],
and the human brain consumes a power of the order of 10 W [133]. Thus, on average
the energy consumption per synaptic event is around 1~10 fJ. Some of the HfOx
RRAM have already shown sub-pJ level energy consumption [26], while it holds the
potential to further decrease in synaptic energy consumption to the fJ level by further
lowering the programming current from tens of µA to sub-µA level.
3) Operating Speed/Programming Time: The brain operates at an average frequency of
1~10 Hz. Most of the synaptic device candidates can already operate faster than that.
The fast (~ns) programming speed of the oxide RRAM provides a lot of flexibility to
design the signaling scheme for implementing learning rules. A good strategy can be
developing plasticity schemes for synaptic devices with ns or µs programming times
to keep the synaptic energy consumption as low as possible (See the discussion about
energy-efficient programming in Section 2.4.2).
4) Multi-level States: Synaptic plasticity characteristics measured on biological synapses
show an analog-like behavior with many synaptic weight states between the highest
and the lowest conductance states [133]. In general, more multi-level states are
known to bring advantages in terms of network capacity and robustness, the precise
136
requirement for the number of conductance states remains strongly application-
specific. Our work (Section 4.3) and also other group’s work [138] on binary synapse
provide more design space with stochastic learning algorithm.
5) Dynamic Range: A biological synapse, which exhibits the STDP behavior, needs to
perform a cumulative weight change with a maximum of 100% and a minimum -50%
[133], which translates into a minimum dynamic range of 4 for the synaptic device
conductance. Hence, a dynamic range of 10 is more than sufficient to implement
biological plasticity. Most of the synaptic device candidates exhibit a wider (>100)
programmable resistance range, which provides flexibility in choosing the operation
regime. Since we have more freedom to choose the operating resistance range, for
oxide RRAM based synaptic device, the high resistance regime is found to be more
energy-efficient because the operating current is low in that regime. Besides, the high
resistance is useful for minimizing the read energy, and also helps to reduce the
neuron capacitor area. When the integrated-and-fire neuron sums the current from
hundreds of synapses, the total current charges the membrane capacitor of the neuron.
A high summated current will require a larger capacitor and, neuron circuitry will
occupy significantly large chip area.
6) Retention and Endurance: For the long-term memory, it needs to have a retention
property in the order of 10 years, to enable formation of life-long memories and to
maintain them for long periods of time. It can be envisioned that an endurance of
3x109 synaptic operations will guarantee 10 years of lifetime with 10 Hz operation
137
frequency. Most of the works published on synaptic devices has not given enough
attention to retention and endurance characteristics yet.
7) Uniformity and Variation: Poor uniformity and variation in device characteristics is a
major barrier to introducing novel nanoscale devices to CMOS logic or memory
applications. In contrast, brain-inspired or neuromorphic architectures promise
immunity against device variations. The level of variation that can be tolerated at the
system level strongly depends on the network architecture and the accuracy required
by the target application. Besides our simulation in Section 4.3.3, some works have
shown the robustness against device variations in different neural networks through
simulations [139][140]. Since the level of variation that can be tolerated is a
parameter that strongly depends on the characteristics of the neural network, we will
not specify a maximum level in this thesis.
Table 4.1 Summary of the desirable performance metrics for synaptic devices.
Performance metrics Targets
Device dimension < 10 nm
Energy consumption <10 fJ/spike
Operation frequency >>10 Hz
Multi-level states number 10~100
Dynamic range >4
Retention/Endurance >10 years/ 109 synaptic activities
138
4.5 Summary
We explore the potential of the RRAM technology as synaptic device for the hardware
implementation of neuromorphic computing. Programming schemes were proposed for
realizing spike-timing dependent plasticity (STDP) in the RRAM devices. The gradual
resistance modulation capability was explored to serve as analog synapse, and the
stochastic switching was explored to serve as binary synapse. A simulation of winner-
take-all network suggests that the orientation classification can be effectively realized
using RRAM synapses. And the system performance is found to be robust against the
RRAM device variability due to the adaptive algorithm and parallelism of the neural
network. Finally, the performance metrics of desired synaptic device were discussed.
139
Chapter 5
Conclusion and Outlook
5.1 Summary of contribution
This thesis addresses the key challenges of the RRAM technology development,
including the physics of resistive switching in oxides, the origin of the relatively poor
uniformity and large variability of the switching parameters. Additionally it also explores
the potential of using RRAM as synaptic device for neuromorphic computing. The
contributions of this thesis include:
1. A general physical picture of resistive switching phenomenon in binary oxides is
established, and is becoming a prevailing theory in the community. The resistive
switching is attributed to the conductive filament (made up of oxygen vacancies)
formation and rupture in the oxides. The physical picture was validated using the
HfOx-based RRAM devices through experiments and modeling.
2. The trap-assisted-tunneling was identified to be the dominant conduction
mechanism in oxide RRAM by various characterization techniques such as I-V
measurement at various temperature, low frequency noise measurement, AC
conductance measurement, etc.
3. An exponential voltage-time relationship was found between the switching time
and the applied voltage, revealing the physics of the oxygen ion migration
140
dynamics. Inspired by the voltage-time relationship, an energy-efficient
programming scheme was also proposed for multi-level operation.
4. For the first time, a Kinetic Monte Carlo (KMC) numerical simulator was
developed for RRAM. The idea of “discretizing” the oxide matrix and tracking
each individual oxygen vacancy and ion evolution path is a breakthrough in the
RRAM modeling as this method inherently includes stochastic nature of resistive
switching in the model and enables the model to describe the experimentally
observed variability of device characteristics. The KMC simulation can reproduce
many experimental observations in the DC I-V sweep, pulse switching, gradual
RESET, temporal fluctuation of RESET current, endurance cycling, and retention
baking, etc.
5. For the first time, the origin of the tail bits in the resistance distribution was
identified: tail bits in HRS are attributed to the oxygen vacancy left over in the
gap region due to a competition between the oxygen vacancy generation and
recombination.
6. A compact RRAM device model was developed for circuit/system-level
simulations, which has been implemented in MATLAB, SPICE macro model, and
Verilog-A and executable with the SPICE simulation engine.
7. The potential of the RRAM technology as synaptic device for the hardware
implementation of neuromorphic computing was explored. Programming schemes
141
were proposed for realizing spike-timing dependent plasticity in the RRAM
devices.
8. Pioneering works on the gradual resistance modulation capability as analog
synapse and the stochastic switching as binary synapse opens new opportunities
in the synaptic design.
9. A simulation of winner-take-all network was performed on the orientation
classification function using RRAM synapses. And the system performance is
found to be robust against the RRAM device variability due to the adaptive
algorithm and parallelism of the neural network.
5.2 Future work
This thesis presents a comprehensive study which provides a solid foundation for more
exciting future work in several directions.
With respect to the RRAM TAT modeling, the coupling of the Poisson equation with
the TAT current continuity equation is missing due to the convergence issue in numerical
solution. Ideally the Poisson equation should be added into the simulator in a self-
consistent manner.
With respect to the RRAM KMC modeling, currently the electrodes are treated as two
lines at the boundaries. In the future work, it is suggested to include the electrode into the
simulated region. By doing so, we can further study the electrode/oxide interface effect.
142
Effects due to the surface roughness can be handled as well. More aggressively, the KMC
simulator could be extended from a 2D simulator to 3D simulator to have better
estimation of the Vo density in the CF as well as a more physics-based three-dimensional
description of the current conduction paths.
With respect to the RRAM compact modeling, implementing the compact model in the
Verilog-A form in the SPICE simulator is useful to enable many circuit design. This
work is already underway and close to completion.
With respect to the synaptic device design, we have measured on a single device and
extracted the parameters for network-level simulation. The next step is to validate the
learning algorithms directly on a cross-point RRAM array.
143
Bibliography
[1] A. Szalay and J. Gray, “2020 computing: science in an exponential world,” Nature,
vol. 440, no. 7083, pp. 413–414, 2006.
[2] J. Akerman, “Toward a universal memory,” Science, vol. 743, no. 9, pp. 508–510,
2005.
[3] B. J. Zhu, “Magnetoresistive random access memory: the path to competitiveness
and scalability,” Proceedings of the IEEE, vol. 96, no. 11, pp. 1786–1798, 2008.
[4] H.-S. P. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M.
Asheghi, and K. E. Goodson, “Phase change memory,” Proceedings of the IEEE,
vol. 98, no. 12, pp. 2201–2227, 2010.
[5] H.-S. P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, B. Lee, F. T.
Chen, and M.-J. Tsai, “Metal–oxide RRAM,” Proceedings of the IEEE, vol. 100,
no. 6, pp. 1951–1970, 2012.
[6] C. W. Smullen, V. Mohan, A. Nigam, S. Gurumurthi, and M. R. Stan, “Relaxing
non-volatility for fast and energy-efficient STT-RAM caches,” IEEE International
Symposium on High Performance Computer Architecture, pp. 50–61, 2011.
144
[7] G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S.
Shenoy, “Overview of candidate device technologies for storage-class memory,”
IBM Journal of Research and Development, vol. 52, no. 4/5, pp. 449–464, 2008.
[8] Y. Xie, “Modeling, architecture, and applications for emerging memory
technologies,” IEEE Design & Test of Computers, vol. 28, no. 1, pp. 44–51, 2011.
[9] T. W. Hickmott, “Low-frequency negative resistance in thin anodic oxide films,”
Journal of Applied Physics, vol. 33, no. 9, pp. 2669–2682, 1962.
[10] W. W. Zhuang, W. Pan, B. D. Ulrich, J. J. Lee, L. Stecker, A. Burmaster, D. R.
Evans, S. T. Hsu, A. Shimaoka, K. Inoue, T. Naka, N. A. K. Sakiyama, Y. Wang,
S. Q. Liu, N. J. Wu, and A. Ignatiev, “Novell colossal magnetoresistive thin film
nonvolatile resistance random access memory (RRAM),” IEEE International
Electron Devices Meeting, pp. 193–196, 2002.
[11] A. Asamitsu, Y. Tomioka, H. Kuwahara, and Y. Tokura, “Current switching of
resistive states in magnetoresistive manganites,” Nature, vol. 388, no. 3, pp. 1995–
1997, 1997.
[12] A. Beck, J. G. Bednorz, C. Gerber, C. Rossel, and D. Widmer, “Reproducible
switching effect in thin oxide films for memory applications,” Applied Physics
Letters, vol. 77, no. 1, pp. 139–141, 2000.
145
[13] Y. Watanabe, J. G. Bednorz, A. Bietsch, C. Gerber, D. Widmer, A. Beck, and S. J.
Wind, “Current-driven insulator–conductor transition and nonvolatile memory in
chromium-doped SrTiO3 single crystals,” Applied Physics Letters, vol. 78, no. 23,
pp. 3738–3740, 2001.
[14] I. G. Baek, M. S. Lee, S. Sco, M. J. Lee, D. H. Seo, D.-S. Suh, J. C. Park, S. O.
Park, H. S. Kim, I. K. Yoo, U.-I. Chung, and J. T. Moon, “Highly scalable non-
volatile resistive memory using simple binary oxide driven by asymmetric unipolar
voltage pulses,” IEEE International Electron Devices Meeting, pp. 587–590, 2004.
[15] S. Seo, M. J. Lee, D. H. Seo, E. J. Jeoung, D.-S. Suh, Y. S. Joung, I. K. Yoo, I. R.
Hwang, S. H. Kim, I. S. Byun, J.-S. Kim, J. S. Choi, and B. H. Park,
“Reproducible resistance switching in polycrystalline NiO films,” Applied Physics
Letters, vol. 85, no. 23, pp. 5655–5657, 2004.
[16] B. J. Choi, D. S. Jeong, S. K. Kim, C. Rohde, S. Choi, J. H. Oh, H. J. Kim, C. S.
Hwang, K. Szot, R. Waser, B. Reichenberg, and S. Tiedke, “Resistive switching
mechanism of TiO2 thin films grown by atomic-layer deposition,” Journal of
Applied Physics, vol. 98, no. 3, p. 033715, 2005.
[17] A. Chen, S. Haddad, Y. J. Wu, T. Fang, Z. Lan, S. Avanzino, M. Buynoski, M.
Rathor, W. D. Cai, N. Tripsas, C. Bill, M. Vanbuskirk, and M. Taguchi, “Non-
146
volatile resistive switching for advanced memory applications,” IEEE
International Electron Devices Meeting, pp. 746 - 749, 2005.
[18] C. Lin, C. Wu, C. Wu, T. Tseng, and C. Hu, “Modified resistive switching
behavior of ZrO2 memory films based on the interface layer formed by using Ti
top electrode,” Journal of Applied Physics vol. 102, no. 9, p. 094101, 2007.
[19] N. Xu, L. Liu, X. Sun, X. Liu, D. Han, Y. Wang, R. Han, J. Kang, and B. Yu,
“Characteristics and mechanism of conduction/set process in TiN∕ZnO∕Pt
resistance switching random-access memories,” Applied Physics Letters, vol. 92,
no. 23, p. 232112, 2008.
[20] H. Y. Lee, P. S. Chen, T. Y. Wu, Y. S. Chen, C. C. Wang, P. J. Tzeng, C. H. Lin, F.
Chen, C. H. Lien, and M. Tsai, “Low power and high speed bipolar switching with
a thin reactive Ti buffer layer in robust HfO2 based RRAM,” IEEE International
Electron Devices Meeting, pp. 297–300, 2008.
[21] Z. Wei, Y. Kanzawa, K. Arita, Y. Katoh, K. Kawai, S. Muraoka, S. Mitani, S. Fujii,
K. Katayama, M. Iijima, T. Mikawa, T. Ninomiya, R. Miyanaga, Y. Kawashima,
K. Tsuji, A. Himeno, T. Okada, R. Azuma, K. Shimakawa, H. Sugaya, T. Takagi,
R. Yasuhara, K. Horiba, H. Kumigashira, and M. Oshima, “Highly reliable TaOx
ReRAM and direct evidence of redox reaction mechanism,” IEEE International
Electron Devices Meeting, pp. 293–296, 2008.
147
[22] W. Kim, S. I. Park, Z. Zhang, Y. Y. Liauw, D. Sekar, H.-S. P. Wong, and S. S.
Wong, “Forming-free nitrogen-doped AlOx RRAM with sub-μA programming
Current,” IEEE Symposium on VLSI Technology, pp. 22-23, 2011.
[23] R. Waser, and M. Aono, “Nanoionics-based resistive switching memories,” Nature
Materials, vol. 6, pp. 833–840, 2007.
[24] I. Valov, R. Waser, J. R. Jameson, and M. N. Kozicki, “Electrochemical
metallization memories--fundamentals, applications, prospects,” Nanotechnology,
vol. 22, no. 25, p. 254003, 2011.
[25] S. Yu, and H.-S. P. Wong, “A phenomenological model for the reset mechanism of
metal oxide RRAM,” IEEE Electron Device Letters, vol. 31, no. 12, pp. 1455–
1457, 2010.
[26] B. Govoreanu, G. S. Kar, Y. Chen, V. Paraschiv, S. Kubicek, A. Fantini, I. P. Radu,
L. Goux, S. Clima, R. Degraeve, N. Jossart, O. Richard, T. Vandeweyer, K. Seo, P.
Hendrickx, G. Pourtois, H. Bender, L. Altimime, D. J. Wouters, J. A. Kittl, and M.
Jurczak, “10×10nm2 Hf /HfOx crossbar resistive RAM with excellent performance ,
reliability and low-energy operation,” IEEE International Electron Devices
Meeting, pp. 729–732, 2011.
[27] J. S. Choi, J.-S. Kim, I. R. Hwang, S. H. Hong, S. H. Jeon, S.-O. Kang, B. H. Park,
D. C. Kim, M. J. Lee, and S. Seo, “Different resistance switching behaviors of NiO
148
thin films deposited on Pt and SrRuO3 electrodes,” Applied Physics Letters, vol. 95,
no. 2, p. 022109, 2009.
[28] C. Rohde, B. J. Choi, D. S. Jeong, S. Choi, J.-S. Zhao, and C. S. Hwang,
“Identification of a determining parameter for resistive switching of TiO2 thin
films,” Applied Physics Letters, vol. 86, no. 26, p. 262907, 2005.
[29] C. Yoshida, K. Tsunoda, H. Noshiro, and Y. Sugiyama, “High speed resistive
switching in Pt∕TiO2∕TiN film for nonvolatile memory application,” Applied
Physics Letters, vol. 91, no. 22, p. 223510, 2007.
[30] W.-Y. Chang, Y.-C. Lai, T.-B. Wu, S.-F. Wang, F. Chen, and M.-J. Tsai,
“Unipolar resistive switching characteristics of ZnO thin films for nonvolatile
memory applications,” Applied Physics Letters, vol. 92, no. 2, p. 022110, 2008.
[31] N. Xu, L. F. Liu, X. Sun, C. Chen, Y. Wang, D. D. Han, X. Y. Liu, R. Q. Han, J. F.
Kang, and B. Yu, “Bipolar switching behavior in TiN/ZnO/Pt resistive nonvolatile
memory with fast switching and long retention,” Semiconductor Science and
Technology, vol. 23, no. 7, p. 075019, 2008.
[32] C. Lin, C. Wu, C. Wu, T. Lee, and F. Yang, “Effect of top electrode material on
resistive switching properties of ZrO2 film memory devices,” IEEE Electron
Device Letters, vol. 28, no. 5, pp. 366–368, 2007.
149
[33] Y.-M. Kim and J.-S. Lee, “Reproducible resistance switching characteristics of
hafnium oxide-based nonvolatile memory devices,” Journal of Applied Physics,
vol. 104, no. 11, p. 114115, 2008.
[34] L. Goux, Y.-Y. Chen, L. Pantisano, X.-P. Wang, G. Groeseneken, M. Jurczak, and
D. J. Wouters, “On the gradual unipolar and bipolar resistive switching of
TiN\HfO2\Pt memory systems,” Electrochemical and Solid-State Letters, vol. 13,
no. 6, p. G54, 2010.
[35] K. M. Kim, B. J. Choi, B. W. Koo, S. Choi, D. S. Jeong, and C. S. Hwang,
“Resistive switching in Pt∕Al2O3∕TiO2∕Ru stacked structures,” Electrochemical and
Solid-State Letters, vol. 9, no. 12, p. G343, 2006.
[36] C.-Y. Lin, C.-Y. Wu, C.-Y. Wu, C. Hu, and T.-Y. Tseng, “Bistable resistive
switching in Al2O3 memory thin films,” Journal of The Electrochemical Society,
vol. 154, no. 9, p. G189, 2007.
[37] M.-J. Lee, C. B. Lee, D. Lee, S. R. Lee, M. Chang, J. H. Hur, Y.-B. Kim, C.-J.
Kim, D. H. Seo, S. Seo, U.-I. Chung, I.-K. Yoo, and K. Kim, “A fast, high-
endurance and scalable non-volatile memory device made from asymmetric Ta2O5-
x/TaO2-x bilayer structures,” Nature Materials, vol. 10, pp. 625–630, 2011.
[38] S.-S. Sheu, M.-F. Chang, K.-F. Lin, C.-W. Wu, Y.-S. Chen, P.-F. Chiu, C.-C. Kuo,
Y.-S. Yang, P.-C. Chiang, W.-P. Lin, C.-H. Lin, H.-Y. Lee, P.-Y. Gu, S.-M. Wang,
150
F. T. Chen, K.-L. Su, C.-H. Lien, K.-H. Cheng, H.-T. Wu, T.-K. Ku, M.-J. Kao,
and M.-J. Tsai, “A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-
write random-access time and 160ns MLC-access capability,” IEEE International
Solid-State Circuits Conference, pp. 200–202, 2011.
[39] A. Kawahara, R. Azuma, Y. Ikeda, K. Kawai, Y. Katoh, K. Tanabe, T. Nakamura,
Y. Sumimoto, N. Yamada, N. Nakai, S. Sakamoto, Y. Hayakawa, K. Tsuji, S.
Yoneda, A. Himeno, K. Origasa, K. Shimakawa, T. Takagi, T. Mikawa, and K.
Aono, “An 8Mb multi-layered cross-point ReRAM macro with 443MB/s write
throughput,” IEEE International Solid-State Circuits Conference, pp. 432–434,
2012.
[40] T.-Y. Liu, T. H. Yan, R. Scheuerlein, Y. Chen, J. K. Lee, G. Balakrishnan, G. Yee,
H. Zhang, A. Yap, J. Ouyang, T. Sasaki, S. Addepalli, A. Al-Shamma, C.-Y. Chen,
M. Gupta, G. Hilton, S. Joshi, A. Kathuria, V. Lai, D. Masiwal, M. Matsumoto, A.
Nigam, A. Pai, J. Pakhale, C. H. Siau, X. Wu, R. Yin, L. Peng, J. Y. Kang, S.
Huynh, H. Wang, N. Nagel, Y. Tanaka, M. Higashitani, T. Minvielle, C. Gorla, T.
Tsukamoto, T. Yamaguchi, M. Okajima, T. Okamura, S. Takase, T. Hara, H. Inoue,
L. Fasoli, M. Mofidi, R. Shrivastava, K. Quader, “A 130.7mm2 2-layer 32Gb
ReRAM memory device in 24nm technology” IEEE International Solid-State
Circuits Conference, pp. 210–212, 2013.
151
[41] W.-C. Chien, M.-H. Lee, Y.-Y. Lin, and K.-Y. Hsieh, “Multi-level 40nm WOx
resistive memory with excellent reliability,” IEEE International Electron Devices
Meeting, pp. 725-728, 2011.
[42] S. R. Lee, Y.-B. Kim, M. Chang, K. M. Kim, C. B. Lee, J. H. Hur, D.-S. Park, D.
Lee, M.-J. Lee, C. J. Kim, U. Chung, I.-K. Yoo, and K. Kim, “Multi-level
switching of triple-layered TaOx RRAM with excellent reliability for storage class
memory,” IEEE Symposium on VLSI Technology, pp. 71-72, 2012.
[43] J. Liang and H.-S. P. Wong, “Cross-point memory array without cell selectors—
device characteristics and data storage pattern dependencies,” IEEE Transactions
on Electron Devices, vol. 57, no. 10, pp. 2531–2538, 2010.
[44] J. Liang, S. Yeh, S. S. Wong, and H.-S. P. Wong, “Effect of wordline/bitline
scaling on the performance, energy consumption, and reliability of cross-point
memory array,” ACM Journal on Emerging Technologies in Computing Systems,
vol. 9, no. 1, p. 9, 2013.
[45] Y. Deng, P. Huang, B. Chen, X. Yang, B. Gao, J. Wang, L. Zeng, G. Du, J. F. Kang,
and X. Y. Liu, “RRAM crossbar array with cell selection device : a device and
circuit interaction study,” IEEE Transactions on Electron Devices, vol. 60, no. 2,
pp. 719–726, 2013.
152
[46] M.-J. Lee, Y. Park, B.-S. Kang, S.-E. Ahn, C. Lee, K. Kim, W. Xianyu, G.
Stefanovich, J.-H. Lee, S.-J. Chung, Y.-H. Kim, C.-S. Lee, J.-B. Park, I.-G. Baek,
and I.-K. Yoo, “2-stack 1D-1R cross-point structure with oxide diodes as switch
elements for high density resistance RAM applications,” IEEE International
Electron Devices Meeting, pp. 771–774, 2007.
[47] G. H. Kim, J. H. Lee, Y. Ahn, W. Jeon, S. J. Song, J. Y. Seok, J. H. Yoon, K. J.
Yoon, T. J. Park, and C. S. Hwang, “32×32 crossbar array resistive memory
composed of a stacked Schottky diode and unipolar resistive memory,” Advanced
Functional Materials, vol. 23, no. 11, pp. 1440–1449, 2013.
[48] J.-J. Huang, Y.-M. Tseng, W.-C. Luo, C.-W. Hsu, and T.-H. Hou, “One selector-
one resistor (1S1R) crossbar array for high-density flexible memory applications,”
IEEE International Electron Devices Meeting, pp. 733–736, 2011.
[49] W. Lee, J. Park, J. Shin, J. Woo, S. Kim, G. Choi, S. Jung, S. Park, D. Lee, E. Cha,
H. D. Lee, S. G. Kim, S. Chung, and H. Hwang, “Varistor-type bidirectional
switch (JMAX>107A/cm2, selectivity~104) for 3D bipolar resistive memory arrays,”
IEEE Symposium on VLSI Technology, pp. 37-38, 2012.
[50] M.-J. Lee, Y. Park, D.-S. Suh, E.-H. Lee, S. Seo, D.-C. Kim, R. Jung, B.-S. Kang,
S.-E. Ahn, C. B. Lee, D. H. Seo, Y.-K. Cha, I.-K. Yoo, J.-S. Kim, and B. H. Park,
153
“Two series oxide resistors applicable to high speed and high density nonvolatile
memory,” Advanced Materials, vol. 19, no. 22, pp. 3919–3923, 2007.
[51] M. Son, J. Lee, J. Park, J. Shin, G. Choi, S. Jung, W. Lee, S. Kim, S. Park, and H.
Hwang, “Excellent selector characteristics of nanoscale VO2 for high-density
bipolar ReRAM applications,” IEEE Electron Device Letters, vol. 32, no. 11, pp.
1579–1581, 2011.
[52] C. Ko and S. Ramanathan, “Observation of electric field-assisted phase transition
in thin film vanadium oxide in a metal-oxide-semiconductor device geometry,”
Applied Physics Letters, vol. 93, no. 25, p. 252101, 2008.
[53] X. Liu, S. M. Sadaf, M. Son, J. Shin, J. Park, J. Lee, S. Park, and H. Hwang,
“Diode-less bilayer oxide (WOx-NbOx) device for cross-point resistive memory
applications.,” Nanotechnology, vol. 22, no. 47, p. 475702, 2011.
[54] S. Kim, X. Liu, J. Park, S. Jung, W. Lee, J. Woo, J. Shin, G. Choi, C. Cho, S. Park,
D. Lee, E. Cha, B.-H. Lee, H. D. Lee, S. G. Kim, S. Chung, and H. Hwang,
“Ultrathin Nb2O5/NbO2 hybrid memory with both memory and selector
characteristics for high density 3D vertically stackable RRAM applications,” IEEE
Symposium on VLSI Technology, pp. 155–156, 2012.
[55] K. Gopalakrishnan, R. S. Shenoy, C. T. Rettner, K. Virwani, D. S. Bethune, R. M.
Shelby, G. W. Burr, A. Kellock, R. S. King, K. Nguyen, A. N. Bowers, M. Jurich,
154
B. Jackson, A. M. Friz, T. Topuria, P. M. Rice, and B. N. Kurdi, “Highly-scalable
novel access device based on mixed ionic electronic conduction (MIEC) materials
for high density phase change memory (PCM) arrays,” IEEE Symposium on VLSI
Technology, pp. 205–206, 2010.
[56] A. Goda, K. Parat, and M. T. January, “Scaling directions for 2D , 3D NAND
Flash cells,” IEEE International Electron Devices Meeting, pp. 13–16, 2012.
[57] H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y.
Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A.
Nitayama, “Bit cost scalable technology with punch and plug process for ultra high
density Flash memory,” IEEE Symposium on VLSI Technology, pp. 14–15, 2007.
[58] W. Kim, S. Choi, J. Sung, T. Lee, C. Park, H. Ko, J. Jung, I. Yoo, and Y. Park,
“Multi-layered vertical gate NAND Flash overcoming stacking limit for terabit
density storage,” IEEE Symposium on VLSI Technology, pp. 188–189, 2009.
[59] J. Jang, H. Kim, W. Cho, H. Cho, J. Kim, S. Il Shim, Y. Jang, J. Jeong, B. Son, D.
W. Kim, K. Kim, J. Shim, J. S. Lim, K. Kim, S. Y. Yi, J. Lim, D. Chung, H. Moon,
S. Hwang, J. Lee, Y. Son, U. Chung, and W. Lee, “Vertical cell array using TCAT
(terabit cell array transistor) technology for ultra high density NAND Flash
memory,” IEEE Symposium on VLSI Technology, pp. 192–193, 2009.
155
[60] M.-J. Lee, S. I. Kim, C. B. Lee, H. Yin, S.-E. Ahn, B. S. Kang, K. H. Kim, J. C.
Park, C. J. Kim, I. Song, S. W. Kim, G. Stefanovich, J. H. Lee, S. J. Chung, Y. H.
Kim, and Y. Park, “Low-temperature-grown transition metal oxide based storage
materials and oxide transistors for high-density non-volatile memory,” Advanced
Functional Materials, vol. 19, no. 10, pp. 1587–1593, 2009.
[61] H. S. Yoon, I. Baek, J. Zhao, H. Sim, M. Y. Park, H. Lee, G. Oh, J. C. Shin, I. Yeo,
and U. Chung, “Vertical cross-point resistance change memory for ultra-high
density non-volatile memory applications,” IEEE Symposium on VLSI Technology,
pp. 26–27, 2009.
[62] I. G. Baek, C. J. Park, H. Ju, D. J. Seong, H. S. Ahn, J. H. Kim, M. K. Yang, S. H.
Song, E. M. Kim, S. O. Park, C. H. Park, C. W. Song, G. T. Jeong, S. Choi, H. K.
Kang, and C. Chung, “Realization of vertical resistive memory (VRRAM) using
cost effective 3D process,” IEEE International Electron Devices Meeting, pp.
737–740, 2011.
[63] W. C. Chien, F. M. Lee, Y. Y. Lin, M. H. Lee, S. H. Chen, C. C. Hsieh, E. K. Lai,
H. H. Hui, Y. K. Huang, C. C. Yu, C. F. Chen, H. L. Lung, K. Y. Hsieh, and C.-Y.
Lu, “Multi-layer sidewall WOx resistive memory suitable for 3D ReRAM,” IEEE
Symposium on VLSI Technology, pp. 153–154, 2012.
156
[64] H.-Y. Chen, S. Yu, B. Gao, P. Huang, J. F. Kang, and H.-S. P. Wong, “HfOx based
vertical resistive random access memory for cost-effective 3D cross-point
architecture without cell selector,” IEEE International Electron Devices Meeting,
pp. 497–500, 2012.
[65] S. Yu, H. Chen, Y. Deng, B. Gao, Z. Jiang, J. F. Kang, and H.-S. P. Wong, “3D
vertical RRAM – scaling limit analysis and demonstration of 3D array operation,”
IEEE Symposium on VLSI Technology, pp. 158–159, 2013.
[66] P.-F. Chiu, M.-F. Chang, C.-W. Wu, C.-H. Chuang, S.-S. Sheu, Y.-S. Chen, and
M.-J. Tsai, “Low store energy, low VDDmin, 8T2R nonvolatile latch and SRAM
with vertical-stacked resistive memory (memristor) devices for low power mobile
applications,” IEEE Journal of Solid-State Circuits, vol. 47, no. 6, pp. 1483–1496,
2012.
[67] Y. Y. Liauw, Z. Zhang, W. Kim, A. E. Gamal, and S. S. Wong, “Nonvolatile 3D-
FPGA with monolithically stacked RRAM-based configuration memory,” IEEE
International Solid-State Circuits Conference, pp. 406–408, 2012.
[68] T. Fujii, M. Kawasaki, A. Sawa, H. Akoh, Y. Kawazoe, and Y. Tokura,
“Hysteretic current–voltage characteristics and resistance switching at an epitaxial
oxide Schottky junction SrRuO3∕SrTi0.99Nb0.01O3,” Applied Physics Letters, vol. 86,
no. 1, p. 012107, 2005.
157
[69] Y. Xia, W. He, L. Chen, X. Meng, and Z. Liu, “Field-induced resistive switching
based on space-charge-limited current,” Applied Physics Letters, vol. 90, no. 2, p.
022907, 2007.
[70] R. Waser, R. Dittmann, G. Staikov, and K. Szot, “Redox-based resistive switching
memories - nanoionic mechanisms, prospects, and challenges,” Advanced
Materials, vol. 21, no. 25–26, pp. 2632–2663, 2009.
[71] J. Y. Son and Y.-H. Shin, “Direct observation of conducting filaments on resistive
switching of NiO thin films,” Applied Physics Letters, vol. 92, no. 22, p. 222106,
2008.
[72] D.-H. Kwon, K. M. Kim, J. H. Jang, J. M. Jeon, M. H. Lee, G. H. Kim, X.-S. Li,
G.-S. Park, B. Lee, S. Han, M. Kim, and C. S. Hwang, “Atomic structure of
conducting nanofilaments in TiO2 resistive switching memory.,” Nature
Nanotechnology, vol. 5, no. 2, pp. 148–53, 2010.
[73] X. Cartoixa, R. Rurali, and J. Sune, “Transport properties of oxygen vacancy
filaments in metal/crystalline or amorphous HfO2/metal structures,” Physical
Review B, vol. 86, no. 16, p. 165445, 2012.
[74] P. Calka, E. Martinez, V. Delaye, D. Lafond, G. Audoit, D. Mariolle, N. Chevalier,
H. Grampeix, C. Cagli, V. Jousseaume, and C. Guedj, “Chemical and structural
158
properties of conducting nanofilaments in TiN/HfO2-based resistive switching
structures.,” Nanotechnology, vol. 24, no. 8, p. 085706, 2013.
[75] S. Privitera, G. Bersuker, B. Butcher, A. Kalantarian, S. Lombardo, C. Bongiorno,
R. Geer, D. C. Gilmer, and P. D. Kirsch, “Microscopy study of the conductive
filament in HfO2 resistive switching memory devices,” Microelectronic
Engineering, vol. 109, pp. 75–78, 2013.
[76] C.-Y. Lin, S.-Y. Wang, D.-Y. Lee, and T.-Y. Tseng, “Electrical properties and
fatigue behaviors of ZrO2 resistive switching thin films,” Journal of The
Electrochemical Society, vol. 155, no. 8, p. H615, 2008.
[77] Q. Liu, W. Guan, S. Long, R. Jia, M. Liu, and J. Chen, “Resistive switching
memory effect of ZrO2 films with Zr+ implanted,” Applied Physics Letters, vol. 92,
no. 1, p. 012117, 2008.
[78] H. Y. Lee, P. Chen, T. Wu, Y. S. Chen, F. Chen, C. Wang, P. Tzeng, C. H. Lin, M.
Tsai, and C. Lien, “HfOx bipolar resistive memory with robust endurance using
AlCu as buffer electrode,” IEEE Electron Device Letters, vol. 30, no. 7, pp. 703–
705, 2009.
[79] S. Yu, X. Guan, and H.-S. P. Wong, “Conduction mechanism of TiN/HfOx/Pt
resistive switching memory: A trap-assisted-tunneling model,” Applied Physics
Letters, vol. 99, no. 6, p. 063507, 2011.
159
[80] G.-H. Buh, I. Hwang, and B. H. Park, “Time-dependent electroforming in NiO
resistive switching devices,” Applied Physics Letters, vol. 95, no. 14, p. 142101,
2009.
[81] M. Fujimoto, H. Koyama, M. Konagai, Y. Hosoi, K. Ishihara, S. Ohnishi, and N.
Awaya, “TiO2 anatase nanolayer on TiN thin film exhibiting high-speed bipolar
resistive switching,” Applied Physics Letters, vol. 89, no. 22, p. 223509, 2006.
[82] G. Bersuker, D. C. Gilmer, D. Veksler, J. Yum, H. Park, S. Lian, L. Vandelli, A.
Padovani, L. Larcher, K. Mckenna, A. Shluger, V. Iglesias, M. Porti, M. Nafria, W.
Taylor, P. D. Kirsch, and R. Jammy, “Metal oxide RRAM switching mechanism
based on conductive filament microscopic properties,” IEEE International
Electron Devices Meeting, pp. 456–459, 2010.
[83] B. Gao, J. F. Kang, Y. S. Chen, F. F. Zhang, B. Chen, P. Huang, L. F. Liu, X. Y.
Liu, Y. Y. Wang, X. A. Tran, Z. R. Wang, H. Y. Yu, and A. Chin, “Oxide-based
RRAM: unified microscopic principle for both unipolar and bipolar switching,”
IEEE International Electron Devices Meeting, pp. 417–420, 2011.
[84] B. Gao, H. W. Zhang, S. Yu, B. Sun, L. F. Liu, X. Y. Liu, Y. Wang, R. Q. Han, J.
F. Kang, B. Yu, and Y. Y. Wang, “Oxide-based RRAM: uniformity improvement
using a new material-oriented methodology,” IEEE Symposium on VLSI
Technology, pp. 30–31, 2009.
160
[85] W. J. Zhu, T.-P. Ma, T. Tamagawa, J. Kim, and Y. Di, “Current transport in
metal/hafnium oxide/silicon structure,” IEEE Electron Device Letters, vol. 23, no.
2, pp. 97–99, 2002.
[86] K. Xiong, J. Robertson, M. C. Gibson, and S. J. Clark, “Defect energy levels in
HfO2 high-dielectric-constant gate oxide,” Applied Physics Letters, vol. 87, no. 18,
p. 183505, 2005.
[87] H. Takeuchi, D. Ha, and T.-J. King, “Observation of bulk HfO2 defects by
spectroscopic ellipsometry,” Journal of Vacuum Science & Technology A: Vacuum,
Surfaces, and Films, vol. 22, no. 4, pp. 1337-1341, 2004.
[88] X. A. Tran, H. Y. Yu, Y. C. Yeo, L. Wu, W. J. Liu, Z. R. Wang, Z. Fang, K. L.
Pey, X. W. Sun, A. Y. Du, B. Y. Nguyen, and M. F. Li, “A High-yield HfOx-based
unipolar resistive RAM employing Ni electrode compatible with Si-diode selector
for crossbar integration,” IEEE Electron Device Letters, vol. 32, no. 3, pp. 396–
398, 2011.
[89] D. S. Jeong and C. S. Hwang, “Tunneling-assisted Poole-Frenkel conduction
mechanism in HfO2 thin films,” Journal of Applied Physics, vol. 98, no. 11, p.
113701, 2005.
161
[90] M. Nardone, V. Kozub, I. Karpov, and V. Karpov, “Possible mechanisms for 1/f
noise in chalcogenide glasses: a theoretical description,” Physical Review B, vol.
79, no. 16, p. 165206, 2009.
[91] J.-K. Lee, H. Y. Jeong, I.-T. Cho, J. Y. Lee, S.-Y. Choi, H.-I. Kwon, and J.-H. Lee,
“Conduction and low-frequency noise analysis in Al/α-TiOx/Al bipolar switching
resistance random access memory devices,” IEEE Electron Device Letters, vol. 31,
no. 6, pp. 603–605, 2010.
[92] S. B. Lee, S. Park, J. S. Lee, S. C. Chae, S. H. Chang, M. H. Jung, Y. Jo, B. Kahng,
B. S. Kang, M.-J. Lee, and T. W. Noh, “Large 1/f noise of unipolar resistance
switching and its percolating nature,” Applied Physics Letters, vol. 95, no. 12, p.
122112, 2009.
[93] G. Jegert, A. Kersch, W. Weinreich, U. Schroder, and P. Lugli, “Modeling of
leakage currents in high-κ dielectrics: three-dimensional approach via kinetic
Monte Carlo,” Applied Physics Letters, vol. 96, no. 6, p. 062113, 2010.
[94] C. Walczyk, C. Wenger, R. Sohal, M. Lukosius, A. Fox, J. Dabrowski, D.
Wolansky, B. Tillack, H.-J. Mussig, and T. Schroeder, “Pulse-induced low-power
resistive switching in HfO2 metal-insulator-metal diodes for nonvolatile memory
applications,” Journal of Applied Physics, vol. 105, no. 11, p. 114103, 2009.
162
[95] J. T. S. Irvine, D. C. Sinclair, and A. R. West, “Electroceramics: characterization
by impedance spectroscopy,” Advanced Materials, vol. 2, no. 3, pp. 132–138,
1990.
[96] Y.-H. You, B.-S. So, J.-H. Hwang, W. Cho, S. S. Lee, T.-M. Chung, C. G. Kim,
and K.-S. An, “Impedance spectroscopy characterization of resistance switching
NiO thin films prepared through atomic layer deposition,” Applied Physics Letters,
vol. 89, no. 22, p. 222105, 2006.
[97] M. H. Lee, K. M. Kim, G. H. Kim, J. Y. Seok, S. J. Song, J. H. Yoon, and C. S.
Hwang, “Study on the electrical conduction mechanism of bipolar resistive
switching TiO2 thin films using impedance spectroscopy,” Applied Physics Letters,
vol. 96, no. 15, p. 152909, 2010.
[98] A. K. Jonscher, “Dielectric relaxation in solids,” Journal of Physics D: Applied
Physics, vol. 32, p. R57, 1999.
[99] S. R. Elliott, “A.C. conduction in amorphous chalcogenide and pnictide
semiconductors,” Advances in Physics, vol. 36, no. 2, pp. 135–217, 1987.
[100] P. Gonon, M. Mougenot, C. Vallee, C. Jorel, V. Jousseaume, H. Grampeix, and F.
E. Kamel, “Resistance switching in HfO2 metal-insulator-metal devices,” Journal
of Applied Physics, vol. 107, no. 7, p. 074507, 2010.
163
[101] B. Gao, J. F. Kang, L. F. Liu, X. Y. Liu, and B. Yu, “A physical model for bipolar
oxide-based resistive switching memory based on ion-transport-recombination
effect,” Applied Physics Letters, vol. 98, no. 23, p. 232108, 2011.
[102] T. Tsuruoka, K. Terabe, T. Hasegawa, and M. Aono, “Forming and switching
mechanisms of a cation-migration-based oxide resistive memory,”
Nanotechnology, vol. 21, no. 42, p. 425205, 2010.
[103] D. B. Strukov and R. S. Williams, “Exponential ionic drift: fast switching and low
volatility of thin-film memristors,” Applied Physics A, vol. 94, no. 3, pp. 515–519,
2008.
[104] B. Gao, J. F. Kang, H. W. Zhang, B. Sun, B. Chen, L. F. Liu, X. Y. Liu, R. Q. Han,
Y. Y. Wang, B. Yu, Z. Fang, H. H. Yu, and D.-L. Kwong, “Oxide-based RRAM:
physical based retention projection,” IEEE European Solid-State Device Research
Conference, pp. 392–395, 2010.
[105] J. McPherson, J.-Y. Kim, A. Shanware, and H. Mogul, “Thermochemical
description of dielectric breakdown in high dielectric constant materials,” Applied
Physics Letters, vol. 82, no. 13, pp. 2121-2123, 2003.
[106] B. Gao, B. Sun, H. W. Zhang, L. F. Liu, X. Y. Liu, R. Q. Han, J. F. Kang, and B.
Yu, “Unified physical model of bipolar oxide-based resistive switching memory,”
IEEE Electron Device Letters, vol. 30, no. 12, pp. 1326–1328, 2009.
164
[107] N. Xu, B. Gao, L. F. Liu, B. Sun, X. Y. Liu, R. Q. Han, J. F. Kang, and B. Yu, “A
unified physical model of switching behavior in oxide-based RRAM,” IEEE
Symposium on VLSI Technology, pp. 100–101, 2008.
[108] K. Kinoshita, K. Tsunoda, Y. Sato, H. Noshiro, S. Yagaki, M. Aoki, and Y.
Sugiyama, “Reduction in the reset current in a resistive random access memory
consisting of NiOx brought about by reducing a parasitic capacitance,” Applied
Physics Letters, vol. 93, no. 3, p. 033506, 2008.
[109] Y. S. Chen, H. Y. Lee, P. S. Chen, P. Y. Gu, C. W. Chen, W. P. Lin, W. H. Liu, Y.
Y. Hsu, S. S. Sheu, P. C. Chiang, W. S. Chen, F. T. Chen, C. H. Lien, and M.-J.
Tsai, “Highly scalable hafnium oxide memory with improvements of resistive
distribution and read disturb immunity,” IEEE International Electron Devices
Meeting, pp. 105–108, 2009.
[110] H. Y. Lee, Y. S. Chen, P. S. Chen, P. Y. Gu, Y. Y. Hsu, S. M. Wang, W. H. Liu, C.
H. Tsai, S. S. Sheu, P. C. Chiang, W. P. Lin, C. H. Lin, W. S. Chen, F. T. Chen, C.
H. Lien, and M.-J. Tsai, “Evidence and solution of over-RESET problem for HfOx
based resistive memory with sub-ns switching speed and high endurance,” IEEE
International Electron Devices Meeting, pp. 460–461, 2010.
[111] Z. Fang, H. Y. Yu, X. Li, N. Singh, G. Q. Lo, and D. L. Kwong,
“HfOx/TiOx/HfOx/TiOx multilayer-based forming-free RRAM devices with
165
excellent uniformity,” IEEE Electron Device Letters, vol. 32, no. 4, pp. 566–568,
2011.
[112] X. Guan, S. Yu, and H.-S. P. Wong, “A SPICE compact model of metal oxide
resistive switching memory with variations,” IEEE Electron Device Letters, vol.
33, no. 10, pp. 1405–1407, 2012.
[113] U. Russo, D. Ielmini, C. Cagli, A. L. Lacaita, “Self-accelerated thermal dissolution
model for reset programming in unipolar resistive-switching memory (RRAM)
devices,” IEEE Transactions on Electron Devices, vol. 56, no. 2, pp. 193–200,
2009.
[114] C. Cagli, F. Nardi, and D. Ielmini, “Modeling of set/reset operations in NiO-based
resistive-switching memory devices,” IEEE Transactions on Electron Devices, vol.
56, no. 8, pp. 1712–1720, 2009.
[115] U. Russo, D. Ielmini, C. Cagli, A. L. Lacaita, “Filament conduction and reset
mechanism memory (RRAM) devices,” IEEE Transactions on Electron Devices,
vol. 56, no. 2, pp. 186–192, 2009.
[116] Y. S. Chen, J. F. Kang, B. Chen, B. Gao, L. F. Liu, X. Y. Liu, Y. Y. Wang, L. Wu,
H. Y. Yu, J. Y. Wang, Q. Chen, and E. G. Wang, “Microscopic mechanism for
unipolar resistive switching behaviour of nickel oxides,” Journal of Physics D:
Applied Physics, vol. 45, no. 6, p. 065303, 2012.
166
[117] G. Bersuker, D. C. Gilmer, D. Veksler, P. Kirsch, L. Vandelli, A. Padovani, L.
Larcher, K. McKenna, A. Shluger, V. Iglesias, M. Porti, and M. Nafria, “Metal
oxide resistive memory switching mechanism based on conductive filament
properties,” Journal of Applied Physics, vol. 110, no. 12, p. 124518, 2011.
[118] L. Vandelli, A. Padovani, L. Larcher, G. Broglia, G. Ori, M. Montorsi, G.
Bersuker, and P. Pavan, “Comprehensive physical modeling of forming and
switching operations in HfO2 RRAM devices,” IEEE International Electron
Devices Meeting, pp. 421–424, 2011.
[119] R. Degraeve, A. Fantini, S. Clima, B. Govoreanu, L. Goux, Y. Y. Chen, D. J.
Wouters, P. Roussel, G. S. Kar, G. Pourtois, S. Cosemans, J. A. Kittl, G.
Groeseneken, M. Jurczak, and L. Altimime, “Dynamic ‘hour glass’ model for set
and reset in HfO2 RRAM,” IEEE Symposium on VLSI Technology, pp. 75–76,
2012.
[120] C. Mead, “Neuromorphic electronic systems,” Proceedings of the IEEE, vol. 78,
no. 10, pp. 1629–1636, 1990.
[121] C.-S. Poon, and K. Zhou, “Neuromorphic silicon neurons and large-scale neural
networks: challenges and opportunities.,” Frontiers in Neuroscience, vol. 5, p. 108,
2011.
167
[122] Q. V. Le, M. A. Ranzato, M. Devin, G. S. Corrado, and A. Y. Ng, “Building high-
level features using large scale unsupervised learning,” International Conference
in Machine Learning, 2012.
[123] R. Ananthanarayanan, S. K. Esser, H. D. Simon, and D. S. Modha, “The cat is out
of the bag : cortical simulations with 109 neurons, 1013 synapses,” Conference on
High Performance Computing Networking, Storage and Analysis, 2009.
[124] G. Indiveri, E. Chicca, and R. Douglas, “A VLSI array of low-power spiking
neurons and bistable synapses with spike-timing dependent plasticity,” IEEE
Transactions on Neural Networks, vol. 17, no. 1, pp. 211–21, 2006.
[125] P. Merolla, J. Arthur, F. Akopyan, N. Imam, R. Manohar, and D. S. Modha, “A
digital neurosynaptic core using embedded crossbar memory with 45pJ per spike
in 45nm,” IEEE Custom Integrated Circuits Conference, 2011.
[126] G. S. Snider, “Self-organized computation with unreliable, memristive
nanodevices,” Nanotechnology, vol. 18, no. 36, p. 365202, 2007.
[127] O. Bichler, M. Suri, D. Querlioz, D. Vuillaume, B. DeSalvo, and C. Gamrat,
“Visual pattern extraction using energy-efficient ‘2-PCM synapse’ neuromorphic
architecture,” IEEE Transactions on Electron Devices, vol. 59, no. 8, pp. 2206–
2214, 2012.
168
[128] D. Kuzum, R. G. D. Jeyasingh, B. Lee, and H.-S. P. Wong, “Nanoelectronic
programmable synapses based on phase change materials for brain-inspired
computing,” Nano Letters, vol. 12, no. 5, pp. 2179–2186, 2012.
[129] S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu,
“Nanoscale memristor device as synapse in neuromorphic systems,” Nano letters,
vol. 10, no. 4, pp. 1297–1301, 2010.
[130] T. Ohno, T. Hasegawa, T. Tsuruoka, K. Terabe, J. K. Gimzewski, and M. Aono,
“Short-term plasticity and long-term potentiation mimicked in single inorganic
synapses.,” Nature Materials, vol. 10, no. 8, pp. 591–595, 2011.
[131] K. Seo, I. Kim, S. Jung, M. Jo, S. Park, J. Park, J. Shin, K. P. Biju, J. Kong, K. Lee,
B. Lee, and H. Hwang, “Analog memory and spike-timing-dependent plasticity
characteristics of a nanoscale titanium oxide bilayer resistive switching device,”
Nanotechnology, vol. 22, no. 25, p. 254023, 2011.
[132] T. Chang, S.-H. Jo, and W. Lu, “Short-term memory to long-term memory
transition in a nanoscale memristor,” ACS Nano, vol. 5, no. 9, pp. 7669–7676,
2011.
[133] E. Kandel, J. Schwartz, and T. Jessell, Principles of Neural Science, Fourth
Edition. McGraw-Hill Medical, 2000.
169
[134] S. Song, K. D. Miller, and L. F. Abbott, “Competitive Hebbian learning through
spike-timing-dependent synaptic plasticity,” Nature Neuroscience, vol. 3, no. 9, pp.
919–926, 2000.
[135] G. Q. Bi, and M. M. Poo, “Synaptic modifications in cultured hippocampal
neurons: dependence on spike timing, synaptic strength, and postsynaptic cell type,”
Journal of Neuroscience, vol. 18, no. 24, pp. 10464–10472, 1998.
[136] W. Senn, and S. Fusi, “Convergence of stochastic learning in perceptrons with
binary synapses,” Physical Review E, vol. 71, no. 6, p. 061907, 2005.
[137] C. Zamarreno-Ramos, L. A Camunas-Mesa, J. A Perez-Carrasco, T. Masquelier, T.
Serrano-Gotarredona, and B. Linares-Barranco, “On spike-timing-dependent-
plasticity, memristive devices, and building a self-learning visual cortex,”
Frontiers in Neuroscience, vol. 5, p. 26, 2011.
[138] M. Suri, O. Bichler, D. Querlioz, G. Palma, E. Vianello, D. Vuillaume, C. Gamrat,
and B. DeSalvo, “CBRAM devices as binary synapses for low-power stochastic
neuromorphic systems: auditory (cochlea) and visual (retina) cognitive processing
applications,” IEEE International Electron Devices Meeting, pp. 235–238, 2012.
[139] D. Querlioz, O. Bichler, and C. Gamrat, “Simulation of a memristor-based spiking
neural network immune to device variations,” International Joint Conference on
Neural Networks, pp. 1775–1781, 2011.
170
[140] D. Kuzum, R. G. D. Jeyasingh, S. Yu, and H.-S. P. Wong, “Low-energy robust
neuromorphic computation using synaptic devices,” IEEE Transactions on
Electron Devices, vol. 59, no. 12, pp. 3489–3494, 2012.
171
Author’s Biography
Shimeng Yu received the B.S. degree in microelectronics from Peking University in
2009, and the M.S. degree and Ph.D. degree in electrical engineering from Stanford
University in 2011, and in 2013, respectively. He joined Arizona State University as
assistant professor of computer engineering and electrical engineering in the fall of 2013.
He did summer internships in IMEC, Belgium in 2011, and IBM TJ Watson Research
Center, Yorktown Heights, New York, in 2012.
He has been working on the fabrication, characterization, and modeling of oxide based
resistive random access memory (RRAM) since 2008. He has also pioneered the use of
artificial synaptic device design for neuromorphic applications. His works have been
widely recognized in this field. By the end of his PhD study, his publications have been
cited over 500 times, with h-index 14.
His general research interests are the fundamental physics exploration of the emerging
device technologies and their applications for future computing paradigms, such as 3D
memory integration, embedded memory, logic-in-memory, reconfigurable computing,
bio-inspired neuromorphic computing, etc.
He has been the recipients of numerous awards due to his outstanding research
achievements, including Stanford Graduate Fellowship (SGF) from 2009 to 2012, IEEE
Electron Device Society Masters Student Fellowship in 2010 and PhD Student
Fellowship in 2012, Chinese Government Fellowship for Outstanding Self-Financed
Students Abroad in 2012, Qualcomm Fellowships for the 2013 Telluride Workshop, etc.
172
Publications
Book chapters
1) S. Yu, B. Lee, and H.-S. P. Wong, “Metal oxide resistive switching memory”,
Functional Metal Oxide Nanostructures, Springer, 2011, invited review.
Journal papers:
1) S. Yu, B. Gao, Z. Fang, H. Y. Yu, J. F. Kang, and H.-S. P. Wong, “A low energy
oxide-based electronic synaptic device for neuromorphic visual system with
tolerance to device variation”, Adv. Mater., vol. 25, no. 12, pp. 1774-1779, 2013.
2) S. Yu, H.-Y. Chen, B. Gao, J. F. Kang, and H.-S. P. Wong, “A HfOx based
vertical resistive switching random access memory for bit-cost-effective three-
dimensional cross-point architecture”, ACS Nano, vol. 7, no. 3, pp. 2320-2325,
2013.
3) H. Tian, H.-Y. Chen, B. Gao, S. Yu, J. Liang, Y. Yang, D. Xie, J. Kang, T.-L.
Ren, Y. Zhang, and H.-S. P. Wong, “Monitoring oxygen movement by Raman
spectroscopy of resistive random access memory with a graphene-inserted
electrode”, Nano Lett., vol. 13, no. 2, pp. 651-657, 2013.
4) D. Kuzum, S. Yu, and H.-S. P. Wong, “Synaptic electronics: materials, devices
and applications”, Nanotechnology, 2013, invited review.
5) S. Yu, R. Jeyasingh, Y. Wu, and H.-S. P. Wong, “Characterization of low-
frequency noise in the resistive switching of transition metal oxide HfO2”, Phys.
Rev. B, vol. 85, 045324, 2012.
6) X. Guan, S. Yu, and H.-S. P. Wong, “On the switching parameter variation of
metal oxide RRAM - part I: physical modeling and simulation methodology”,
IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1172-1182, 2012.
173
7) S. Yu, X. Guan, and H.-S. P. Wong, “On the switching parameter variation of
metal oxide RRAM - part II: model corroboration and device design strategy”,
IEEE Trans. Electron Devices, vol. 59 no. 4, pp. 1183-1189, 2012.
8) S. Yu, Y. Y. Chen, X. Guan, H.-S. P. Wong, J. A. Kittl, “A Monte Carlo study of
the low resistance state retention of HfOx based resistive switching memory”,
Appl. Phys. Lett., vol. 100, 043507, 2012.
9) X. Guan, S. Yu, and H.-S. P. Wong, “A SPICE compact model of metal oxide
resistive switching memory with variations”, IEEE Electron Device Lett., vol.
33, no. 10, pp. 1405-1407, 2012.
10) D. Kuzum, R. Jeyasingh, S. Yu, and H.-S. P. Wong, “Low energy, robust
neuromorphic computation using synaptic devices”, IEEE Trans. Electron
Devices, vol. 59, no. 12, pp. 3489-3494, 2012.
11) H.-S. P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, B. Lee, F. T.
Chen, and M.-J. Tsai, “Metal oxide RRAM”, Proc. IEEE, vol. 100, no. 6, pp.
1951-1970, 2012, invited review.
12) S. Yu, R. Jeyasingh, Y. Wu, and H.-S. P. Wong, “AC conductance measurement
and analysis of the conduction processes in HfOx based resistive switching
memory”, Appl. Phys. Lett., vol. 99, 232105, 2011.
13) S. Yu, X. Guan, and H.-S. P. Wong, “Conduction mechanism of TiN/HfOx/Pt
resistive switching memory: a trap-assisted-tunneling model”, Appl. Phys. Lett.,
vol. 99, 063507, 2011.
14) S. Yu, Y. Wu, and H.-S. P. Wong, “Investigating the switching dynamics and
multilevel capability of bipolar metal oxide resistive switching memory”, Appl.
Phys. Lett., vol. 98, 103514, 2011.
15) S. Yu, Y. Wu, R. Jeyasingh, D. Kuzum, and H.-S. P. Wong, “An electronic
synapse device based on metal oxide resistive switching memory for
neuromorphic computation”, IEEE Trans. Electron Devices, vol. 58, no. 8, pp.
2729-2737, 2011.
174
16) S. Yu, and H.-S. P. Wong, “Compact modeling of conducting bridge random
access memory (CBRAM)”, IEEE Trans. Electron Devices, vol. 58, no. 5, pp.
1352-1360, 2011.
17) Y. Wu, S. Yu, B. Lee, and H.-S. P. Wong, “Low-power TiN/Al2O3/Pt resistive
switching device with sub-20 µA switching current and gradual resistance
modulation”, J. Appl. Phys. vol. 110, 094104, 2011.
18) Y. Chai, Y. Wu, K. Takei, H.-Y. Chen, S. Yu, P. C. H. Chan, A. Javey, and H.-S.
P. Wong, “Nanoscale bipolar and complementary resistive switching memory
based on amorphous carbon”, IEEE Trans. Electron Devices, vol. 58, no. 11, pp.
3933-3939, 2011.
19) S. Yu, and H.-S. P. Wong, “A phenomenological model for the reset mechanism
of metal oxide RRAM”, IEEE Electron Device Lett. vol. 31, no. 12, pp.1455-
1457, 2010.
20) S. Yu, J. Liang, Y. Wu, and H.-S. P. Wong, “Read/write schemes analysis for the
novel complementary resistive switches in passive crossbar memory arrays”,
Nanotechnology, vol. 21, 465202, 2010.
Conference papers:
1) S. Yu, H.-Y. Chen, Y. Deng, B. Gao, Z. Jiang, J. F. Kang, and H.-S. P. Wong,
“3D vertical RRAM - scaling limit analysis and demonstration of 3D array
operation”, Symposium on VLSI Technology 2013, pp. 158-159, Kyoto, Japan.
2) D. Kuzum, R. J. D. Jeyasingh, S. B. Eryilmaz, S. Yu, and H.-S. P. Wong,
“Programming phase change synaptic devices for neuromorphic computation”,
MRS Spring Meeting 2013, San Francisco, USA, invited.
3) S. Yu, and H.-S. P. Wong, “Characterization and modeling of the conduction and
switching mechanism of HfOx based RRAM”, MRS Fall Meeting 2013, Boston,
USA, invited.
175
4) Y. Wu, S. Yu, H.-Y. Chen, J. Liang, Z. Jiang, and H.-S. P. Wong, "Resistive
switching random access memory (RRAM): materials, device, scaling, and array
design”, 60th International Symposium of the American Vacuum Society (AVS)
2013, Long Beach, CA, USA, invited.
5) H.-Y. Chen, S. Yu, Y. Wu, and H.-S. P. Wong, “3D vertical RRAM architecture
and electrode/oxide interface engineering for next generation mass
storage”, International Conference on Solid State Devices and Materials (SSDM)
2013, Fukuoka, Japan, invited.
6) C.-S. Lee, S. Yu, X. Guan, J. Luo, L. Wei, and H.-S. P. Wong, “Compact models
of emerging devices”, International Conference of Electron Devices and Solid-
State Circuits (EDSSC) 2013, Hong Kong, invited.
7) S. Yu, B. Gao, Z. Fang, H. Y. Yu, J. F. Kang, and H.-S. P. Wong, “A
neuromorphic visual system using RRAM synaptic devices with sub-pJ energy
and tolerance to variability: experimental characterization and large-scale
modeling”, IEEE International Electron Devices Meeting (IEDM) 2012, pp. 239-
242, San Francisco, USA.
8) S. Yu, X. Guan, and H.-S. P. Wong, “Understanding metal oxide RRAM current
overshoot and reliability using Kinetic Monte Carlo simulation”, IEEE
International Electron Devices Meeting (IEDM) 2012, pp. 585-588, San
Francisco, USA.
9) H.-Y. Chen, S. Yu, B. Gao, P. Huang, J. F. Kang, and H.-S. P. Wong, “HfOx
based vertical RRAM for cost-effective 3D cross-point architecture without cell
selector”, IEEE International Electron Devices Meeting (IEDM) 2012, pp. 497-
500, San Francisco, USA.
10) H.-Y. Chen, H. Tian, B. Gao, S. Yu, J. Liang, J. Kang, Y. Zhang, T.-L. Ren, and
H.-S. P. Wong, “Electrode/oxide interface engineering by inserting single-layer
graphene: application for HfOx-based resistive random access memory”, IEEE
176
International Electron Devices Meeting (IEDM) 2012, pp. 489-492, San
Francisco, USA.
11) Y. Wu, S. Yu, H.-S. P. Wong, Y.-S. Chen, H.-Y. Lee, S.-M. Wang, P.-Y. Gu, F.
Chen, and M.-J. Tsai, “AlOx-based resistive switching device with gradual
resistance modulation for neuromorphic device application”, IEEE International
Memory Workshop (IMW) 2012, pp. 111-114, Milan, Italy.
12) H.-S. P. Wong, X. Guan, D. Kuzum, R. Jeyasingh, and S. Yu, “Variability in
emerging memory devices: physical understanding, modeling, and mitigation”,
IEEE Workshop on Variability Modeling and Characterization (VMC) 2012, San
Jose, USA, invited.
13) Y. Wu, J. Liang, S. Yu, X. Guan, and H.-S. P. Wong, “Resistive switching
random access memory - materials, device, interconnects, and scaling
considerations”, IEEE International Integrated Reliability Workshop (IIRW)
2012, Lake Tahoe, USA, invited.
14) Y. Wu, S. Yu, X. Guan, and H.-S. P. Wong, “Recent progress of resistive
switching random access memory (RRAM)”, IEEE Silicon Nanoelectronics
Workshop (SNW) 2012, Hawaii, USA, invited.
15) X. Guan, S. Yu, and H.-S. P. Wong, “On the variability of HfOx RRAM: from
numerical simulation to compact modeling”, IEEE Workshop on Compact
Modeling (WCM) 2012, Santa Clara, CA, USA, invited.
16) S. Yu, R. Jeyasingh, Y. Wu, and H.-S. P. Wong, “Understanding the conduction
and switching mechanism of metal oxide RRAM through low frequency noise
and AC conductance measurement and analysis”, IEEE International Electron
Devices Meeting (IEDM) 2011, pp. 275-278, Washington DC, USA.
17) S. Yu, X. Guan, and H.-S. P. Wong, “On the stochastic nature of resistive
switching in metal oxide RRAM: physical modeling, Monte Carlo simulation, and
experimental characterization”, IEEE International Electron Devices Meeting
(IEDM) 2011, pp. 413-416, Washington DC, USA.
177
18) S. Yu, Y. Wu, Y. Chai, J. Provine and H.-S. P. Wong, “Characterization of
switching parameters and multilevel capability in HfOx/AlOx bi-layer RRAM
devices”, International Symposium on VLSI Technology, Systems and
Applications (VLSI-TSA) 2011, pp. 106-107, Hsinchu, Taiwan.
19) Y. Wu, Y. Chai, H.-Y. Chen, S. Yu, and H.-S. P. Wong, “Resistive switching
AlOx-based memory with CNT electrode for ultra-low switching current and high
density memory application”, Symposium on VLSI Technology 2011, pp. 26-27,
Kyoto, Japan.
20) H.-S. P. Wong, S. Kim, B. Lee, M. A. Caldwell, J. Liang, Y. Wu, R. Jeyasingh,
and S. Yu, “Recent progress of phase change memory (PCM) and resistive
switching random access memory (RRAM)”, IEEE International Memory
Workshop (IMW) 2011, pp. 10-14, Monterey, USA, invited.
21) S. Yu, and H.-S. P. Wong, “Modeling the switching dynamics of programmable-
metallization cell (PMC) memory and its application as synapse device for a
neuromorphic computation system”, IEEE International Electron Devices
Meeting (IEDM) 2010, pp. 520-523, San Francisco, USA.
22) S. Yu, and H.-S. P. Wong, “A phenomenological model of oxygen ion transport
for metal oxide resistive switching memory”, IEEE International Memory
Workshop (IMW) 2010, pp. 54-57, Seoul, Korea.
23) Y. Chai, Y. Wu, K. Takei, H.-Y. Chen, S. Yu, P. C. H. Chan, A. Javey, and H.-S.
P. Wong, “Resistive switching of carbon-based RRAM with CNT electrodes for
ultra-dense memory”, IEEE International Electron Devices Meeting (IEDM)
2010, pp. 214-217, San Francisco, USA.
24) H.-S. P. Wong, S. Kim, B. Lee, M. A. Caldwell, J. Liang, Y. Wu, R. Jeyasingh,
and S. Yu, “Recent progress of phase change memory (PCM) and resistive
switching random access memory (RRAM)”, IEEE International Conference on
Solid-State and Integrated Circuits Technology (ICSICT) 2010, pp. 1055-1060,
Shanghai, China, invited.
178
25) Y. Wu, S. Yu, B. Lee and H.-S. P. Wong, “Gradual set and reset in TiN/Al2O3/Pt
resistive switching device with sub-20 µA current”, MRS Fall Meeting 2010,
paper K4.2, Boston, USA.