research unit 3 - imsims.unipv.it/firb2006/workshop/unit3.pdf · 2010. 11. 12. · cmos path linear...

FIRB - ACCORDO DI PROGRAMMA

RESEARCH UNIT 3

1 - University of Pavia – Microelectronics Laboratory – R. Castello

2 - University of Pavia – Instrumentation Laboratory – L. Ratti

Speaker: D. Manstretta (1)

4 Novembre 2010 1 di

Laboratorio di Microelettronica Laboratorio di Strumentazione Elettronica RESEARCH UNIT 3

L. Ratti, L. Gaioni, M. Manghisoni, V. Re, V. Speziali, G. Traversi

3D deep N-well MAPS with sparse readout for high resolution, highly efficient particle tracking

Task 1.6 - Low-noise Analog Design

CMOS compatible bipolar transistors in a 65 nm technology

L. Ratti, S. Zucca, M. Manghisoni

Instrumentation Laboratory

COMPLETED

ONGOING


  A DNW is used to collect the charge released in the substrate   A classical readout for capacitive detectors is used for Q-V conversion   NMOS devices for the analog section are built in the deep N-well   PMOS devices can be included in the front-end with good efficiency

DEEP N-well Monolithic Active Pixel Sensors MAPS

Deep N-well structure

NMOS PMOS

Buried N-type layer P-well

P-substrate

++ ++

---

-

Potential drawbacks •  cross-talk and charge collection efficiency degradation •  small area for the digital FE detection efficiency degradation


VERTICAL INTEGRATION (3D) TECHNOLOGIES

•  Electrically isolated connections through the silicon vias (TSV)

•  Substrate thinning (below 50 µm) •  Inter-layer alignment and mechanical/

electrical bonding

  3D processes enabling steps:

  Tezzaron Semiconductor technology can be used to vertically integrate two layers specifically processed by Chartered Semiconductor

1 st wafer 2

nd wafer WB/BB pad

TSV

Inter-tier bond pads


MIGRATION TO 3D PROCESS

Analog section Digital section

DNW sensor

P-well N-well NMOS

PMOS

Digital section

DNW sensor Analog section

  Separate analog and digital sections minimize cross-talk

•  Tier 1: collecting electrode (deep N-well/P-substrate junction) and analog front-end and discriminator

•  Tier 2: digital front-end and digital back-end


PUBLICATIONS

L. Ratti, L. Gaioni, M. Manghisoni, V. Re, G. Traversi, ``Vertically integrated monolithic pixel sensors for charged particle tracking and biomedical imaging'',Nucl. Instrum. Methods, doi:10.1016/j.nima.2010.09.084.

L. Ratti, L. Gaioni, M. Manghisoni, V. Re, G. Traversi, ``Vertically integrated deep N-well CMOS MAPS with sparsification and time stamping capabilities for thin charged particle trackers'',Nucl. Instrum. Methods, doi:10.1016/j.nima.2010.05.039.

W. Dulinski, G. Bertolone, R. de Masi, Y. Degerli, A. Dorokhov,F. Morel, F. Orsini, L. Ratti, C. Santos, V. Re, X. Wei, M. Winter, ''Thin, fully depleted monolithic active pixel sensor based on 3D integration of heterogeneous CMOS layers'',2009 IEEE Nuclear Science Symposium Conference Record, pp.~1165-1168, 25-31 Oct. 2009.

L. Ratti, L. Gaioni, M. Manghisoni, V. Re, V. Speziali,G. Traversi, ``3D deep N-well MAPS with sparse readout for highresolution, highly efficient particle tracking'', 7thInternational Meeting on Front-End Electronics, Montauk, USA, May18-21 2009.

W. Dulinski, G. Bertolone, Y. Degerli, A. Dorokhov, F. Morel, L. Ratti, V. Re, X. Wei, ``Ultra Thin, Fully Depleted MAPS based on 3D Integration of Heterogeneous CMOS Layers'', 7thInternational Meeting on Front-End Electronics, Montauk, USA, May18-21 2009.


Bipolar devices developed in a standard CMOS process (65 nm) with no additional masks to take advantage of their better analog performance

DUTs are single NPN bipolar junction transistors with different layout geometry, junction area and base length

Devices characterized from the standpoint of static and noise behavior

Physical device model developed for simulations and device improvements

CMOS COMPATIBLE BJTs


Results compatible with spreading resistance values in the order of a few hundred Ohms

White noise in the collector current

Measured white noise in the collector current is compared to theoretical noise based on static parameter extraction

NOISE MEASUREMENTS

Flicker noise corner frequency of a few kHz


2D device model developed to reproduce experimental results

Starting point to design devices with improved performance

Will implement a 3D model for more accurate device design and more reliable simulations

Performed with a technology CAD tool provided by Synopsys and based on finite elements methods

Simulated device after meshing with doping concentration in a color scale

DEVICE SIMULATION


Research Activities - Targets

•  Task 1.4 – Advanced RF Design

–  Efficient TX architectures COMPLETED

–  Wideband DCO COMPLETED

–  Complete TX, including ADPLL ONGOING

–  Analog baseband COMPLETED

–  WCDMA Transmitter ONGOING

–  Integrated PA for cellular applications COMPLETED

–  PA efficiency enhancement techniques ONGOING

•  Task 1.5 – RF Bodynet and RFID

–  Micropower, low-data rate applications standard (Zig-Bee)

–  RX front-end COMPLETED

–  TRX including: FLL for direct modulation, analog BB / PA ONGOING

Microelectronics Laboratory


An All-Digital PLL with fine resolution DCO for Cellular TX

T1.4 – Advanced RF Design

L. Fanori, A. Liscidini, R. Castello



DCO DESIGN

DCO fine tuning bank: Thanks to “shrinking” effect equivalent CLSB < 1aF

Shrinking factor ~100


RESULTS SUMMARY RESULTS TABLE

This work [1] [2] [3] [4] [5] [6] Center Frequency [GHz] 3 3.6 7.75 1.7 4 10.4 3.35

Tuning Range [MHz] 780 900 2800 132 1000 1050 600

Frequency Resolution [kHz] 0.15-1.5(a) 12(b) 3.2 150 200 1030 5

Power Supply [V] 1.8 1.4 1.2 0.5 2.5 1.1 1.2

Current Consumption [mA] 16 18 16 0.372 3.2 3 2

Phase Noise@1 MHz [dBc/Hz] -127.5 -126 -118 -109 -114 -102 -118

FoM dBc/Hz 183 183 183 181 177 177 185

Technology 65 nm 90 nm 65 nm 130 nm 130 nm 65 nm 90 nm (a)  Programmable by the bias current (b)  Frequency resolu7on without dithering [1] R. Staszewski et al.

[2] Y. Chen et al. [3] N.M Pletcher and J.M. Rabaey

[4] T. PiKorino, Y. Chen et al. [5] Nicola Da Dalt et al. [6] J. Zhaung, Q. Du, T. Kwasnie

RELATED PUBLICATIONS: •  L. Fanori, A. Liscidini, R. Castello,” 3.3GHz DCO with frequency resolution of 150Hz for

All-digital PLL ” IEEE ISSCC Feb. 2010. •  L. Fanori, A. Liscidini, R. Castello,“ Capacitive degeneration in LC tank oscillator for DCO

fine frequency tuning”, IEEE JSSC, Dec 2010 (in press.)


ALL DIGITAL PLL

Compared to analog PLL, ADPLL occupies less area, is more

reconfigurable and exploits highly scaled digital technology.


ALL DIGITAL PLL IN A GSM TRASNMITTER

Main characteristics:

-  Novel TDC and DCO

-  Two point modulation

-  Gear shifting

-  All Calibration Loops (DCO

and TDC gain, PVT)

Operation in a real scenario:

all voltage regulator and XTAL

buffer included (Prototype under test)


A 1.25mW 75dB SFDR Continuous Time Filter with in-band Noise Reduction

T1.4 – Advanced RF Design

A. Liscidini, A. Pirola, R. Castello



PIPE FILTERS: THE BASIC IDEA

•  The signal is sensed as an output current instead of as a voltage across C

•  The noise integrated in the pass band is 5.6dB below the classic filters

For a given noise target, almost 4 time less capacitance

Wireless Receivers demands High SFDR with in-band low noise and high out-of-band IIP3


4TH ORDER BUTTERWORTH LPF FOR WCDMA

•  Differential Structure

•  4th order as a cascade of two biquads

•  Linear V-I (R1) and I-V (R2) conversion

“Pipe” Filter

90nm CMOS 0.5mm2 ac/ve area


CHIP MICROGRAPH

RELATED PUBLICATIONS: •  A. Liscidini, A. Pirola, R. Castello,” 1.25mW 75dB-SFDR CT Filter with In-Band noise

Reduction” IEEE ISSCC, Feb. 2009. •  A. Pirola, A. Liscidini, R. Castello,“ Current-Mode, WCDMA Channel Filter With In-Band

Noise Shaping”, IEEE JSSC, Sept 2010

This Work

JSSC July 2006

JSSC March 2002

JSSC May 2007

JSSC July 2005

JSSC July 2007

Vdd 2.5 1.2 2.7 1.8 2.5 1.2 Power [mW] 1.26 3.4 6.21 4.86 7.3 1.8

Cut-freq[MHz] 2.8 2.11 1.92 2 2.2 2.75

# Poles 4 4 5 5 3 5 IIP3* [dBm] 35.6 31 41 33 15 24

Input Referred Noise [µVrms]

32 36 57 80 52 116

SFDR [dB] 75 71.25 76.5 68 58.5 59.75 FoM [dB] -174 -165 -168 -161 -148 -159


CALSS AB UP CONVERSION TX PATH

•  Single OA base band:

biquad “pipe” LPF + Class AB Gm stage

•  Mixer:

Linear Class AB Current-Driven Gilbert cell

(Only I path reported for simplicity)


Efficiency Enhancement Techniques for New Generation Cellular Applications

Doherty Power Transmitter Design (CMOS 65nm)

F. Avanzo, M. Vallabhaneni, D. Manstretta



3G and next generation Mobile phones use spectrally efficient modulation schemes: signal has variable amplitude and phase

Signal Amplification with Linear Power Amplifiers


S-H Liao, JSSC Oct 2010 Pulsed Load Modulation

A. M. Niknejad, CICC 2006

o  Signal combining techniques to minimize losses and improve efficiency, especially at reduced power levels.

o  “Non-linear” techniques (e.g. polar, Chireix) :   Limited signal bandwidth   High out-of-band emissions

N. Wongkomet, et al JSSC 2006 CMOS RF Doherty


The integration of a Doherty PA in a CMOS transceiver faces several challenges:

o  Low quality factor of passives •  higher losses, non-linear Doherty operation

o  Low voltage operation •  low output impedance: large chip area, higher losses

o  Process variations •  reduced efficiency, non-linear operation


SiGe –BiCMOS PATH

CMOS PATH

Linear PA

Linear Power Modulator

Linear Doherty TX

Linear Doherty TX

Doherty TX Building Blocks

The integration is forecast within the end of the project

F. Avanzo, F. De Paola, D. Manstretta, , ``A Common-Base Linear RF Power Amplifier for 3G Cellular Applications'',IEEE Custom Integrated Circuits Conference, pp.579-582 , Sept 2008

RELATED PUBLICATIONS


An on-chip LC balun performs differential to single-ended conversion and transformation to 50Ω:

o  Smaller area o  Lower BoM 2 BALUNs back-to-back

65nm CMOS

900µm

800µ

m


The λ/4 line is replaced with an LC π-network and merged with PAs resonant load: o  Smaller area o  Lower losses


  Highly linear up-conversion mixers directly drive the power stages:

o  smaller chip area o  lower power consumption

  The relative amplitude and phase of Main and Aux PAs can be adjusted to compensate for process variations

Main and auxiliary LO signals with variable phase shift


9MHz 10MHz

IM3 tests

Power mixer linearity tests

High efficiency (~40% at P1dB) and linearity (S/D>40dB up to the P1dB)

PA


A ZigBee Complete Transceiver

T1.5 – RF Bodynet and RFID

M. Tedeschi, A. Liscidini, R. Castello



•  Low-IF receiver architecture with complex filter •  Direct VCO modulation transmitter •  Quadrature LMV cell: self-oscillating mixer

ZIG-BEE TRANSCEIVER


QUADRATURE LMV CELL

LNA, Mixers and VCO are merged sharing the

same bias current and the same devices

ZigBee main targets:

•  power savings

•  area savings


RECEIVERS PROTOTYPES PERFOMANCE

[1] Nguyen et al., JSSC 2006 (IEEE 802.15.4)

[2] Kluge et al., JSSC 2006 (IEEE 802.15.4)

[3] Cook et al., JSSC 2006 (proprietary standard)

RELATED PUBLICATIONS: •  A. Liscidini, M. Tedeschi, R. Castello,” A 2.4 GHz 3.6mW 0.35mm2 Quadrature Front-End

RX for ZigBee and WPAN Applications” IEEE ISSCC, Feb 2008, pp.370-371. •  M. Tedeschi, A. Liscidini, R. Castello, “ A 0.23mm2 free coil ZigBee Receiver based on a

bond-wire self-oscillating mixer”, IEEE ESSCIRC, Sept 2008, pp.430-433. •  M. Tedeschi, A. Liscidini, R. Castello,“ Low-Power Quadrature Receivers for ZigBee

(802.15.4) Applications”, IEEE JSSC, vol 45, issue 9, Sept 2010.


TRANSMITTER SECTION (ADPLL)

•  Type I ADPLL has a phase locking with constant phase error and zero frequency error

•  Integrator as digital filter •  coarse tuning:

200MHz - 10MHz steps (5 bits) •  fine tuning:

5MHz - 98kHz steps (8 bits)

•  FDC formed by a 25ps resolution TDC + derivator •  Class-B push pull PA with no integrated coils (60% efficiency delivering 3.6mW of power)

The integration is forecast within the end of the project

research unit 3 - imsims.unipv.it/firb2006/workshop/unit3.pdf · 2010. 11. 12. · cmos path linear...

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