Hindawi Publishing CorporationISRN ElectronicsVolume 2013 Article ID 850267 9 pageshttpdxdoiorg1011552013850267

Research ArticleReversible Logic-Based Fault-Tolerant Nanocircuits in QCA

Bibhash Sen1 Siddhant Ganeriwal1 and Biplab K Sikdar2

1 Department of Computer Science and Engineering National Institute of Technology Durgapur 713209 India2Department of Computer Science and Technology Bengal Engineering and Science University Shibpur 711103 India

Correspondence should be addressed to Bibhash Sen bibhashsengmailcom

Received 28 April 2013 Accepted 26 May 2013

Academic Editors D Rossi and P Wachulak

Copyright copy 2013 Bibhash Sen et al This is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

Parity-preserving reversible circuits are gaining importance for the development of fault-tolerant systems in nanotechnology Onthe other hand Quantum-dot Cellular Automata (QCA) a potential alternative to CMOS promises efficient digital design atnanoscaleThiswork targets design of reversibleALU (arithmetic logic unit) inQCA (Quantum-dotCellularAutomata) frameworkThe design is based on the fault tolerant reversible adders (FTRA) introduced in this paper The proposed fault tolerant adder is aparity-preserving gate and QCA implementation of FTRA achieved 4738 fault-free output in the presence of all possible singlemissingadditional cell defects The proposed designs are verified and evaluated over the existing ALU designs and found to bemore efficient in terms of design complexity and quantum cost

1 Introduction

Reversible logic has attractive perspective of constructingdigital devices that can realize computing unit with almostzero power dissipation Landauer [1] proved that for irre-versible computations each bit of information loss generates1198961198611198791198971198992 joules of heat energy The energy 119864bit required for a

binary transition is given by SNL (Shannon-Von Neumann-Landauer) expression in [1] as follows

119864bit ge 119864SNL = 1198961198611198791198971198992 = 0017 eV (1)

where 119896119861is Boltzmann constant and 119879 = 300K This is the

minimum energy to process a bit Bennett [2] showed that azero power dissipation in logic circuit is possible only if thecircuit is composed of reversible logic gates Since QCA cir-cuits are clocked information preserving systems the energydissipation of QCA circuits can be significantly lower than1198961198611198791198971198992 This feature favours the introduction of QCA tech-

nology in reversible logic designThough reversibility recovers bit loss but it is not able

to detect bit error in circuit Fault-tolerant reversible circuitsare capable of preventing errors at outputs If the system itselfmade of fault-tolerant components then the detection andcorrection of faults become easier and simple In communi-cation and many other systems fault tolerance is achieved by

parity Therefore parity-preserving reversible circuits will bethe future design trends to the development of fault-tolerantreversible systems in nanotechnology

On the other hand QCA (Quantum-dot Cellular Auto-mata) is considered to be promising in the field of nanotech-nology due to their extremely small sizes and ultralow-powerconsumption [3] The QCA is based on encoding binaryinformation in the charge configuration of quantum-dot cellsThe interaction between cells is coulombic and provides thenecessary computing power The fundamental unit of QCA-based design is the 3-input majority gate [3] Majority gatewith inverter called MI is used to realize the QCA designsbecause of its functional incompleteness

Significant contributions have beenmade in the literaturetowards the design of arithmetic units in [4ndash6] Also fault-tolerant full adder circuits are explored in [7ndash10] How-ever there have only been a few efforts towards designingreversible fault-tolerant ALUs

Thismotivates us to design a fault-tolerant reversibleALUarchitecture considering QCA technology A cost-effectiverealization of a fault-tolerant reversible adder (FTRA) is firstintroduced It is then utilized to synthesize the desired fault-tolerant reversible arithmetic logic unit which outperformsthe efficiency of existing designs in terms of design complex-ity and quantum cost The major contributions of this work

2 ISRN Electronics

around reversible QCA architecture can be summarized asfollows

(i) realization of generic fault-tolerant reversible adderhaving parity-preserving logic with cost effectivequantum cost

(ii) the presented fault-tolerant reversible adder block isused to realize different arithmetic circuit such as fulladder subtractor ripple carry adder and carry-skiplogic

(iii) synthesis of a fault-tolerant reversible arithmetic logicunit (ALU) using proposed adder

(iv) application of the proposed adder in QCA nanotech-nology with effective fault tolerance of 4738 in thepresence of all possible single missingadditional celldefects

Simulations using QCADesigner [11] supports all the resultspresented

2 Preliminaries

Reversible Logic A logic gate is reversible if the mapping ofits inputs to outputs is bijective that is every distinct inputyields a distinct output and the number of inputs is equalto the number of outputs [12] An important cost metrics inreversible logic circuits is the quantum costThe cost of every2times 2 gate is the same that is unity and the cost of 1times 1 gate arezero [13] Any reversible logic can be realized using primitivequantum gates like 1 times 1 NOT gates and 2 times 2 reversiblegates such as Controlled-119881 Controlled-119881+ and CNOT gate(Figure 1) The quantum cost of a reversible gate can becalculated by counting the numbers of primitive quantumgates used in implementing it The fan-outs and feedbackpaths are not permitted in reversible logic

QCA Basics A QCA cell consists of four quantum dotspositioned at the corners of a square (Figure 2(a)) andcontains two free electrons [3] The electrons can quantummechanically tunnel among the dots and settle either inpolarization P = minus1 (logic 0) or in P = +1 (logic 1) as shown inFigure 2(b) Timing in QCA is accomplished by the cascadedclocking of four distinct and periodic phases [3] The basicstructure realized with QCA is the 3-input majority gateMV (A B C) = Maj (A B C) = AB + BC + CA (Figure 2(c))It can also function as a 2-input AND (2-input OR) logicby fixing one of the three input cells to P = minus1 (P = +1)Inverter is realized in two different orientations as shown inFigure 2(d) In QCA-based logic implementations two kindsof wire crossover termed coplanar crossover and multilayercrossover are possible Figure 2(e) describes the coplanerwire crossing considering a 90∘ (times-cell) and a 45∘ (+-cell)structures

Fault-Tolerant Logic Fault tolerance enables a system to oper-ate properly in the event of the failure of some its componentsIf the system itself is made up of fault-tolerant componentsthen the detection and correction of faults become easierand simple A fault-tolerant (FT) reversible gate is also called

Table 1 Truth table of proposed fault-tolerant adder

A B C D E P Q R S T0 0 0 0 0 0 0 0 0 00 0 0 0 1 0 0 0 0 10 0 0 1 0 0 0 1 1 10 0 0 1 1 0 0 1 1 00 0 1 0 0 0 0 1 0 00 0 1 0 1 0 0 1 0 10 0 1 1 0 0 0 0 1 10 0 1 1 1 0 0 0 1 00 1 0 0 0 0 1 1 0 10 1 0 0 1 0 1 1 0 00 1 0 1 0 0 1 0 0 10 1 0 1 1 0 1 0 0 00 1 1 0 0 0 1 0 1 00 1 1 0 1 0 1 0 1 10 1 1 1 0 0 1 1 1 00 1 1 1 1 0 1 1 1 11 0 0 0 0 1 0 1 0 01 0 0 0 1 1 0 1 0 11 0 0 1 0 1 0 0 0 01 0 0 1 1 1 0 0 0 11 0 1 0 0 1 0 0 1 11 0 1 0 1 1 0 0 1 01 0 1 1 0 1 0 1 1 11 0 1 1 1 1 0 1 1 01 1 0 0 0 1 1 0 1 01 1 0 0 1 1 1 0 1 11 1 0 1 0 1 1 1 0 11 1 0 1 1 1 1 1 0 01 1 1 0 0 1 1 1 1 01 1 1 0 1 1 1 1 1 11 1 1 1 0 1 1 0 0 11 1 1 1 1 1 1 0 0 0

conservative gate [7] The hamming weight of its inputs andoutputs is equal Let the input and output vectors of any fault-tolerant gate be 119868V = 1198680 1198681 119868119899minus1 and119874V = 1198740 1198741 119874119899minus1where

(i) 119868V⟨Bijective⟩119874V(ii) 1198680oplus 1198681oplus sdot sdot sdot oplus 119868

119899minus1= 1198740oplus 1198741oplus sdot sdot sdot oplus 119874

119899minus1

Few fault-tolerant reversible 3 times 3 gate-like Feynman doublegate (F2G) Fredkin (FRG) NFT and so forth and 4 times 4 gatelike MIG are already investigated

3 Related Work

In [14] the feasibility of the parity-preserving approach todesign of reversible logic circuits was explored Few newfault-tolerant reversible logic gates were proposed in [8]Fault-tolerant full adder circuits are explored in [7ndash10] In allthese researches no such single logic unit was identified toimplement fault-tolerant full adder Also the fault tolerance

ISRN Electronics 3

A oplus A998400

(a)

AA

B A oplusoplus B

(b)

If (A) thenVelse B

V(B)

A

B

A

(c)

If ( ) then V+

V+ (B)

else B

A A

AB

(d)

Figure 1 Elementary quantum logic gates (a) NOT (b) exclusive OR (c) square root of NOT (SRN) and (d) Hermitian matrix of SRN

Quantumtunnel

Junctionwell

Tunnelling potential

(a) Structure of a QCA Cell

Localised electron

= minus1 = +1

Binary ldquo0rdquo binary ldquo1rdquoP P

(b) QCA cell with two dif-ferent polarizations

A

B

C

F

(c) Majority voter

OutputInput

A

A

A998400

A998400

(d) Inverter

ldquo+rdquo cell

AA

B

B

ldquotimesrdquo cell

(e) Wire crossing

Figure 2 QCA basics

capability of those logic gates was not explored quanti-tatively Significant contributions have been made in theliterature towards the design of arithmetic units in [4ndash6]However there have only been a few efforts towards designingreversible fault-tolerant ALUs A new fault-tolerant methodbased on majority multiplexing (Maj-MUX) is proposed forQCA in [15] But the application of reversible logic in QCA toachieve fault tolerance was not identified (which is of primaryinterest to us in this work)

4 Proposed Fault-Tolerant Adder

In communication andmany other systems fault tolerance isachieved by parity A parity-preserving reversible gate whenused with an arbitrary synthesis strategy for reversible logiccircuits allows any fault that affects no more than a singlelogic signal to be detectable at the circuitrsquos primary outputs[14] In [10] a minimum number of garbage outputs andconstant inputs for a fault-tolerant reversible full adder circuitare specified as 3 and 2 Keeping in mind to have min-imum number of garbage outputs and constant inputs anew fault-tolerant reversible adder (FTRA) is proposed here(Figure 3(a)) followed by design of different adder-basedcircuits The input to output mapping of FTRA structure isP = AQ = AoplusB R = AoplusBoplusCoplusD S = (AoplusB)(CoplusD)(ABoplusD)

and T = (A oplus B)(C oplus D)(AB oplus D) oplus E where A B C Dand E are inputs and P Q R S and T are outputs It is a5 times 5 reversible gate with a quantum cost of 8 (Figure 3(b))The proposed reversible FTRA gate is parity preserving Thereversibility and parity preserve nature of the proposed FTRAgate can be verified from Table 1

A fault-tolerant reversible full adder and subtractorcircuit using the newly proposed FTRA gate is shown inFigure 4(a) The design uses only one FTRA gate has aquantum cost of 8 produces 3 garbage outputs and uses 2constant inputs only No such single logic gate is found whichcan implement a fault-tolerant reversible full adder with suchquantum cost and less complexity Design capability of theproposed adder is further analyzed by implementing a 4-bit fault-tolerant ripple carry adder (Figure 4(b)) and carryskip adder (Figure 4(c)) A comparative performance analysisof the proposed design with existing designs is reported inTable 2 with enviable gate count besides other parametersThe results shows that the proposed design is much moreeffective than the existing designs

The advantage of our method is in the implementationof this logic at gate level Thus once the required gates havebeen designed and an appropriate synthesis framework hasbeen established fault-tolerant implementation requires noextra expenditure in design or verification effort

4 ISRN Electronics

FTRA

ABCDE

P = AQ = A oplus BR = A oplus B oplus C oplus DS = (A oplus B)(C oplus D) oplus (AB oplus D)

T = (A oplus B)(C oplus D) oplus (A998400B oplus D) oplus E

(a) Block diagram fault-tolerant adder

A

B

C

DE

P = A

Q = A oplus

oplus

B

R = A oplus B oplus C oplus D

S = (A oplus B)(C oplus D) oplus (AB oplus D)

T = (A oplus B)(C oplus D) oplus

oplus

oplus

oplus

V V V V+

(A998400B oplus D) oplus Eoplus

(b) Quantum implementation of fault-tolerant adder

Figure 3 Proposed fault-tolerant reversible adder

FTRA

Full adder

FTRADiff

Full subtractor

0

0

Sum

AB

C

GG

G0

0

AB

C GG

GCout Bout

(a) Fault-tolerant full adder and subtractor

FTRAFTRAFTRAFTRA00

0 0 0

GG

GG

GG

GG

G

A0

B0

A1B1

A2

B2

A3

B3

S0 S1 S2 S3

CinCout

(b) Fault-tolerant ripple carry adder

FTRA FTRA FTRA FTRA0

0

0

0 0

0

GG

G G G

G

G G

G

G GG G

S0 S1 S2 S3

Cout

00

0 0

FRGF2G FRG

FRGFRG

G

A0

B0

A1B1

A2

B2

A3

B3

Cin

(c) Fault-tolerant carry-skip adder

Figure 4 Implementation of different logic circuit with proposed FTRA

ISRN Electronics 5

FTRA0

GG

Cin

F2G

F2G

0

G

B00

A

FRG

F2GFRG

OutputG

G

F2G

Cout Bout

C0

C2 C2

C1C1C0

Figure 5 Fault-tolerant ALU with proposed FTRA

FTRA

FTRA

FTRA

0

0

00

F2G

F2G

F2G

F2G

F2G

F2G

F2G

F2G

F2G

FRG

FRG

GG

G

G

G

Cout Bout

C0

00

0

0

0

00

A1

B1

GG

G

F2G

F2G

F2G

G

G

G

G

FRG

FRG

FRG

FRG

G

A0

B0

C1C0

C2

GG

Cin

0

Out1

Outn

Out0

C1An

Bn

C2

Figure 6 Implementation of n-bit fault-tolerant ALU

Table 2 Performance analysis of different fault-tolerant full adders

Parameter [7] [8] [9] [10] ProposedGate count 5 6 2 4 1Quantum cost 25 18 14 11 8Garbage outputs 4 6 3 3 3Constant inputs 2 5 2 2 2Logical calculations 8120572 + 16120573 + 8120575 12120572 + 8120573 + 4120575 8120572 + 6120573 + 2120575 9120572 + 4120573 + 3120575 13120572 + 4120573 + 120575

120572 ldquotwo-input EXOR calculationrdquo 120573 ldquotwo-input AND calculationrdquo 120575 ldquoNOT calculationrdquo

6 ISRN Electronics

minus1

minus1

minus1

minus1

minus1 minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

1 2 30

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

A B P

Q

R

S

EC

T

Clocking zone

D

minus1

Figure 7 QCA implementation of fault-tolerant adder

Table 3 Different function of ALU

C0 C1 C2 Output Function0 0 0 AB AND0 0 1 A + B NOR0 1 0 AB NAND0 1 1 A + B OR1 X 0 A oplus B oplus C ADD1 X 1 A oplus B oplus C SUB

41 Design of Fault-TolerantArithmetic LogicUnit (ALU) Thereversible fault-tolerant 1-bit ALU is designed with one FTRAgate two Fredkin gates and four Double-Feynman gatesThus the design uses a total of 7 gates and has a quantumcost of 26 (Figure 5) It produces 5 garbage outputs and uses4 constant inputs The various operations performed by theproposed FTRA-ALU is shown in Table 3 The total logicaloperations performed is 21120572 + 10120573 + 5120575 The main advantageof the proposed ALU logic is its programmable feature thatis just programming the constants C1 C2 and C3 differentALU functions are implemented Besides its fault tolerancethis programmable feature adds more flexibility in reversibleALU Figure 6 shows the design of an n-bit fault-tolerantALUwhich is synthesized by cascading the 1-bit ALUmoduleexplored in Figure 5

5 FTRA Gates in QCA Computing

To demonstrate the application of the proposed fault-tolerantdesign approach to reversible adder in emerging nano-tech-nologies Quantum-dot cellular automata (QCA) technologyis considered because reversible logic has potential applica-tions in QCA computing The QCA implementation of theproposed FTRAgate is shown in Figure 7Thedesign requires27MVs and has a delay of 12 clock zones In the followingsection the fault tolerance capability is established quantita-tively FTRA simulation shown in Figure 8 is performed byfixingD and E to 0 In this simulation result R generates sumand S propagates carry

6 Fault Tolerance of Proposed Logic Gate

In QCAmanufacturing defects can occur during the synthe-sis and deposition phases although defects are most likelyto take place during the deposition phase [16] Researchershave shown that QCA cells are more susceptible to missingand additional QCA cell defects [17] In additional cell defectan additional cell is deposited on the substrate The missingcell defect occurs due to the missing of a particular cellResearchers have been addressing the design and test of QCAcircuits assuming the single missingadditional cell defectmodel

ISRN Electronics 7

AMax

Min

B

C

P

Q

R

S

T

0 0

0

0

000

000

0

00

00

1

10 10 1

0 1

1111

1

1

1

111

0 10 100 11

minus100e + 000

100e + 000

Min minus100e + 000

Max 100e + 000

Min minus100e + 000

Max 100e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Figure 8 Simulation result of fault-tolerant QCA adder

LS5

LS31

CW14

INV26

INV27

MAJ25

LS33

LS32

MAJ26

MAJ27 T

INV7

LS13

MAJ12

INV13

LS10

MAJ9

INV10

INV9

MAJ6

MAJ5

INV5

INV11

MAJ11

LS18

LS17

MAJ13

MAJ14

INV14

LS12

MAJ10

INV6

FO14

LS14LS19

FO16

FO1 INV1

FO2

FO3

FO4

FO10

CW1

FO5

CW2

FO6

CW3

FO7 LS7

MAJ8

LS8INV8

INV12LS11

FO13

FO12

CW7

FO11

FO9

CW4

LS4

LS3

INV3INV2

MAJ1

LS1

LS2

INV4

FO8MAJ2

MAJ3

CW6

MAJ6

MAJ7

LS16

FO15

INV16

LS15

LS9

LS27

CW10

CW9

FO17

CW8

INV17

MAJ16

LS22

LS24

FO18

CW12

FO19

FO20

CW13

LS28 LS29

MAJ22

INV23

LS16

MAJ19

INV21

INV20

INV22

MAJ17

LS25

INV25INV24

MAJ24

MAJ23

LS30

LS21

LS34

LS23

CW11

LS20

FO21

D

A

C

B

MAJ4

CW5

INV15MAJ15

R

S

E

1

INV28

1

PQ

MAJ18

INV19INV18

MAJ20

MAJ21

minus1

minus1

minus1

minus1

minus1

1

minus1

minus1

1

minus1

minus1

minus1

1

minus1minus1

minus1

minus1

1

minus1

minus1

1

minus1

minus1

minus1

minus1

Figure 9 HDLQ modelling of QCA-based fault-tolerant adder

8 ISRN Electronics

Table 4 Fault pattern of proposed fault-tolerant adder

Input Output Fault pattern Success rate FT1 2 3 sdot sdot sdot 43 44 45 sdot sdot sdot 76 77 78

1198860

1198860

11988616119886121198860sdot sdot sdot 119886

211988611198860sdot sdot sdot 119886

1211988611198860

3278 41021198861

1198861

11988617119886131198861sdot sdot sdot 119886

311988601198861sdot sdot sdot 119886

111988601198860

3478 43591198862

1198867

1198862311988681198867sdot sdot sdot 119886

511988661198867sdot sdot sdot 119886

711988661198867

3878 48721198863

1198866

1198862211988681198867sdot sdot sdot 119886

411988671198866sdot sdot sdot 119886

611988661198866

3878 48721198864

1198864

11988620119886111198864sdot sdot sdot 119886

611988651198864sdot sdot sdot 119886

511988641198864

3778 47431198865

1198865

11988621119886101198865sdot sdot sdot 119886

711988641198865sdot sdot sdot 119886

511988651198865

3978 50001198866

1198863

11988619119886151198863sdot sdot sdot 119886

111988621198863sdot sdot sdot 119886

311988621198863

4078 5128

11988630

11988617

119886131198861711988619sdot sdot sdot 119886

191198861611988617sdot sdot sdot 119886

171198861611988617

4178 525611988631

11988616

119886121198861611988618sdot sdot sdot 119886

181198861711988616sdot sdot sdot 119886

161198861611988616

4278 5378Average FT = fault tolerance 4738

In the proposed work the QCA layout of the FTRA gateis converted into the corresponding hardware descriptionlanguage notations using the HDLQ Verilog library [18] TheHDLQ design tool Verilog equivalent for QCA consists of aVerilog HDL library of QCA devices that is MV INV FOCrosswire (CW) and L-shape wire with fault injection capa-bilityThe HDLQ-modeled design of the FTRA gate is shownin Figure 9 and an exhaustive testing of the HDLQ modelof the FTRA gate is conducted with 32 input patterns in thepresence of all possible single missingadditional cell defectsThe design is simulated using the Verilog HDL simulatorin the presence of faults to determine the correspondingoutputs

Testing of the FTRA gate generated 78 unique fault pat-terns at the output as shown in Table 4 Due to huge volumeof data the fault pattern table is partially shown In the faultpatterns study shown in the Table 4 119886

119894is the five-bit pattern

with an equivalent decimal value of 119894 For example 1198860repre-

sents 00000 (decimal 0) and 11988631represents 11111 (decimal 31)

In Table 4 first two columns present the correct behaviour ofFTRAgate that is for a particular input vector correspondingexpected output vector Each row of the Table 4 representsthe output generated after the fault injection of different 78modules of the HDLQ model (Figure 9) for example forgiven input 119886

0 after the fault injection of different modules

the generated fault pattern is 1198860 11988616 11988612 119886

1 1198860 From

those fault patterns we observed that there are average 4738successful patterns that produce the correct output evenwhen there is a fault

7 Conclusions

This work presents a novel architecture of fault-tolerantreversible adder (FTRA) gate Experimental results estab-lish the fact that the proposed FTRA achieved signifi-cant improvements in reversible circuits over the existingones A reversible arithmetic logic unit is synthesized basedon the FTRA proposed This is first attempt to synthesize afault-tolerant full addersubtractor using only single revers-ible logic block (FTRA) with optimal quantum cost toavoid wire-crossing bottleneck Also the application of this

fault-tolerant logic in QCA nanotechnology gets an extraadvantage in fault-tolerant computing with effective 4738fault-free output in the presence of all possible single miss-ingadditional cell defects

Though the clocking structure beneath the QCA celllayer is also very important and nontrivial research issue

Acknowledgment

Theauthors would like to thankMr Samik Some UG studentof CSE department NIT Durgapur for his valuable help intesting the design using HDLQ tool

References

[1] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 5no 3 pp 183ndash191 1961

[2] C H Bennett ldquoLogical reversibility of computationrdquo IBM Jour-nal of Research andDevelopment vol 17 no 6 pp 525ndash532 1973

[3] C S Lent P D Tougaw W Porod and G H BernsteinldquoQuantum cellular automatardquo Nanotechnology vol 4 no 1 pp49ndash57 1993

[4] Z Guan W Li W Ding Y Hang and L Ni ldquoAn arithmeticlogic unit design based on reversible logic gatesrdquo in Proceedingsof the 13th IEEE Pacific Rim Conference on CommunicationsComputers and Signal Processing (PacRim rsquo11) pp 925ndash931August 2011

[5] M Morrison and N Ranganathan ldquoDesign of a reversible ALUbased on novel programmable reversible logic gate structuresrdquoin Proceedings of IEEE Computer Society Annual Symposium onVLSI (ISVLSI rsquo11) pp 126ndash131 Washington DC USA July 2011

[6] Y Syamala andA V N Tilak ldquoReversible arithmetic logic unitrdquoin Proceedings of the 3rd International Conference on ElectronicsComputer Technology (ICECT rsquo11) pp 207ndash211 April 2011

[7] J W Bruce M A Thornton L Shivakumaraiah P S Kokateand X Li ldquoEfficient adder circuits based on a conservativereversible logic gaterdquo in Proceedings of IEEE Symposium onVLSI pp 83ndash88 Washington DC USA 2002

[8] M Haghparast and K Navi ldquoA novel fault tolerant reversiblegate for nanotechnology based systemsrdquo American Journal ofApplied Sciences vol 5 no 5 pp 519ndash523 2008

ISRN Electronics 9

[9] Md S Islam M M Rahman Z Begum and M Z HafizldquoEfficient approaches for designing fault tolerant reversiblecarry look-ahead and carry-skip addersrdquo MASAUM Journal ofBasic and Applied Sciences vol 1 no 3 pp 354ndash360 2009

[10] S K Mitra and A R Chowdhury ldquoMinimum cost fault tolerantadder circuits in reversible logic synthesisrdquo in Proceedings of the25th International Conference on VLSI Design (VLSID rsquo12) pp334ndash339 January 2012

[11] K Walus T J Dysart G A Jullien and R A BudimanldquoQCADesigner a rapid design and simulation tool for quan-tum-dot cellular automatardquo IEEE Transactions on Nanotechnol-ogy vol 3 no 1 pp 26ndash31 2004

[12] T Toffoli ldquoReversible computingrdquo in Proceedings of the 7thColloquium on Automata Languages and Programming pp632ndash644 Springer London UK 1980

[13] M Perkowski M Lukac P Kerntopf et al ldquoA hierarchicalapproach to computer-aided design of quantum circuitsrdquo inProceedings of the 6th International Symposium on Representa-tions andMethodology of Future Computing Technology pp 201ndash209 2003

[14] B Parhami ldquoFault-tolerant reversible circuitsrdquo in Proceedings ofthe 40th Asilomar Conference on Signals Systems and Comput-ers (ACSSC rsquo06) pp 1726ndash1729 November 2006

[15] X Ma and F Lombardi ldquoFault tolerant schemes for QCA sys-temsrdquo in Proceedings of the 23rd IEEE International Symposiumon Defect and Fault Tolerance in VLSI Systems (DFT rsquo08) pp236ndash244 October 2008

[16] M B Tahoori J Huang M Momenzadeh and F LombardildquoTesting of quantum cellular automatardquo IEEE Transactions onNanotechnology vol 3 no 4 pp 432ndash442 2004

[17] M Momenzadeh M Ottavi and F Lombardi ldquoModelingQCA defects at molecular-level in combinational circuitsrdquo inProceedings of the 20th IEEE International Symposium on Defectand Fault Tolerance in VLSI Systems (DFT rsquo05) pp 208ndash216October 2005

[18] M Ottavi L Schiano F Lombardi and D Tougaw ldquoHDLQ aHDL environment for QCA designrdquo Journal on Emerging Tech-nologies in Computing Systems vol 2 no 4 pp 243ndash261 2006

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Shock and Vibration

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Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

2 ISRN Electronics

around reversible QCA architecture can be summarized asfollows

(i) realization of generic fault-tolerant reversible adderhaving parity-preserving logic with cost effectivequantum cost

(ii) the presented fault-tolerant reversible adder block isused to realize different arithmetic circuit such as fulladder subtractor ripple carry adder and carry-skiplogic

(iii) synthesis of a fault-tolerant reversible arithmetic logicunit (ALU) using proposed adder

(iv) application of the proposed adder in QCA nanotech-nology with effective fault tolerance of 4738 in thepresence of all possible single missingadditional celldefects

Simulations using QCADesigner [11] supports all the resultspresented

2 Preliminaries

Reversible Logic A logic gate is reversible if the mapping ofits inputs to outputs is bijective that is every distinct inputyields a distinct output and the number of inputs is equalto the number of outputs [12] An important cost metrics inreversible logic circuits is the quantum costThe cost of every2times 2 gate is the same that is unity and the cost of 1times 1 gate arezero [13] Any reversible logic can be realized using primitivequantum gates like 1 times 1 NOT gates and 2 times 2 reversiblegates such as Controlled-119881 Controlled-119881+ and CNOT gate(Figure 1) The quantum cost of a reversible gate can becalculated by counting the numbers of primitive quantumgates used in implementing it The fan-outs and feedbackpaths are not permitted in reversible logic

QCA Basics A QCA cell consists of four quantum dotspositioned at the corners of a square (Figure 2(a)) andcontains two free electrons [3] The electrons can quantummechanically tunnel among the dots and settle either inpolarization P = minus1 (logic 0) or in P = +1 (logic 1) as shown inFigure 2(b) Timing in QCA is accomplished by the cascadedclocking of four distinct and periodic phases [3] The basicstructure realized with QCA is the 3-input majority gateMV (A B C) = Maj (A B C) = AB + BC + CA (Figure 2(c))It can also function as a 2-input AND (2-input OR) logicby fixing one of the three input cells to P = minus1 (P = +1)Inverter is realized in two different orientations as shown inFigure 2(d) In QCA-based logic implementations two kindsof wire crossover termed coplanar crossover and multilayercrossover are possible Figure 2(e) describes the coplanerwire crossing considering a 90∘ (times-cell) and a 45∘ (+-cell)structures

Fault-Tolerant Logic Fault tolerance enables a system to oper-ate properly in the event of the failure of some its componentsIf the system itself is made up of fault-tolerant componentsthen the detection and correction of faults become easierand simple A fault-tolerant (FT) reversible gate is also called

Table 1 Truth table of proposed fault-tolerant adder

A B C D E P Q R S T0 0 0 0 0 0 0 0 0 00 0 0 0 1 0 0 0 0 10 0 0 1 0 0 0 1 1 10 0 0 1 1 0 0 1 1 00 0 1 0 0 0 0 1 0 00 0 1 0 1 0 0 1 0 10 0 1 1 0 0 0 0 1 10 0 1 1 1 0 0 0 1 00 1 0 0 0 0 1 1 0 10 1 0 0 1 0 1 1 0 00 1 0 1 0 0 1 0 0 10 1 0 1 1 0 1 0 0 00 1 1 0 0 0 1 0 1 00 1 1 0 1 0 1 0 1 10 1 1 1 0 0 1 1 1 00 1 1 1 1 0 1 1 1 11 0 0 0 0 1 0 1 0 01 0 0 0 1 1 0 1 0 11 0 0 1 0 1 0 0 0 01 0 0 1 1 1 0 0 0 11 0 1 0 0 1 0 0 1 11 0 1 0 1 1 0 0 1 01 0 1 1 0 1 0 1 1 11 0 1 1 1 1 0 1 1 01 1 0 0 0 1 1 0 1 01 1 0 0 1 1 1 0 1 11 1 0 1 0 1 1 1 0 11 1 0 1 1 1 1 1 0 01 1 1 0 0 1 1 1 1 01 1 1 0 1 1 1 1 1 11 1 1 1 0 1 1 0 0 11 1 1 1 1 1 1 0 0 0

conservative gate [7] The hamming weight of its inputs andoutputs is equal Let the input and output vectors of any fault-tolerant gate be 119868V = 1198680 1198681 119868119899minus1 and119874V = 1198740 1198741 119874119899minus1where

(i) 119868V⟨Bijective⟩119874V(ii) 1198680oplus 1198681oplus sdot sdot sdot oplus 119868

119899minus1= 1198740oplus 1198741oplus sdot sdot sdot oplus 119874

119899minus1

Few fault-tolerant reversible 3 times 3 gate-like Feynman doublegate (F2G) Fredkin (FRG) NFT and so forth and 4 times 4 gatelike MIG are already investigated

3 Related Work

In [14] the feasibility of the parity-preserving approach todesign of reversible logic circuits was explored Few newfault-tolerant reversible logic gates were proposed in [8]Fault-tolerant full adder circuits are explored in [7ndash10] In allthese researches no such single logic unit was identified toimplement fault-tolerant full adder Also the fault tolerance

ISRN Electronics 3

A oplus A998400

(a)

AA

B A oplusoplus B

(b)

If (A) thenVelse B

V(B)

A

B

A

(c)

If ( ) then V+

V+ (B)

else B

A A

AB

(d)

Figure 1 Elementary quantum logic gates (a) NOT (b) exclusive OR (c) square root of NOT (SRN) and (d) Hermitian matrix of SRN

Quantumtunnel

Junctionwell

Tunnelling potential

(a) Structure of a QCA Cell

Localised electron

= minus1 = +1

Binary ldquo0rdquo binary ldquo1rdquoP P

(b) QCA cell with two dif-ferent polarizations

A

B

C

F

(c) Majority voter

OutputInput

A

A

A998400

A998400

(d) Inverter

ldquo+rdquo cell

AA

B

B

ldquotimesrdquo cell

(e) Wire crossing

Figure 2 QCA basics

capability of those logic gates was not explored quanti-tatively Significant contributions have been made in theliterature towards the design of arithmetic units in [4ndash6]However there have only been a few efforts towards designingreversible fault-tolerant ALUs A new fault-tolerant methodbased on majority multiplexing (Maj-MUX) is proposed forQCA in [15] But the application of reversible logic in QCA toachieve fault tolerance was not identified (which is of primaryinterest to us in this work)

4 Proposed Fault-Tolerant Adder

In communication andmany other systems fault tolerance isachieved by parity A parity-preserving reversible gate whenused with an arbitrary synthesis strategy for reversible logiccircuits allows any fault that affects no more than a singlelogic signal to be detectable at the circuitrsquos primary outputs[14] In [10] a minimum number of garbage outputs andconstant inputs for a fault-tolerant reversible full adder circuitare specified as 3 and 2 Keeping in mind to have min-imum number of garbage outputs and constant inputs anew fault-tolerant reversible adder (FTRA) is proposed here(Figure 3(a)) followed by design of different adder-basedcircuits The input to output mapping of FTRA structure isP = AQ = AoplusB R = AoplusBoplusCoplusD S = (AoplusB)(CoplusD)(ABoplusD)

and T = (A oplus B)(C oplus D)(AB oplus D) oplus E where A B C Dand E are inputs and P Q R S and T are outputs It is a5 times 5 reversible gate with a quantum cost of 8 (Figure 3(b))The proposed reversible FTRA gate is parity preserving Thereversibility and parity preserve nature of the proposed FTRAgate can be verified from Table 1

A fault-tolerant reversible full adder and subtractorcircuit using the newly proposed FTRA gate is shown inFigure 4(a) The design uses only one FTRA gate has aquantum cost of 8 produces 3 garbage outputs and uses 2constant inputs only No such single logic gate is found whichcan implement a fault-tolerant reversible full adder with suchquantum cost and less complexity Design capability of theproposed adder is further analyzed by implementing a 4-bit fault-tolerant ripple carry adder (Figure 4(b)) and carryskip adder (Figure 4(c)) A comparative performance analysisof the proposed design with existing designs is reported inTable 2 with enviable gate count besides other parametersThe results shows that the proposed design is much moreeffective than the existing designs

The advantage of our method is in the implementationof this logic at gate level Thus once the required gates havebeen designed and an appropriate synthesis framework hasbeen established fault-tolerant implementation requires noextra expenditure in design or verification effort

4 ISRN Electronics

FTRA

ABCDE

P = AQ = A oplus BR = A oplus B oplus C oplus DS = (A oplus B)(C oplus D) oplus (AB oplus D)

T = (A oplus B)(C oplus D) oplus (A998400B oplus D) oplus E

(a) Block diagram fault-tolerant adder

A

B

C

DE

P = A

Q = A oplus

oplus

B

R = A oplus B oplus C oplus D

S = (A oplus B)(C oplus D) oplus (AB oplus D)

T = (A oplus B)(C oplus D) oplus

oplus

oplus

oplus

V V V V+

(A998400B oplus D) oplus Eoplus

(b) Quantum implementation of fault-tolerant adder

Figure 3 Proposed fault-tolerant reversible adder

FTRA

Full adder

FTRADiff

Full subtractor

0

0

Sum

AB

C

GG

G0

0

AB

C GG

GCout Bout

(a) Fault-tolerant full adder and subtractor

FTRAFTRAFTRAFTRA00

0 0 0

GG

GG

GG

GG

G

A0

B0

A1B1

A2

B2

A3

B3

S0 S1 S2 S3

CinCout

(b) Fault-tolerant ripple carry adder

FTRA FTRA FTRA FTRA0

0

0

0 0

0

GG

G G G

G

G G

G

G GG G

S0 S1 S2 S3

Cout

00

0 0

FRGF2G FRG

FRGFRG

G

A0

B0

A1B1

A2

B2

A3

B3

Cin

(c) Fault-tolerant carry-skip adder

Figure 4 Implementation of different logic circuit with proposed FTRA

ISRN Electronics 5

FTRA0

GG

Cin

F2G

F2G

0

G

B00

A

FRG

F2GFRG

OutputG

G

F2G

Cout Bout

C0

C2 C2

C1C1C0

Figure 5 Fault-tolerant ALU with proposed FTRA

FTRA

FTRA

FTRA

0

0

00

F2G

F2G

F2G

F2G

F2G

F2G

F2G

F2G

F2G

FRG

FRG

GG

G

G

G

Cout Bout

C0

00

0

0

0

00

A1

B1

GG

G

F2G

F2G

F2G

G

G

G

G

FRG

FRG

FRG

FRG

G

A0

B0

C1C0

C2

GG

Cin

0

Out1

Outn

Out0

C1An

Bn

C2

Figure 6 Implementation of n-bit fault-tolerant ALU

Table 2 Performance analysis of different fault-tolerant full adders

Parameter [7] [8] [9] [10] ProposedGate count 5 6 2 4 1Quantum cost 25 18 14 11 8Garbage outputs 4 6 3 3 3Constant inputs 2 5 2 2 2Logical calculations 8120572 + 16120573 + 8120575 12120572 + 8120573 + 4120575 8120572 + 6120573 + 2120575 9120572 + 4120573 + 3120575 13120572 + 4120573 + 120575

120572 ldquotwo-input EXOR calculationrdquo 120573 ldquotwo-input AND calculationrdquo 120575 ldquoNOT calculationrdquo

6 ISRN Electronics

minus1

minus1

minus1

minus1

minus1 minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

1 2 30

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

A B P

Q

R

S

EC

T

Clocking zone

D

minus1

Figure 7 QCA implementation of fault-tolerant adder

Table 3 Different function of ALU

C0 C1 C2 Output Function0 0 0 AB AND0 0 1 A + B NOR0 1 0 AB NAND0 1 1 A + B OR1 X 0 A oplus B oplus C ADD1 X 1 A oplus B oplus C SUB

41 Design of Fault-TolerantArithmetic LogicUnit (ALU) Thereversible fault-tolerant 1-bit ALU is designed with one FTRAgate two Fredkin gates and four Double-Feynman gatesThus the design uses a total of 7 gates and has a quantumcost of 26 (Figure 5) It produces 5 garbage outputs and uses4 constant inputs The various operations performed by theproposed FTRA-ALU is shown in Table 3 The total logicaloperations performed is 21120572 + 10120573 + 5120575 The main advantageof the proposed ALU logic is its programmable feature thatis just programming the constants C1 C2 and C3 differentALU functions are implemented Besides its fault tolerancethis programmable feature adds more flexibility in reversibleALU Figure 6 shows the design of an n-bit fault-tolerantALUwhich is synthesized by cascading the 1-bit ALUmoduleexplored in Figure 5

5 FTRA Gates in QCA Computing

To demonstrate the application of the proposed fault-tolerantdesign approach to reversible adder in emerging nano-tech-nologies Quantum-dot cellular automata (QCA) technologyis considered because reversible logic has potential applica-tions in QCA computing The QCA implementation of theproposed FTRAgate is shown in Figure 7Thedesign requires27MVs and has a delay of 12 clock zones In the followingsection the fault tolerance capability is established quantita-tively FTRA simulation shown in Figure 8 is performed byfixingD and E to 0 In this simulation result R generates sumand S propagates carry

6 Fault Tolerance of Proposed Logic Gate

In QCAmanufacturing defects can occur during the synthe-sis and deposition phases although defects are most likelyto take place during the deposition phase [16] Researchershave shown that QCA cells are more susceptible to missingand additional QCA cell defects [17] In additional cell defectan additional cell is deposited on the substrate The missingcell defect occurs due to the missing of a particular cellResearchers have been addressing the design and test of QCAcircuits assuming the single missingadditional cell defectmodel

ISRN Electronics 7

AMax

Min

B

C

P

Q

R

S

T

0 0

0

0

000

000

0

00

00

1

10 10 1

0 1

1111

1

1

1

111

0 10 100 11

minus100e + 000

100e + 000

Min minus100e + 000

Max 100e + 000

Min minus100e + 000

Max 100e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Figure 8 Simulation result of fault-tolerant QCA adder

LS5

LS31

CW14

INV26

INV27

MAJ25

LS33

LS32

MAJ26

MAJ27 T

INV7

LS13

MAJ12

INV13

LS10

MAJ9

INV10

INV9

MAJ6

MAJ5

INV5

INV11

MAJ11

LS18

LS17

MAJ13

MAJ14

INV14

LS12

MAJ10

INV6

FO14

LS14LS19

FO16

FO1 INV1

FO2

FO3

FO4

FO10

CW1

FO5

CW2

FO6

CW3

FO7 LS7

MAJ8

LS8INV8

INV12LS11

FO13

FO12

CW7

FO11

FO9

CW4

LS4

LS3

INV3INV2

MAJ1

LS1

LS2

INV4

FO8MAJ2

MAJ3

CW6

MAJ6

MAJ7

LS16

FO15

INV16

LS15

LS9

LS27

CW10

CW9

FO17

CW8

INV17

MAJ16

LS22

LS24

FO18

CW12

FO19

FO20

CW13

LS28 LS29

MAJ22

INV23

LS16

MAJ19

INV21

INV20

INV22

MAJ17

LS25

INV25INV24

MAJ24

MAJ23

LS30

LS21

LS34

LS23

CW11

LS20

FO21

D

A

C

B

MAJ4

CW5

INV15MAJ15

R

S

E

1

INV28

1

PQ

MAJ18

INV19INV18

MAJ20

MAJ21

minus1

minus1

minus1

minus1

minus1

1

minus1

minus1

1

minus1

minus1

minus1

1

minus1minus1

minus1

minus1

1

minus1

minus1

1

minus1

minus1

minus1

minus1

Figure 9 HDLQ modelling of QCA-based fault-tolerant adder

8 ISRN Electronics

Table 4 Fault pattern of proposed fault-tolerant adder

Input Output Fault pattern Success rate FT1 2 3 sdot sdot sdot 43 44 45 sdot sdot sdot 76 77 78

1198860

1198860

11988616119886121198860sdot sdot sdot 119886

211988611198860sdot sdot sdot 119886

1211988611198860

3278 41021198861

1198861

11988617119886131198861sdot sdot sdot 119886

311988601198861sdot sdot sdot 119886

111988601198860

3478 43591198862

1198867

1198862311988681198867sdot sdot sdot 119886

511988661198867sdot sdot sdot 119886

711988661198867

3878 48721198863

1198866

1198862211988681198867sdot sdot sdot 119886

411988671198866sdot sdot sdot 119886

611988661198866

3878 48721198864

1198864

11988620119886111198864sdot sdot sdot 119886

611988651198864sdot sdot sdot 119886

511988641198864

3778 47431198865

1198865

11988621119886101198865sdot sdot sdot 119886

711988641198865sdot sdot sdot 119886

511988651198865

3978 50001198866

1198863

11988619119886151198863sdot sdot sdot 119886

111988621198863sdot sdot sdot 119886

311988621198863

4078 5128

11988630

11988617

119886131198861711988619sdot sdot sdot 119886

191198861611988617sdot sdot sdot 119886

171198861611988617

4178 525611988631

11988616

119886121198861611988618sdot sdot sdot 119886

181198861711988616sdot sdot sdot 119886

161198861611988616

4278 5378Average FT = fault tolerance 4738

In the proposed work the QCA layout of the FTRA gateis converted into the corresponding hardware descriptionlanguage notations using the HDLQ Verilog library [18] TheHDLQ design tool Verilog equivalent for QCA consists of aVerilog HDL library of QCA devices that is MV INV FOCrosswire (CW) and L-shape wire with fault injection capa-bilityThe HDLQ-modeled design of the FTRA gate is shownin Figure 9 and an exhaustive testing of the HDLQ modelof the FTRA gate is conducted with 32 input patterns in thepresence of all possible single missingadditional cell defectsThe design is simulated using the Verilog HDL simulatorin the presence of faults to determine the correspondingoutputs

Testing of the FTRA gate generated 78 unique fault pat-terns at the output as shown in Table 4 Due to huge volumeof data the fault pattern table is partially shown In the faultpatterns study shown in the Table 4 119886

119894is the five-bit pattern

with an equivalent decimal value of 119894 For example 1198860repre-

sents 00000 (decimal 0) and 11988631represents 11111 (decimal 31)

In Table 4 first two columns present the correct behaviour ofFTRAgate that is for a particular input vector correspondingexpected output vector Each row of the Table 4 representsthe output generated after the fault injection of different 78modules of the HDLQ model (Figure 9) for example forgiven input 119886

0 after the fault injection of different modules

the generated fault pattern is 1198860 11988616 11988612 119886

1 1198860 From

those fault patterns we observed that there are average 4738successful patterns that produce the correct output evenwhen there is a fault

7 Conclusions

This work presents a novel architecture of fault-tolerantreversible adder (FTRA) gate Experimental results estab-lish the fact that the proposed FTRA achieved signifi-cant improvements in reversible circuits over the existingones A reversible arithmetic logic unit is synthesized basedon the FTRA proposed This is first attempt to synthesize afault-tolerant full addersubtractor using only single revers-ible logic block (FTRA) with optimal quantum cost toavoid wire-crossing bottleneck Also the application of this

fault-tolerant logic in QCA nanotechnology gets an extraadvantage in fault-tolerant computing with effective 4738fault-free output in the presence of all possible single miss-ingadditional cell defects

Though the clocking structure beneath the QCA celllayer is also very important and nontrivial research issue

Acknowledgment

Theauthors would like to thankMr Samik Some UG studentof CSE department NIT Durgapur for his valuable help intesting the design using HDLQ tool

References

[1] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 5no 3 pp 183ndash191 1961

[2] C H Bennett ldquoLogical reversibility of computationrdquo IBM Jour-nal of Research andDevelopment vol 17 no 6 pp 525ndash532 1973

[3] C S Lent P D Tougaw W Porod and G H BernsteinldquoQuantum cellular automatardquo Nanotechnology vol 4 no 1 pp49ndash57 1993

[4] Z Guan W Li W Ding Y Hang and L Ni ldquoAn arithmeticlogic unit design based on reversible logic gatesrdquo in Proceedingsof the 13th IEEE Pacific Rim Conference on CommunicationsComputers and Signal Processing (PacRim rsquo11) pp 925ndash931August 2011

[5] M Morrison and N Ranganathan ldquoDesign of a reversible ALUbased on novel programmable reversible logic gate structuresrdquoin Proceedings of IEEE Computer Society Annual Symposium onVLSI (ISVLSI rsquo11) pp 126ndash131 Washington DC USA July 2011

[6] Y Syamala andA V N Tilak ldquoReversible arithmetic logic unitrdquoin Proceedings of the 3rd International Conference on ElectronicsComputer Technology (ICECT rsquo11) pp 207ndash211 April 2011

[7] J W Bruce M A Thornton L Shivakumaraiah P S Kokateand X Li ldquoEfficient adder circuits based on a conservativereversible logic gaterdquo in Proceedings of IEEE Symposium onVLSI pp 83ndash88 Washington DC USA 2002

[8] M Haghparast and K Navi ldquoA novel fault tolerant reversiblegate for nanotechnology based systemsrdquo American Journal ofApplied Sciences vol 5 no 5 pp 519ndash523 2008

ISRN Electronics 9

[9] Md S Islam M M Rahman Z Begum and M Z HafizldquoEfficient approaches for designing fault tolerant reversiblecarry look-ahead and carry-skip addersrdquo MASAUM Journal ofBasic and Applied Sciences vol 1 no 3 pp 354ndash360 2009

[10] S K Mitra and A R Chowdhury ldquoMinimum cost fault tolerantadder circuits in reversible logic synthesisrdquo in Proceedings of the25th International Conference on VLSI Design (VLSID rsquo12) pp334ndash339 January 2012

[11] K Walus T J Dysart G A Jullien and R A BudimanldquoQCADesigner a rapid design and simulation tool for quan-tum-dot cellular automatardquo IEEE Transactions on Nanotechnol-ogy vol 3 no 1 pp 26ndash31 2004

[12] T Toffoli ldquoReversible computingrdquo in Proceedings of the 7thColloquium on Automata Languages and Programming pp632ndash644 Springer London UK 1980

[13] M Perkowski M Lukac P Kerntopf et al ldquoA hierarchicalapproach to computer-aided design of quantum circuitsrdquo inProceedings of the 6th International Symposium on Representa-tions andMethodology of Future Computing Technology pp 201ndash209 2003

[14] B Parhami ldquoFault-tolerant reversible circuitsrdquo in Proceedings ofthe 40th Asilomar Conference on Signals Systems and Comput-ers (ACSSC rsquo06) pp 1726ndash1729 November 2006

[15] X Ma and F Lombardi ldquoFault tolerant schemes for QCA sys-temsrdquo in Proceedings of the 23rd IEEE International Symposiumon Defect and Fault Tolerance in VLSI Systems (DFT rsquo08) pp236ndash244 October 2008

[16] M B Tahoori J Huang M Momenzadeh and F LombardildquoTesting of quantum cellular automatardquo IEEE Transactions onNanotechnology vol 3 no 4 pp 432ndash442 2004

[17] M Momenzadeh M Ottavi and F Lombardi ldquoModelingQCA defects at molecular-level in combinational circuitsrdquo inProceedings of the 20th IEEE International Symposium on Defectand Fault Tolerance in VLSI Systems (DFT rsquo05) pp 208ndash216October 2005

[18] M Ottavi L Schiano F Lombardi and D Tougaw ldquoHDLQ aHDL environment for QCA designrdquo Journal on Emerging Tech-nologies in Computing Systems vol 2 no 4 pp 243ndash261 2006

International Journal of

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Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

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Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

ISRN Electronics 3

A oplus A998400

(a)

AA

B A oplusoplus B

(b)

If (A) thenVelse B

V(B)

A

B

A

(c)

If ( ) then V+

V+ (B)

else B

A A

AB

(d)

Figure 1 Elementary quantum logic gates (a) NOT (b) exclusive OR (c) square root of NOT (SRN) and (d) Hermitian matrix of SRN

Quantumtunnel

Junctionwell

Tunnelling potential

(a) Structure of a QCA Cell

Localised electron

= minus1 = +1

Binary ldquo0rdquo binary ldquo1rdquoP P

(b) QCA cell with two dif-ferent polarizations

A

B

C

F

(c) Majority voter

OutputInput

A

A

A998400

A998400

(d) Inverter

ldquo+rdquo cell

AA

B

B

ldquotimesrdquo cell

(e) Wire crossing

Figure 2 QCA basics

capability of those logic gates was not explored quanti-tatively Significant contributions have been made in theliterature towards the design of arithmetic units in [4ndash6]However there have only been a few efforts towards designingreversible fault-tolerant ALUs A new fault-tolerant methodbased on majority multiplexing (Maj-MUX) is proposed forQCA in [15] But the application of reversible logic in QCA toachieve fault tolerance was not identified (which is of primaryinterest to us in this work)

4 Proposed Fault-Tolerant Adder

In communication andmany other systems fault tolerance isachieved by parity A parity-preserving reversible gate whenused with an arbitrary synthesis strategy for reversible logiccircuits allows any fault that affects no more than a singlelogic signal to be detectable at the circuitrsquos primary outputs[14] In [10] a minimum number of garbage outputs andconstant inputs for a fault-tolerant reversible full adder circuitare specified as 3 and 2 Keeping in mind to have min-imum number of garbage outputs and constant inputs anew fault-tolerant reversible adder (FTRA) is proposed here(Figure 3(a)) followed by design of different adder-basedcircuits The input to output mapping of FTRA structure isP = AQ = AoplusB R = AoplusBoplusCoplusD S = (AoplusB)(CoplusD)(ABoplusD)

and T = (A oplus B)(C oplus D)(AB oplus D) oplus E where A B C Dand E are inputs and P Q R S and T are outputs It is a5 times 5 reversible gate with a quantum cost of 8 (Figure 3(b))The proposed reversible FTRA gate is parity preserving Thereversibility and parity preserve nature of the proposed FTRAgate can be verified from Table 1

A fault-tolerant reversible full adder and subtractorcircuit using the newly proposed FTRA gate is shown inFigure 4(a) The design uses only one FTRA gate has aquantum cost of 8 produces 3 garbage outputs and uses 2constant inputs only No such single logic gate is found whichcan implement a fault-tolerant reversible full adder with suchquantum cost and less complexity Design capability of theproposed adder is further analyzed by implementing a 4-bit fault-tolerant ripple carry adder (Figure 4(b)) and carryskip adder (Figure 4(c)) A comparative performance analysisof the proposed design with existing designs is reported inTable 2 with enviable gate count besides other parametersThe results shows that the proposed design is much moreeffective than the existing designs

The advantage of our method is in the implementationof this logic at gate level Thus once the required gates havebeen designed and an appropriate synthesis framework hasbeen established fault-tolerant implementation requires noextra expenditure in design or verification effort

4 ISRN Electronics

FTRA

ABCDE

P = AQ = A oplus BR = A oplus B oplus C oplus DS = (A oplus B)(C oplus D) oplus (AB oplus D)

T = (A oplus B)(C oplus D) oplus (A998400B oplus D) oplus E

(a) Block diagram fault-tolerant adder

A

B

C

DE

P = A

Q = A oplus

oplus

B

R = A oplus B oplus C oplus D

S = (A oplus B)(C oplus D) oplus (AB oplus D)

T = (A oplus B)(C oplus D) oplus

oplus

oplus

oplus

V V V V+

(A998400B oplus D) oplus Eoplus

(b) Quantum implementation of fault-tolerant adder

Figure 3 Proposed fault-tolerant reversible adder

FTRA

Full adder

FTRADiff

Full subtractor

0

0

Sum

AB

C

GG

G0

0

AB

C GG

GCout Bout

(a) Fault-tolerant full adder and subtractor

FTRAFTRAFTRAFTRA00

0 0 0

GG

GG

GG

GG

G

A0

B0

A1B1

A2

B2

A3

B3

S0 S1 S2 S3

CinCout

(b) Fault-tolerant ripple carry adder

FTRA FTRA FTRA FTRA0

0

0

0 0

0

GG

G G G

G

G G

G

G GG G

S0 S1 S2 S3

Cout

00

0 0

FRGF2G FRG

FRGFRG

G

A0

B0

A1B1

A2

B2

A3

B3

Cin

(c) Fault-tolerant carry-skip adder

Figure 4 Implementation of different logic circuit with proposed FTRA

ISRN Electronics 5

FTRA0

GG

Cin

F2G

F2G

0

G

B00

A

FRG

F2GFRG

OutputG

G

F2G

Cout Bout

C0

C2 C2

C1C1C0

Figure 5 Fault-tolerant ALU with proposed FTRA

FTRA

FTRA

FTRA

0

0

00

F2G

F2G

F2G

F2G

F2G

F2G

F2G

F2G

F2G

FRG

FRG

GG

G

G

G

Cout Bout

C0

00

0

0

0

00

A1

B1

GG

G

F2G

F2G

F2G

G

G

G

G

FRG

FRG

FRG

FRG

G

A0

B0

C1C0

C2

GG

Cin

0

Out1

Outn

Out0

C1An

Bn

C2

Figure 6 Implementation of n-bit fault-tolerant ALU

Table 2 Performance analysis of different fault-tolerant full adders

Parameter [7] [8] [9] [10] ProposedGate count 5 6 2 4 1Quantum cost 25 18 14 11 8Garbage outputs 4 6 3 3 3Constant inputs 2 5 2 2 2Logical calculations 8120572 + 16120573 + 8120575 12120572 + 8120573 + 4120575 8120572 + 6120573 + 2120575 9120572 + 4120573 + 3120575 13120572 + 4120573 + 120575

120572 ldquotwo-input EXOR calculationrdquo 120573 ldquotwo-input AND calculationrdquo 120575 ldquoNOT calculationrdquo

6 ISRN Electronics

minus1

minus1

minus1

minus1

minus1 minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

1 2 30

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

A B P

Q

R

S

EC

T

Clocking zone

D

minus1

Figure 7 QCA implementation of fault-tolerant adder

Table 3 Different function of ALU

C0 C1 C2 Output Function0 0 0 AB AND0 0 1 A + B NOR0 1 0 AB NAND0 1 1 A + B OR1 X 0 A oplus B oplus C ADD1 X 1 A oplus B oplus C SUB

41 Design of Fault-TolerantArithmetic LogicUnit (ALU) Thereversible fault-tolerant 1-bit ALU is designed with one FTRAgate two Fredkin gates and four Double-Feynman gatesThus the design uses a total of 7 gates and has a quantumcost of 26 (Figure 5) It produces 5 garbage outputs and uses4 constant inputs The various operations performed by theproposed FTRA-ALU is shown in Table 3 The total logicaloperations performed is 21120572 + 10120573 + 5120575 The main advantageof the proposed ALU logic is its programmable feature thatis just programming the constants C1 C2 and C3 differentALU functions are implemented Besides its fault tolerancethis programmable feature adds more flexibility in reversibleALU Figure 6 shows the design of an n-bit fault-tolerantALUwhich is synthesized by cascading the 1-bit ALUmoduleexplored in Figure 5

5 FTRA Gates in QCA Computing

To demonstrate the application of the proposed fault-tolerantdesign approach to reversible adder in emerging nano-tech-nologies Quantum-dot cellular automata (QCA) technologyis considered because reversible logic has potential applica-tions in QCA computing The QCA implementation of theproposed FTRAgate is shown in Figure 7Thedesign requires27MVs and has a delay of 12 clock zones In the followingsection the fault tolerance capability is established quantita-tively FTRA simulation shown in Figure 8 is performed byfixingD and E to 0 In this simulation result R generates sumand S propagates carry

6 Fault Tolerance of Proposed Logic Gate

In QCAmanufacturing defects can occur during the synthe-sis and deposition phases although defects are most likelyto take place during the deposition phase [16] Researchershave shown that QCA cells are more susceptible to missingand additional QCA cell defects [17] In additional cell defectan additional cell is deposited on the substrate The missingcell defect occurs due to the missing of a particular cellResearchers have been addressing the design and test of QCAcircuits assuming the single missingadditional cell defectmodel

ISRN Electronics 7

AMax

Min

B

C

P

Q

R

S

T

0 0

0

0

000

000

0

00

00

1

10 10 1

0 1

1111

1

1

1

111

0 10 100 11

minus100e + 000

100e + 000

Min minus100e + 000

Max 100e + 000

Min minus100e + 000

Max 100e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Figure 8 Simulation result of fault-tolerant QCA adder

LS5

LS31

CW14

INV26

INV27

MAJ25

LS33

LS32

MAJ26

MAJ27 T

INV7

LS13

MAJ12

INV13

LS10

MAJ9

INV10

INV9

MAJ6

MAJ5

INV5

INV11

MAJ11

LS18

LS17

MAJ13

MAJ14

INV14

LS12

MAJ10

INV6

FO14

LS14LS19

FO16

FO1 INV1

FO2

FO3

FO4

FO10

CW1

FO5

CW2

FO6

CW3

FO7 LS7

MAJ8

LS8INV8

INV12LS11

FO13

FO12

CW7

FO11

FO9

CW4

LS4

LS3

INV3INV2

MAJ1

LS1

LS2

INV4

FO8MAJ2

MAJ3

CW6

MAJ6

MAJ7

LS16

FO15

INV16

LS15

LS9

LS27

CW10

CW9

FO17

CW8

INV17

MAJ16

LS22

LS24

FO18

CW12

FO19

FO20

CW13

LS28 LS29

MAJ22

INV23

LS16

MAJ19

INV21

INV20

INV22

MAJ17

LS25

INV25INV24

MAJ24

MAJ23

LS30

LS21

LS34

LS23

CW11

LS20

FO21

D

A

C

B

MAJ4

CW5

INV15MAJ15

R

S

E

1

INV28

1

PQ

MAJ18

INV19INV18

MAJ20

MAJ21

minus1

minus1

minus1

minus1

minus1

1

minus1

minus1

1

minus1

minus1

minus1

1

minus1minus1

minus1

minus1

1

minus1

minus1

1

minus1

minus1

minus1

minus1

Figure 9 HDLQ modelling of QCA-based fault-tolerant adder

8 ISRN Electronics

Table 4 Fault pattern of proposed fault-tolerant adder

Input Output Fault pattern Success rate FT1 2 3 sdot sdot sdot 43 44 45 sdot sdot sdot 76 77 78

1198860

1198860

11988616119886121198860sdot sdot sdot 119886

211988611198860sdot sdot sdot 119886

1211988611198860

3278 41021198861

1198861

11988617119886131198861sdot sdot sdot 119886

311988601198861sdot sdot sdot 119886

111988601198860

3478 43591198862

1198867

1198862311988681198867sdot sdot sdot 119886

511988661198867sdot sdot sdot 119886

711988661198867

3878 48721198863

1198866

1198862211988681198867sdot sdot sdot 119886

411988671198866sdot sdot sdot 119886

611988661198866

3878 48721198864

1198864

11988620119886111198864sdot sdot sdot 119886

611988651198864sdot sdot sdot 119886

511988641198864

3778 47431198865

1198865

11988621119886101198865sdot sdot sdot 119886

711988641198865sdot sdot sdot 119886

511988651198865

3978 50001198866

1198863

11988619119886151198863sdot sdot sdot 119886

111988621198863sdot sdot sdot 119886

311988621198863

4078 5128

11988630

11988617

119886131198861711988619sdot sdot sdot 119886

191198861611988617sdot sdot sdot 119886

171198861611988617

4178 525611988631

11988616

119886121198861611988618sdot sdot sdot 119886

181198861711988616sdot sdot sdot 119886

161198861611988616

4278 5378Average FT = fault tolerance 4738

In the proposed work the QCA layout of the FTRA gateis converted into the corresponding hardware descriptionlanguage notations using the HDLQ Verilog library [18] TheHDLQ design tool Verilog equivalent for QCA consists of aVerilog HDL library of QCA devices that is MV INV FOCrosswire (CW) and L-shape wire with fault injection capa-bilityThe HDLQ-modeled design of the FTRA gate is shownin Figure 9 and an exhaustive testing of the HDLQ modelof the FTRA gate is conducted with 32 input patterns in thepresence of all possible single missingadditional cell defectsThe design is simulated using the Verilog HDL simulatorin the presence of faults to determine the correspondingoutputs

Testing of the FTRA gate generated 78 unique fault pat-terns at the output as shown in Table 4 Due to huge volumeof data the fault pattern table is partially shown In the faultpatterns study shown in the Table 4 119886

119894is the five-bit pattern

with an equivalent decimal value of 119894 For example 1198860repre-

sents 00000 (decimal 0) and 11988631represents 11111 (decimal 31)

In Table 4 first two columns present the correct behaviour ofFTRAgate that is for a particular input vector correspondingexpected output vector Each row of the Table 4 representsthe output generated after the fault injection of different 78modules of the HDLQ model (Figure 9) for example forgiven input 119886

0 after the fault injection of different modules

the generated fault pattern is 1198860 11988616 11988612 119886

1 1198860 From

those fault patterns we observed that there are average 4738successful patterns that produce the correct output evenwhen there is a fault

7 Conclusions

This work presents a novel architecture of fault-tolerantreversible adder (FTRA) gate Experimental results estab-lish the fact that the proposed FTRA achieved signifi-cant improvements in reversible circuits over the existingones A reversible arithmetic logic unit is synthesized basedon the FTRA proposed This is first attempt to synthesize afault-tolerant full addersubtractor using only single revers-ible logic block (FTRA) with optimal quantum cost toavoid wire-crossing bottleneck Also the application of this

fault-tolerant logic in QCA nanotechnology gets an extraadvantage in fault-tolerant computing with effective 4738fault-free output in the presence of all possible single miss-ingadditional cell defects

Though the clocking structure beneath the QCA celllayer is also very important and nontrivial research issue

Acknowledgment

Theauthors would like to thankMr Samik Some UG studentof CSE department NIT Durgapur for his valuable help intesting the design using HDLQ tool

References

[1] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 5no 3 pp 183ndash191 1961

[2] C H Bennett ldquoLogical reversibility of computationrdquo IBM Jour-nal of Research andDevelopment vol 17 no 6 pp 525ndash532 1973

[3] C S Lent P D Tougaw W Porod and G H BernsteinldquoQuantum cellular automatardquo Nanotechnology vol 4 no 1 pp49ndash57 1993

[4] Z Guan W Li W Ding Y Hang and L Ni ldquoAn arithmeticlogic unit design based on reversible logic gatesrdquo in Proceedingsof the 13th IEEE Pacific Rim Conference on CommunicationsComputers and Signal Processing (PacRim rsquo11) pp 925ndash931August 2011

[5] M Morrison and N Ranganathan ldquoDesign of a reversible ALUbased on novel programmable reversible logic gate structuresrdquoin Proceedings of IEEE Computer Society Annual Symposium onVLSI (ISVLSI rsquo11) pp 126ndash131 Washington DC USA July 2011

[6] Y Syamala andA V N Tilak ldquoReversible arithmetic logic unitrdquoin Proceedings of the 3rd International Conference on ElectronicsComputer Technology (ICECT rsquo11) pp 207ndash211 April 2011

[7] J W Bruce M A Thornton L Shivakumaraiah P S Kokateand X Li ldquoEfficient adder circuits based on a conservativereversible logic gaterdquo in Proceedings of IEEE Symposium onVLSI pp 83ndash88 Washington DC USA 2002

[8] M Haghparast and K Navi ldquoA novel fault tolerant reversiblegate for nanotechnology based systemsrdquo American Journal ofApplied Sciences vol 5 no 5 pp 519ndash523 2008

ISRN Electronics 9

[9] Md S Islam M M Rahman Z Begum and M Z HafizldquoEfficient approaches for designing fault tolerant reversiblecarry look-ahead and carry-skip addersrdquo MASAUM Journal ofBasic and Applied Sciences vol 1 no 3 pp 354ndash360 2009

[10] S K Mitra and A R Chowdhury ldquoMinimum cost fault tolerantadder circuits in reversible logic synthesisrdquo in Proceedings of the25th International Conference on VLSI Design (VLSID rsquo12) pp334ndash339 January 2012

[11] K Walus T J Dysart G A Jullien and R A BudimanldquoQCADesigner a rapid design and simulation tool for quan-tum-dot cellular automatardquo IEEE Transactions on Nanotechnol-ogy vol 3 no 1 pp 26ndash31 2004

[12] T Toffoli ldquoReversible computingrdquo in Proceedings of the 7thColloquium on Automata Languages and Programming pp632ndash644 Springer London UK 1980

[13] M Perkowski M Lukac P Kerntopf et al ldquoA hierarchicalapproach to computer-aided design of quantum circuitsrdquo inProceedings of the 6th International Symposium on Representa-tions andMethodology of Future Computing Technology pp 201ndash209 2003

[14] B Parhami ldquoFault-tolerant reversible circuitsrdquo in Proceedings ofthe 40th Asilomar Conference on Signals Systems and Comput-ers (ACSSC rsquo06) pp 1726ndash1729 November 2006

[15] X Ma and F Lombardi ldquoFault tolerant schemes for QCA sys-temsrdquo in Proceedings of the 23rd IEEE International Symposiumon Defect and Fault Tolerance in VLSI Systems (DFT rsquo08) pp236ndash244 October 2008

[16] M B Tahoori J Huang M Momenzadeh and F LombardildquoTesting of quantum cellular automatardquo IEEE Transactions onNanotechnology vol 3 no 4 pp 432ndash442 2004

[17] M Momenzadeh M Ottavi and F Lombardi ldquoModelingQCA defects at molecular-level in combinational circuitsrdquo inProceedings of the 20th IEEE International Symposium on Defectand Fault Tolerance in VLSI Systems (DFT rsquo05) pp 208ndash216October 2005

[18] M Ottavi L Schiano F Lombardi and D Tougaw ldquoHDLQ aHDL environment for QCA designrdquo Journal on Emerging Tech-nologies in Computing Systems vol 2 no 4 pp 243ndash261 2006

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International Journal of

4 ISRN Electronics

FTRA

ABCDE

P = AQ = A oplus BR = A oplus B oplus C oplus DS = (A oplus B)(C oplus D) oplus (AB oplus D)

T = (A oplus B)(C oplus D) oplus (A998400B oplus D) oplus E

(a) Block diagram fault-tolerant adder

A

B

C

DE

P = A

Q = A oplus

oplus

B

R = A oplus B oplus C oplus D

S = (A oplus B)(C oplus D) oplus (AB oplus D)

T = (A oplus B)(C oplus D) oplus

oplus

oplus

oplus

V V V V+

(A998400B oplus D) oplus Eoplus

(b) Quantum implementation of fault-tolerant adder

Figure 3 Proposed fault-tolerant reversible adder

FTRA

Full adder

FTRADiff

Full subtractor

0

0

Sum

AB

C

GG

G0

0

AB

C GG

GCout Bout

(a) Fault-tolerant full adder and subtractor

FTRAFTRAFTRAFTRA00

0 0 0

GG

GG

GG

GG

G

A0

B0

A1B1

A2

B2

A3

B3

S0 S1 S2 S3

CinCout

(b) Fault-tolerant ripple carry adder

FTRA FTRA FTRA FTRA0

0

0

0 0

0

GG

G G G

G

G G

G

G GG G

S0 S1 S2 S3

Cout

00

0 0

FRGF2G FRG

FRGFRG

G

A0

B0

A1B1

A2

B2

A3

B3

Cin

(c) Fault-tolerant carry-skip adder

Figure 4 Implementation of different logic circuit with proposed FTRA

ISRN Electronics 5

FTRA0

GG

Cin

F2G

F2G

0

G

B00

A

FRG

F2GFRG

OutputG

G

F2G

Cout Bout

C0

C2 C2

C1C1C0

Figure 5 Fault-tolerant ALU with proposed FTRA

FTRA

FTRA

FTRA

0

0

00

F2G

F2G

F2G

F2G

F2G

F2G

F2G

F2G

F2G

FRG

FRG

GG

G

G

G

Cout Bout

C0

00

0

0

0

00

A1

B1

GG

G

F2G

F2G

F2G

G

G

G

G

FRG

FRG

FRG

FRG

G

A0

B0

C1C0

C2

GG

Cin

0

Out1

Outn

Out0

C1An

Bn

C2

Figure 6 Implementation of n-bit fault-tolerant ALU

Table 2 Performance analysis of different fault-tolerant full adders

Parameter [7] [8] [9] [10] ProposedGate count 5 6 2 4 1Quantum cost 25 18 14 11 8Garbage outputs 4 6 3 3 3Constant inputs 2 5 2 2 2Logical calculations 8120572 + 16120573 + 8120575 12120572 + 8120573 + 4120575 8120572 + 6120573 + 2120575 9120572 + 4120573 + 3120575 13120572 + 4120573 + 120575

120572 ldquotwo-input EXOR calculationrdquo 120573 ldquotwo-input AND calculationrdquo 120575 ldquoNOT calculationrdquo

6 ISRN Electronics

minus1

minus1

minus1

minus1

minus1 minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

1 2 30

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

A B P

Q

R

S

EC

T

Clocking zone

D

minus1

Figure 7 QCA implementation of fault-tolerant adder

Table 3 Different function of ALU

C0 C1 C2 Output Function0 0 0 AB AND0 0 1 A + B NOR0 1 0 AB NAND0 1 1 A + B OR1 X 0 A oplus B oplus C ADD1 X 1 A oplus B oplus C SUB

41 Design of Fault-TolerantArithmetic LogicUnit (ALU) Thereversible fault-tolerant 1-bit ALU is designed with one FTRAgate two Fredkin gates and four Double-Feynman gatesThus the design uses a total of 7 gates and has a quantumcost of 26 (Figure 5) It produces 5 garbage outputs and uses4 constant inputs The various operations performed by theproposed FTRA-ALU is shown in Table 3 The total logicaloperations performed is 21120572 + 10120573 + 5120575 The main advantageof the proposed ALU logic is its programmable feature thatis just programming the constants C1 C2 and C3 differentALU functions are implemented Besides its fault tolerancethis programmable feature adds more flexibility in reversibleALU Figure 6 shows the design of an n-bit fault-tolerantALUwhich is synthesized by cascading the 1-bit ALUmoduleexplored in Figure 5

5 FTRA Gates in QCA Computing

To demonstrate the application of the proposed fault-tolerantdesign approach to reversible adder in emerging nano-tech-nologies Quantum-dot cellular automata (QCA) technologyis considered because reversible logic has potential applica-tions in QCA computing The QCA implementation of theproposed FTRAgate is shown in Figure 7Thedesign requires27MVs and has a delay of 12 clock zones In the followingsection the fault tolerance capability is established quantita-tively FTRA simulation shown in Figure 8 is performed byfixingD and E to 0 In this simulation result R generates sumand S propagates carry

6 Fault Tolerance of Proposed Logic Gate

In QCAmanufacturing defects can occur during the synthe-sis and deposition phases although defects are most likelyto take place during the deposition phase [16] Researchershave shown that QCA cells are more susceptible to missingand additional QCA cell defects [17] In additional cell defectan additional cell is deposited on the substrate The missingcell defect occurs due to the missing of a particular cellResearchers have been addressing the design and test of QCAcircuits assuming the single missingadditional cell defectmodel

ISRN Electronics 7

AMax

Min

B

C

P

Q

R

S

T

0 0

0

0

000

000

0

00

00

1

10 10 1

0 1

1111

1

1

1

111

0 10 100 11

minus100e + 000

100e + 000

Min minus100e + 000

Max 100e + 000

Min minus100e + 000

Max 100e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Figure 8 Simulation result of fault-tolerant QCA adder

LS5

LS31

CW14

INV26

INV27

MAJ25

LS33

LS32

MAJ26

MAJ27 T

INV7

LS13

MAJ12

INV13

LS10

MAJ9

INV10

INV9

MAJ6

MAJ5

INV5

INV11

MAJ11

LS18

LS17

MAJ13

MAJ14

INV14

LS12

MAJ10

INV6

FO14

LS14LS19

FO16

FO1 INV1

FO2

FO3

FO4

FO10

CW1

FO5

CW2

FO6

CW3

FO7 LS7

MAJ8

LS8INV8

INV12LS11

FO13

FO12

CW7

FO11

FO9

CW4

LS4

LS3

INV3INV2

MAJ1

LS1

LS2

INV4

FO8MAJ2

MAJ3

CW6

MAJ6

MAJ7

LS16

FO15

INV16

LS15

LS9

LS27

CW10

CW9

FO17

CW8

INV17

MAJ16

LS22

LS24

FO18

CW12

FO19

FO20

CW13

LS28 LS29

MAJ22

INV23

LS16

MAJ19

INV21

INV20

INV22

MAJ17

LS25

INV25INV24

MAJ24

MAJ23

LS30

LS21

LS34

LS23

CW11

LS20

FO21

D

A

C

B

MAJ4

CW5

INV15MAJ15

R

S

E

1

INV28

1

PQ

MAJ18

INV19INV18

MAJ20

MAJ21

minus1

minus1

minus1

minus1

minus1

1

minus1

minus1

1

minus1

minus1

minus1

1

minus1minus1

minus1

minus1

1

minus1

minus1

1

minus1

minus1

minus1

minus1

Figure 9 HDLQ modelling of QCA-based fault-tolerant adder

8 ISRN Electronics

Table 4 Fault pattern of proposed fault-tolerant adder

Input Output Fault pattern Success rate FT1 2 3 sdot sdot sdot 43 44 45 sdot sdot sdot 76 77 78

1198860

1198860

11988616119886121198860sdot sdot sdot 119886

211988611198860sdot sdot sdot 119886

1211988611198860

3278 41021198861

1198861

11988617119886131198861sdot sdot sdot 119886

311988601198861sdot sdot sdot 119886

111988601198860

3478 43591198862

1198867

1198862311988681198867sdot sdot sdot 119886

511988661198867sdot sdot sdot 119886

711988661198867

3878 48721198863

1198866

1198862211988681198867sdot sdot sdot 119886

411988671198866sdot sdot sdot 119886

611988661198866

3878 48721198864

1198864

11988620119886111198864sdot sdot sdot 119886

611988651198864sdot sdot sdot 119886

511988641198864

3778 47431198865

1198865

11988621119886101198865sdot sdot sdot 119886

711988641198865sdot sdot sdot 119886

511988651198865

3978 50001198866

1198863

11988619119886151198863sdot sdot sdot 119886

111988621198863sdot sdot sdot 119886

311988621198863

4078 5128

11988630

11988617

119886131198861711988619sdot sdot sdot 119886

191198861611988617sdot sdot sdot 119886

171198861611988617

4178 525611988631

11988616

119886121198861611988618sdot sdot sdot 119886

181198861711988616sdot sdot sdot 119886

161198861611988616

4278 5378Average FT = fault tolerance 4738

In the proposed work the QCA layout of the FTRA gateis converted into the corresponding hardware descriptionlanguage notations using the HDLQ Verilog library [18] TheHDLQ design tool Verilog equivalent for QCA consists of aVerilog HDL library of QCA devices that is MV INV FOCrosswire (CW) and L-shape wire with fault injection capa-bilityThe HDLQ-modeled design of the FTRA gate is shownin Figure 9 and an exhaustive testing of the HDLQ modelof the FTRA gate is conducted with 32 input patterns in thepresence of all possible single missingadditional cell defectsThe design is simulated using the Verilog HDL simulatorin the presence of faults to determine the correspondingoutputs

Testing of the FTRA gate generated 78 unique fault pat-terns at the output as shown in Table 4 Due to huge volumeof data the fault pattern table is partially shown In the faultpatterns study shown in the Table 4 119886

119894is the five-bit pattern

with an equivalent decimal value of 119894 For example 1198860repre-

sents 00000 (decimal 0) and 11988631represents 11111 (decimal 31)

In Table 4 first two columns present the correct behaviour ofFTRAgate that is for a particular input vector correspondingexpected output vector Each row of the Table 4 representsthe output generated after the fault injection of different 78modules of the HDLQ model (Figure 9) for example forgiven input 119886

0 after the fault injection of different modules

the generated fault pattern is 1198860 11988616 11988612 119886

1 1198860 From

those fault patterns we observed that there are average 4738successful patterns that produce the correct output evenwhen there is a fault

7 Conclusions

This work presents a novel architecture of fault-tolerantreversible adder (FTRA) gate Experimental results estab-lish the fact that the proposed FTRA achieved signifi-cant improvements in reversible circuits over the existingones A reversible arithmetic logic unit is synthesized basedon the FTRA proposed This is first attempt to synthesize afault-tolerant full addersubtractor using only single revers-ible logic block (FTRA) with optimal quantum cost toavoid wire-crossing bottleneck Also the application of this

fault-tolerant logic in QCA nanotechnology gets an extraadvantage in fault-tolerant computing with effective 4738fault-free output in the presence of all possible single miss-ingadditional cell defects

Though the clocking structure beneath the QCA celllayer is also very important and nontrivial research issue

Acknowledgment

Theauthors would like to thankMr Samik Some UG studentof CSE department NIT Durgapur for his valuable help intesting the design using HDLQ tool

References

[1] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 5no 3 pp 183ndash191 1961

[2] C H Bennett ldquoLogical reversibility of computationrdquo IBM Jour-nal of Research andDevelopment vol 17 no 6 pp 525ndash532 1973

[3] C S Lent P D Tougaw W Porod and G H BernsteinldquoQuantum cellular automatardquo Nanotechnology vol 4 no 1 pp49ndash57 1993

[4] Z Guan W Li W Ding Y Hang and L Ni ldquoAn arithmeticlogic unit design based on reversible logic gatesrdquo in Proceedingsof the 13th IEEE Pacific Rim Conference on CommunicationsComputers and Signal Processing (PacRim rsquo11) pp 925ndash931August 2011

[5] M Morrison and N Ranganathan ldquoDesign of a reversible ALUbased on novel programmable reversible logic gate structuresrdquoin Proceedings of IEEE Computer Society Annual Symposium onVLSI (ISVLSI rsquo11) pp 126ndash131 Washington DC USA July 2011

[6] Y Syamala andA V N Tilak ldquoReversible arithmetic logic unitrdquoin Proceedings of the 3rd International Conference on ElectronicsComputer Technology (ICECT rsquo11) pp 207ndash211 April 2011

[7] J W Bruce M A Thornton L Shivakumaraiah P S Kokateand X Li ldquoEfficient adder circuits based on a conservativereversible logic gaterdquo in Proceedings of IEEE Symposium onVLSI pp 83ndash88 Washington DC USA 2002

[8] M Haghparast and K Navi ldquoA novel fault tolerant reversiblegate for nanotechnology based systemsrdquo American Journal ofApplied Sciences vol 5 no 5 pp 519ndash523 2008

ISRN Electronics 9

[9] Md S Islam M M Rahman Z Begum and M Z HafizldquoEfficient approaches for designing fault tolerant reversiblecarry look-ahead and carry-skip addersrdquo MASAUM Journal ofBasic and Applied Sciences vol 1 no 3 pp 354ndash360 2009

[10] S K Mitra and A R Chowdhury ldquoMinimum cost fault tolerantadder circuits in reversible logic synthesisrdquo in Proceedings of the25th International Conference on VLSI Design (VLSID rsquo12) pp334ndash339 January 2012

[11] K Walus T J Dysart G A Jullien and R A BudimanldquoQCADesigner a rapid design and simulation tool for quan-tum-dot cellular automatardquo IEEE Transactions on Nanotechnol-ogy vol 3 no 1 pp 26ndash31 2004

[12] T Toffoli ldquoReversible computingrdquo in Proceedings of the 7thColloquium on Automata Languages and Programming pp632ndash644 Springer London UK 1980

[13] M Perkowski M Lukac P Kerntopf et al ldquoA hierarchicalapproach to computer-aided design of quantum circuitsrdquo inProceedings of the 6th International Symposium on Representa-tions andMethodology of Future Computing Technology pp 201ndash209 2003

[14] B Parhami ldquoFault-tolerant reversible circuitsrdquo in Proceedings ofthe 40th Asilomar Conference on Signals Systems and Comput-ers (ACSSC rsquo06) pp 1726ndash1729 November 2006

[15] X Ma and F Lombardi ldquoFault tolerant schemes for QCA sys-temsrdquo in Proceedings of the 23rd IEEE International Symposiumon Defect and Fault Tolerance in VLSI Systems (DFT rsquo08) pp236ndash244 October 2008

[16] M B Tahoori J Huang M Momenzadeh and F LombardildquoTesting of quantum cellular automatardquo IEEE Transactions onNanotechnology vol 3 no 4 pp 432ndash442 2004

[17] M Momenzadeh M Ottavi and F Lombardi ldquoModelingQCA defects at molecular-level in combinational circuitsrdquo inProceedings of the 20th IEEE International Symposium on Defectand Fault Tolerance in VLSI Systems (DFT rsquo05) pp 208ndash216October 2005

[18] M Ottavi L Schiano F Lombardi and D Tougaw ldquoHDLQ aHDL environment for QCA designrdquo Journal on Emerging Tech-nologies in Computing Systems vol 2 no 4 pp 243ndash261 2006

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

ISRN Electronics 5

FTRA0

GG

Cin

F2G

F2G

0

G

B00

A

FRG

F2GFRG

OutputG

G

F2G

Cout Bout

C0

C2 C2

C1C1C0

Figure 5 Fault-tolerant ALU with proposed FTRA

FTRA

FTRA

FTRA

0

0

00

F2G

F2G

F2G

F2G

F2G

F2G

F2G

F2G

F2G

FRG

FRG

GG

G

G

G

Cout Bout

C0

00

0

0

0

00

A1

B1

GG

G

F2G

F2G

F2G

G

G

G

G

FRG

FRG

FRG

FRG

G

A0

B0

C1C0

C2

GG

Cin

0

Out1

Outn

Out0

C1An

Bn

C2

Figure 6 Implementation of n-bit fault-tolerant ALU

Table 2 Performance analysis of different fault-tolerant full adders

Parameter [7] [8] [9] [10] ProposedGate count 5 6 2 4 1Quantum cost 25 18 14 11 8Garbage outputs 4 6 3 3 3Constant inputs 2 5 2 2 2Logical calculations 8120572 + 16120573 + 8120575 12120572 + 8120573 + 4120575 8120572 + 6120573 + 2120575 9120572 + 4120573 + 3120575 13120572 + 4120573 + 120575

120572 ldquotwo-input EXOR calculationrdquo 120573 ldquotwo-input AND calculationrdquo 120575 ldquoNOT calculationrdquo

6 ISRN Electronics

minus1

minus1

minus1

minus1

minus1 minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

1 2 30

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

A B P

Q

R

S

EC

T

Clocking zone

D

minus1

Figure 7 QCA implementation of fault-tolerant adder

Table 3 Different function of ALU

C0 C1 C2 Output Function0 0 0 AB AND0 0 1 A + B NOR0 1 0 AB NAND0 1 1 A + B OR1 X 0 A oplus B oplus C ADD1 X 1 A oplus B oplus C SUB

41 Design of Fault-TolerantArithmetic LogicUnit (ALU) Thereversible fault-tolerant 1-bit ALU is designed with one FTRAgate two Fredkin gates and four Double-Feynman gatesThus the design uses a total of 7 gates and has a quantumcost of 26 (Figure 5) It produces 5 garbage outputs and uses4 constant inputs The various operations performed by theproposed FTRA-ALU is shown in Table 3 The total logicaloperations performed is 21120572 + 10120573 + 5120575 The main advantageof the proposed ALU logic is its programmable feature thatis just programming the constants C1 C2 and C3 differentALU functions are implemented Besides its fault tolerancethis programmable feature adds more flexibility in reversibleALU Figure 6 shows the design of an n-bit fault-tolerantALUwhich is synthesized by cascading the 1-bit ALUmoduleexplored in Figure 5

5 FTRA Gates in QCA Computing

To demonstrate the application of the proposed fault-tolerantdesign approach to reversible adder in emerging nano-tech-nologies Quantum-dot cellular automata (QCA) technologyis considered because reversible logic has potential applica-tions in QCA computing The QCA implementation of theproposed FTRAgate is shown in Figure 7Thedesign requires27MVs and has a delay of 12 clock zones In the followingsection the fault tolerance capability is established quantita-tively FTRA simulation shown in Figure 8 is performed byfixingD and E to 0 In this simulation result R generates sumand S propagates carry

6 Fault Tolerance of Proposed Logic Gate

In QCAmanufacturing defects can occur during the synthe-sis and deposition phases although defects are most likelyto take place during the deposition phase [16] Researchershave shown that QCA cells are more susceptible to missingand additional QCA cell defects [17] In additional cell defectan additional cell is deposited on the substrate The missingcell defect occurs due to the missing of a particular cellResearchers have been addressing the design and test of QCAcircuits assuming the single missingadditional cell defectmodel

ISRN Electronics 7

AMax

Min

B

C

P

Q

R

S

T

0 0

0

0

000

000

0

00

00

1

10 10 1

0 1

1111

1

1

1

111

0 10 100 11

minus100e + 000

100e + 000

Min minus100e + 000

Max 100e + 000

Min minus100e + 000

Max 100e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Figure 8 Simulation result of fault-tolerant QCA adder

LS5

LS31

CW14

INV26

INV27

MAJ25

LS33

LS32

MAJ26

MAJ27 T

INV7

LS13

MAJ12

INV13

LS10

MAJ9

INV10

INV9

MAJ6

MAJ5

INV5

INV11

MAJ11

LS18

LS17

MAJ13

MAJ14

INV14

LS12

MAJ10

INV6

FO14

LS14LS19

FO16

FO1 INV1

FO2

FO3

FO4

FO10

CW1

FO5

CW2

FO6

CW3

FO7 LS7

MAJ8

LS8INV8

INV12LS11

FO13

FO12

CW7

FO11

FO9

CW4

LS4

LS3

INV3INV2

MAJ1

LS1

LS2

INV4

FO8MAJ2

MAJ3

CW6

MAJ6

MAJ7

LS16

FO15

INV16

LS15

LS9

LS27

CW10

CW9

FO17

CW8

INV17

MAJ16

LS22

LS24

FO18

CW12

FO19

FO20

CW13

LS28 LS29

MAJ22

INV23

LS16

MAJ19

INV21

INV20

INV22

MAJ17

LS25

INV25INV24

MAJ24

MAJ23

LS30

LS21

LS34

LS23

CW11

LS20

FO21

D

A

C

B

MAJ4

CW5

INV15MAJ15

R

S

E

1

INV28

1

PQ

MAJ18

INV19INV18

MAJ20

MAJ21

minus1

minus1

minus1

minus1

minus1

1

minus1

minus1

1

minus1

minus1

minus1

1

minus1minus1

minus1

minus1

1

minus1

minus1

1

minus1

minus1

minus1

minus1

Figure 9 HDLQ modelling of QCA-based fault-tolerant adder

8 ISRN Electronics

Table 4 Fault pattern of proposed fault-tolerant adder

Input Output Fault pattern Success rate FT1 2 3 sdot sdot sdot 43 44 45 sdot sdot sdot 76 77 78

1198860

1198860

11988616119886121198860sdot sdot sdot 119886

211988611198860sdot sdot sdot 119886

1211988611198860

3278 41021198861

1198861

11988617119886131198861sdot sdot sdot 119886

311988601198861sdot sdot sdot 119886

111988601198860

3478 43591198862

1198867

1198862311988681198867sdot sdot sdot 119886

511988661198867sdot sdot sdot 119886

711988661198867

3878 48721198863

1198866

1198862211988681198867sdot sdot sdot 119886

411988671198866sdot sdot sdot 119886

611988661198866

3878 48721198864

1198864

11988620119886111198864sdot sdot sdot 119886

611988651198864sdot sdot sdot 119886

511988641198864

3778 47431198865

1198865

11988621119886101198865sdot sdot sdot 119886

711988641198865sdot sdot sdot 119886

511988651198865

3978 50001198866

1198863

11988619119886151198863sdot sdot sdot 119886

111988621198863sdot sdot sdot 119886

311988621198863

4078 5128

11988630

11988617

119886131198861711988619sdot sdot sdot 119886

191198861611988617sdot sdot sdot 119886

171198861611988617

4178 525611988631

11988616

119886121198861611988618sdot sdot sdot 119886

181198861711988616sdot sdot sdot 119886

161198861611988616

4278 5378Average FT = fault tolerance 4738

In the proposed work the QCA layout of the FTRA gateis converted into the corresponding hardware descriptionlanguage notations using the HDLQ Verilog library [18] TheHDLQ design tool Verilog equivalent for QCA consists of aVerilog HDL library of QCA devices that is MV INV FOCrosswire (CW) and L-shape wire with fault injection capa-bilityThe HDLQ-modeled design of the FTRA gate is shownin Figure 9 and an exhaustive testing of the HDLQ modelof the FTRA gate is conducted with 32 input patterns in thepresence of all possible single missingadditional cell defectsThe design is simulated using the Verilog HDL simulatorin the presence of faults to determine the correspondingoutputs

Testing of the FTRA gate generated 78 unique fault pat-terns at the output as shown in Table 4 Due to huge volumeof data the fault pattern table is partially shown In the faultpatterns study shown in the Table 4 119886

119894is the five-bit pattern

with an equivalent decimal value of 119894 For example 1198860repre-

sents 00000 (decimal 0) and 11988631represents 11111 (decimal 31)

In Table 4 first two columns present the correct behaviour ofFTRAgate that is for a particular input vector correspondingexpected output vector Each row of the Table 4 representsthe output generated after the fault injection of different 78modules of the HDLQ model (Figure 9) for example forgiven input 119886

0 after the fault injection of different modules

the generated fault pattern is 1198860 11988616 11988612 119886

1 1198860 From

those fault patterns we observed that there are average 4738successful patterns that produce the correct output evenwhen there is a fault

7 Conclusions

This work presents a novel architecture of fault-tolerantreversible adder (FTRA) gate Experimental results estab-lish the fact that the proposed FTRA achieved signifi-cant improvements in reversible circuits over the existingones A reversible arithmetic logic unit is synthesized basedon the FTRA proposed This is first attempt to synthesize afault-tolerant full addersubtractor using only single revers-ible logic block (FTRA) with optimal quantum cost toavoid wire-crossing bottleneck Also the application of this

fault-tolerant logic in QCA nanotechnology gets an extraadvantage in fault-tolerant computing with effective 4738fault-free output in the presence of all possible single miss-ingadditional cell defects

Though the clocking structure beneath the QCA celllayer is also very important and nontrivial research issue

Acknowledgment

Theauthors would like to thankMr Samik Some UG studentof CSE department NIT Durgapur for his valuable help intesting the design using HDLQ tool

References

[1] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 5no 3 pp 183ndash191 1961

[2] C H Bennett ldquoLogical reversibility of computationrdquo IBM Jour-nal of Research andDevelopment vol 17 no 6 pp 525ndash532 1973

[3] C S Lent P D Tougaw W Porod and G H BernsteinldquoQuantum cellular automatardquo Nanotechnology vol 4 no 1 pp49ndash57 1993

[4] Z Guan W Li W Ding Y Hang and L Ni ldquoAn arithmeticlogic unit design based on reversible logic gatesrdquo in Proceedingsof the 13th IEEE Pacific Rim Conference on CommunicationsComputers and Signal Processing (PacRim rsquo11) pp 925ndash931August 2011

[5] M Morrison and N Ranganathan ldquoDesign of a reversible ALUbased on novel programmable reversible logic gate structuresrdquoin Proceedings of IEEE Computer Society Annual Symposium onVLSI (ISVLSI rsquo11) pp 126ndash131 Washington DC USA July 2011

[6] Y Syamala andA V N Tilak ldquoReversible arithmetic logic unitrdquoin Proceedings of the 3rd International Conference on ElectronicsComputer Technology (ICECT rsquo11) pp 207ndash211 April 2011

[7] J W Bruce M A Thornton L Shivakumaraiah P S Kokateand X Li ldquoEfficient adder circuits based on a conservativereversible logic gaterdquo in Proceedings of IEEE Symposium onVLSI pp 83ndash88 Washington DC USA 2002

[8] M Haghparast and K Navi ldquoA novel fault tolerant reversiblegate for nanotechnology based systemsrdquo American Journal ofApplied Sciences vol 5 no 5 pp 519ndash523 2008

ISRN Electronics 9

[9] Md S Islam M M Rahman Z Begum and M Z HafizldquoEfficient approaches for designing fault tolerant reversiblecarry look-ahead and carry-skip addersrdquo MASAUM Journal ofBasic and Applied Sciences vol 1 no 3 pp 354ndash360 2009

[10] S K Mitra and A R Chowdhury ldquoMinimum cost fault tolerantadder circuits in reversible logic synthesisrdquo in Proceedings of the25th International Conference on VLSI Design (VLSID rsquo12) pp334ndash339 January 2012

[11] K Walus T J Dysart G A Jullien and R A BudimanldquoQCADesigner a rapid design and simulation tool for quan-tum-dot cellular automatardquo IEEE Transactions on Nanotechnol-ogy vol 3 no 1 pp 26ndash31 2004

[12] T Toffoli ldquoReversible computingrdquo in Proceedings of the 7thColloquium on Automata Languages and Programming pp632ndash644 Springer London UK 1980

[13] M Perkowski M Lukac P Kerntopf et al ldquoA hierarchicalapproach to computer-aided design of quantum circuitsrdquo inProceedings of the 6th International Symposium on Representa-tions andMethodology of Future Computing Technology pp 201ndash209 2003

[14] B Parhami ldquoFault-tolerant reversible circuitsrdquo in Proceedings ofthe 40th Asilomar Conference on Signals Systems and Comput-ers (ACSSC rsquo06) pp 1726ndash1729 November 2006

[15] X Ma and F Lombardi ldquoFault tolerant schemes for QCA sys-temsrdquo in Proceedings of the 23rd IEEE International Symposiumon Defect and Fault Tolerance in VLSI Systems (DFT rsquo08) pp236ndash244 October 2008

[16] M B Tahoori J Huang M Momenzadeh and F LombardildquoTesting of quantum cellular automatardquo IEEE Transactions onNanotechnology vol 3 no 4 pp 432ndash442 2004

[17] M Momenzadeh M Ottavi and F Lombardi ldquoModelingQCA defects at molecular-level in combinational circuitsrdquo inProceedings of the 20th IEEE International Symposium on Defectand Fault Tolerance in VLSI Systems (DFT rsquo05) pp 208ndash216October 2005

[18] M Ottavi L Schiano F Lombardi and D Tougaw ldquoHDLQ aHDL environment for QCA designrdquo Journal on Emerging Tech-nologies in Computing Systems vol 2 no 4 pp 243ndash261 2006

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

6 ISRN Electronics

minus1

minus1

minus1

minus1

minus1 minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

1 2 30

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

minus1

A B P

Q

R

S

EC

T

Clocking zone

D

minus1

Figure 7 QCA implementation of fault-tolerant adder

Table 3 Different function of ALU

C0 C1 C2 Output Function0 0 0 AB AND0 0 1 A + B NOR0 1 0 AB NAND0 1 1 A + B OR1 X 0 A oplus B oplus C ADD1 X 1 A oplus B oplus C SUB

41 Design of Fault-TolerantArithmetic LogicUnit (ALU) Thereversible fault-tolerant 1-bit ALU is designed with one FTRAgate two Fredkin gates and four Double-Feynman gatesThus the design uses a total of 7 gates and has a quantumcost of 26 (Figure 5) It produces 5 garbage outputs and uses4 constant inputs The various operations performed by theproposed FTRA-ALU is shown in Table 3 The total logicaloperations performed is 21120572 + 10120573 + 5120575 The main advantageof the proposed ALU logic is its programmable feature thatis just programming the constants C1 C2 and C3 differentALU functions are implemented Besides its fault tolerancethis programmable feature adds more flexibility in reversibleALU Figure 6 shows the design of an n-bit fault-tolerantALUwhich is synthesized by cascading the 1-bit ALUmoduleexplored in Figure 5

5 FTRA Gates in QCA Computing

To demonstrate the application of the proposed fault-tolerantdesign approach to reversible adder in emerging nano-tech-nologies Quantum-dot cellular automata (QCA) technologyis considered because reversible logic has potential applica-tions in QCA computing The QCA implementation of theproposed FTRAgate is shown in Figure 7Thedesign requires27MVs and has a delay of 12 clock zones In the followingsection the fault tolerance capability is established quantita-tively FTRA simulation shown in Figure 8 is performed byfixingD and E to 0 In this simulation result R generates sumand S propagates carry

6 Fault Tolerance of Proposed Logic Gate

In QCAmanufacturing defects can occur during the synthe-sis and deposition phases although defects are most likelyto take place during the deposition phase [16] Researchershave shown that QCA cells are more susceptible to missingand additional QCA cell defects [17] In additional cell defectan additional cell is deposited on the substrate The missingcell defect occurs due to the missing of a particular cellResearchers have been addressing the design and test of QCAcircuits assuming the single missingadditional cell defectmodel

ISRN Electronics 7

AMax

Min

B

C

P

Q

R

S

T

0 0

0

0

000

000

0

00

00

1

10 10 1

0 1

1111

1

1

1

111

0 10 100 11

minus100e + 000

100e + 000

Min minus100e + 000

Max 100e + 000

Min minus100e + 000

Max 100e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Figure 8 Simulation result of fault-tolerant QCA adder

LS5

LS31

CW14

INV26

INV27

MAJ25

LS33

LS32

MAJ26

MAJ27 T

INV7

LS13

MAJ12

INV13

LS10

MAJ9

INV10

INV9

MAJ6

MAJ5

INV5

INV11

MAJ11

LS18

LS17

MAJ13

MAJ14

INV14

LS12

MAJ10

INV6

FO14

LS14LS19

FO16

FO1 INV1

FO2

FO3

FO4

FO10

CW1

FO5

CW2

FO6

CW3

FO7 LS7

MAJ8

LS8INV8

INV12LS11

FO13

FO12

CW7

FO11

FO9

CW4

LS4

LS3

INV3INV2

MAJ1

LS1

LS2

INV4

FO8MAJ2

MAJ3

CW6

MAJ6

MAJ7

LS16

FO15

INV16

LS15

LS9

LS27

CW10

CW9

FO17

CW8

INV17

MAJ16

LS22

LS24

FO18

CW12

FO19

FO20

CW13

LS28 LS29

MAJ22

INV23

LS16

MAJ19

INV21

INV20

INV22

MAJ17

LS25

INV25INV24

MAJ24

MAJ23

LS30

LS21

LS34

LS23

CW11

LS20

FO21

D

A

C

B

MAJ4

CW5

INV15MAJ15

R

S

E

1

INV28

1

PQ

MAJ18

INV19INV18

MAJ20

MAJ21

minus1

minus1

minus1

minus1

minus1

1

minus1

minus1

1

minus1

minus1

minus1

1

minus1minus1

minus1

minus1

1

minus1

minus1

1

minus1

minus1

minus1

minus1

Figure 9 HDLQ modelling of QCA-based fault-tolerant adder

8 ISRN Electronics

Table 4 Fault pattern of proposed fault-tolerant adder

Input Output Fault pattern Success rate FT1 2 3 sdot sdot sdot 43 44 45 sdot sdot sdot 76 77 78

1198860

1198860

11988616119886121198860sdot sdot sdot 119886

211988611198860sdot sdot sdot 119886

1211988611198860

3278 41021198861

1198861

11988617119886131198861sdot sdot sdot 119886

311988601198861sdot sdot sdot 119886

111988601198860

3478 43591198862

1198867

1198862311988681198867sdot sdot sdot 119886

511988661198867sdot sdot sdot 119886

711988661198867

3878 48721198863

1198866

1198862211988681198867sdot sdot sdot 119886

411988671198866sdot sdot sdot 119886

611988661198866

3878 48721198864

1198864

11988620119886111198864sdot sdot sdot 119886

611988651198864sdot sdot sdot 119886

511988641198864

3778 47431198865

1198865

11988621119886101198865sdot sdot sdot 119886

711988641198865sdot sdot sdot 119886

511988651198865

3978 50001198866

1198863

11988619119886151198863sdot sdot sdot 119886

111988621198863sdot sdot sdot 119886

311988621198863

4078 5128

11988630

11988617

119886131198861711988619sdot sdot sdot 119886

191198861611988617sdot sdot sdot 119886

171198861611988617

4178 525611988631

11988616

119886121198861611988618sdot sdot sdot 119886

181198861711988616sdot sdot sdot 119886

161198861611988616

4278 5378Average FT = fault tolerance 4738

In the proposed work the QCA layout of the FTRA gateis converted into the corresponding hardware descriptionlanguage notations using the HDLQ Verilog library [18] TheHDLQ design tool Verilog equivalent for QCA consists of aVerilog HDL library of QCA devices that is MV INV FOCrosswire (CW) and L-shape wire with fault injection capa-bilityThe HDLQ-modeled design of the FTRA gate is shownin Figure 9 and an exhaustive testing of the HDLQ modelof the FTRA gate is conducted with 32 input patterns in thepresence of all possible single missingadditional cell defectsThe design is simulated using the Verilog HDL simulatorin the presence of faults to determine the correspondingoutputs

Testing of the FTRA gate generated 78 unique fault pat-terns at the output as shown in Table 4 Due to huge volumeof data the fault pattern table is partially shown In the faultpatterns study shown in the Table 4 119886

119894is the five-bit pattern

with an equivalent decimal value of 119894 For example 1198860repre-

sents 00000 (decimal 0) and 11988631represents 11111 (decimal 31)

In Table 4 first two columns present the correct behaviour ofFTRAgate that is for a particular input vector correspondingexpected output vector Each row of the Table 4 representsthe output generated after the fault injection of different 78modules of the HDLQ model (Figure 9) for example forgiven input 119886

0 after the fault injection of different modules

the generated fault pattern is 1198860 11988616 11988612 119886

1 1198860 From

those fault patterns we observed that there are average 4738successful patterns that produce the correct output evenwhen there is a fault

7 Conclusions

This work presents a novel architecture of fault-tolerantreversible adder (FTRA) gate Experimental results estab-lish the fact that the proposed FTRA achieved signifi-cant improvements in reversible circuits over the existingones A reversible arithmetic logic unit is synthesized basedon the FTRA proposed This is first attempt to synthesize afault-tolerant full addersubtractor using only single revers-ible logic block (FTRA) with optimal quantum cost toavoid wire-crossing bottleneck Also the application of this

fault-tolerant logic in QCA nanotechnology gets an extraadvantage in fault-tolerant computing with effective 4738fault-free output in the presence of all possible single miss-ingadditional cell defects

Though the clocking structure beneath the QCA celllayer is also very important and nontrivial research issue

Acknowledgment

Theauthors would like to thankMr Samik Some UG studentof CSE department NIT Durgapur for his valuable help intesting the design using HDLQ tool

References

[1] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 5no 3 pp 183ndash191 1961

[2] C H Bennett ldquoLogical reversibility of computationrdquo IBM Jour-nal of Research andDevelopment vol 17 no 6 pp 525ndash532 1973

[3] C S Lent P D Tougaw W Porod and G H BernsteinldquoQuantum cellular automatardquo Nanotechnology vol 4 no 1 pp49ndash57 1993

[4] Z Guan W Li W Ding Y Hang and L Ni ldquoAn arithmeticlogic unit design based on reversible logic gatesrdquo in Proceedingsof the 13th IEEE Pacific Rim Conference on CommunicationsComputers and Signal Processing (PacRim rsquo11) pp 925ndash931August 2011

[5] M Morrison and N Ranganathan ldquoDesign of a reversible ALUbased on novel programmable reversible logic gate structuresrdquoin Proceedings of IEEE Computer Society Annual Symposium onVLSI (ISVLSI rsquo11) pp 126ndash131 Washington DC USA July 2011

[6] Y Syamala andA V N Tilak ldquoReversible arithmetic logic unitrdquoin Proceedings of the 3rd International Conference on ElectronicsComputer Technology (ICECT rsquo11) pp 207ndash211 April 2011

[7] J W Bruce M A Thornton L Shivakumaraiah P S Kokateand X Li ldquoEfficient adder circuits based on a conservativereversible logic gaterdquo in Proceedings of IEEE Symposium onVLSI pp 83ndash88 Washington DC USA 2002

[8] M Haghparast and K Navi ldquoA novel fault tolerant reversiblegate for nanotechnology based systemsrdquo American Journal ofApplied Sciences vol 5 no 5 pp 519ndash523 2008

ISRN Electronics 9

[9] Md S Islam M M Rahman Z Begum and M Z HafizldquoEfficient approaches for designing fault tolerant reversiblecarry look-ahead and carry-skip addersrdquo MASAUM Journal ofBasic and Applied Sciences vol 1 no 3 pp 354ndash360 2009

[10] S K Mitra and A R Chowdhury ldquoMinimum cost fault tolerantadder circuits in reversible logic synthesisrdquo in Proceedings of the25th International Conference on VLSI Design (VLSID rsquo12) pp334ndash339 January 2012

[11] K Walus T J Dysart G A Jullien and R A BudimanldquoQCADesigner a rapid design and simulation tool for quan-tum-dot cellular automatardquo IEEE Transactions on Nanotechnol-ogy vol 3 no 1 pp 26ndash31 2004

[12] T Toffoli ldquoReversible computingrdquo in Proceedings of the 7thColloquium on Automata Languages and Programming pp632ndash644 Springer London UK 1980

[13] M Perkowski M Lukac P Kerntopf et al ldquoA hierarchicalapproach to computer-aided design of quantum circuitsrdquo inProceedings of the 6th International Symposium on Representa-tions andMethodology of Future Computing Technology pp 201ndash209 2003

[14] B Parhami ldquoFault-tolerant reversible circuitsrdquo in Proceedings ofthe 40th Asilomar Conference on Signals Systems and Comput-ers (ACSSC rsquo06) pp 1726ndash1729 November 2006

[15] X Ma and F Lombardi ldquoFault tolerant schemes for QCA sys-temsrdquo in Proceedings of the 23rd IEEE International Symposiumon Defect and Fault Tolerance in VLSI Systems (DFT rsquo08) pp236ndash244 October 2008

[16] M B Tahoori J Huang M Momenzadeh and F LombardildquoTesting of quantum cellular automatardquo IEEE Transactions onNanotechnology vol 3 no 4 pp 432ndash442 2004

[17] M Momenzadeh M Ottavi and F Lombardi ldquoModelingQCA defects at molecular-level in combinational circuitsrdquo inProceedings of the 20th IEEE International Symposium on Defectand Fault Tolerance in VLSI Systems (DFT rsquo05) pp 208ndash216October 2005

[18] M Ottavi L Schiano F Lombardi and D Tougaw ldquoHDLQ aHDL environment for QCA designrdquo Journal on Emerging Tech-nologies in Computing Systems vol 2 no 4 pp 243ndash261 2006

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

ISRN Electronics 7

AMax

Min

B

C

P

Q

R

S

T

0 0

0

0

000

000

0

00

00

1

10 10 1

0 1

1111

1

1

1

111

0 10 100 11

minus100e + 000

100e + 000

Min minus100e + 000

Max 100e + 000

Min minus100e + 000

Max 100e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Max 954e + 000

Min minus954e + 000

Figure 8 Simulation result of fault-tolerant QCA adder

LS5

LS31

CW14

INV26

INV27

MAJ25

LS33

LS32

MAJ26

MAJ27 T

INV7

LS13

MAJ12

INV13

LS10

MAJ9

INV10

INV9

MAJ6

MAJ5

INV5

INV11

MAJ11

LS18

LS17

MAJ13

MAJ14

INV14

LS12

MAJ10

INV6

FO14

LS14LS19

FO16

FO1 INV1

FO2

FO3

FO4

FO10

CW1

FO5

CW2

FO6

CW3

FO7 LS7

MAJ8

LS8INV8

INV12LS11

FO13

FO12

CW7

FO11

FO9

CW4

LS4

LS3

INV3INV2

MAJ1

LS1

LS2

INV4

FO8MAJ2

MAJ3

CW6

MAJ6

MAJ7

LS16

FO15

INV16

LS15

LS9

LS27

CW10

CW9

FO17

CW8

INV17

MAJ16

LS22

LS24

FO18

CW12

FO19

FO20

CW13

LS28 LS29

MAJ22

INV23

LS16

MAJ19

INV21

INV20

INV22

MAJ17

LS25

INV25INV24

MAJ24

MAJ23

LS30

LS21

LS34

LS23

CW11

LS20

FO21

D

A

C

B

MAJ4

CW5

INV15MAJ15

R

S

E

1

INV28

1

PQ

MAJ18

INV19INV18

MAJ20

MAJ21

minus1

minus1

minus1

minus1

minus1

1

minus1

minus1

1

minus1

minus1

minus1

1

minus1minus1

minus1

minus1

1

minus1

minus1

1

minus1

minus1

minus1

minus1

Figure 9 HDLQ modelling of QCA-based fault-tolerant adder

8 ISRN Electronics

Table 4 Fault pattern of proposed fault-tolerant adder

Input Output Fault pattern Success rate FT1 2 3 sdot sdot sdot 43 44 45 sdot sdot sdot 76 77 78

1198860

1198860

11988616119886121198860sdot sdot sdot 119886

211988611198860sdot sdot sdot 119886

1211988611198860

3278 41021198861

1198861

11988617119886131198861sdot sdot sdot 119886

311988601198861sdot sdot sdot 119886

111988601198860

3478 43591198862

1198867

1198862311988681198867sdot sdot sdot 119886

511988661198867sdot sdot sdot 119886

711988661198867

3878 48721198863

1198866

1198862211988681198867sdot sdot sdot 119886

411988671198866sdot sdot sdot 119886

611988661198866

3878 48721198864

1198864

11988620119886111198864sdot sdot sdot 119886

611988651198864sdot sdot sdot 119886

511988641198864

3778 47431198865

1198865

11988621119886101198865sdot sdot sdot 119886

711988641198865sdot sdot sdot 119886

511988651198865

3978 50001198866

1198863

11988619119886151198863sdot sdot sdot 119886

111988621198863sdot sdot sdot 119886

311988621198863

4078 5128

11988630

11988617

119886131198861711988619sdot sdot sdot 119886

191198861611988617sdot sdot sdot 119886

171198861611988617

4178 525611988631

11988616

119886121198861611988618sdot sdot sdot 119886

181198861711988616sdot sdot sdot 119886

161198861611988616

4278 5378Average FT = fault tolerance 4738

In the proposed work the QCA layout of the FTRA gateis converted into the corresponding hardware descriptionlanguage notations using the HDLQ Verilog library [18] TheHDLQ design tool Verilog equivalent for QCA consists of aVerilog HDL library of QCA devices that is MV INV FOCrosswire (CW) and L-shape wire with fault injection capa-bilityThe HDLQ-modeled design of the FTRA gate is shownin Figure 9 and an exhaustive testing of the HDLQ modelof the FTRA gate is conducted with 32 input patterns in thepresence of all possible single missingadditional cell defectsThe design is simulated using the Verilog HDL simulatorin the presence of faults to determine the correspondingoutputs

Testing of the FTRA gate generated 78 unique fault pat-terns at the output as shown in Table 4 Due to huge volumeof data the fault pattern table is partially shown In the faultpatterns study shown in the Table 4 119886

119894is the five-bit pattern

with an equivalent decimal value of 119894 For example 1198860repre-

sents 00000 (decimal 0) and 11988631represents 11111 (decimal 31)

In Table 4 first two columns present the correct behaviour ofFTRAgate that is for a particular input vector correspondingexpected output vector Each row of the Table 4 representsthe output generated after the fault injection of different 78modules of the HDLQ model (Figure 9) for example forgiven input 119886

0 after the fault injection of different modules

the generated fault pattern is 1198860 11988616 11988612 119886

1 1198860 From

those fault patterns we observed that there are average 4738successful patterns that produce the correct output evenwhen there is a fault

7 Conclusions

This work presents a novel architecture of fault-tolerantreversible adder (FTRA) gate Experimental results estab-lish the fact that the proposed FTRA achieved signifi-cant improvements in reversible circuits over the existingones A reversible arithmetic logic unit is synthesized basedon the FTRA proposed This is first attempt to synthesize afault-tolerant full addersubtractor using only single revers-ible logic block (FTRA) with optimal quantum cost toavoid wire-crossing bottleneck Also the application of this

fault-tolerant logic in QCA nanotechnology gets an extraadvantage in fault-tolerant computing with effective 4738fault-free output in the presence of all possible single miss-ingadditional cell defects

Though the clocking structure beneath the QCA celllayer is also very important and nontrivial research issue

Acknowledgment

Theauthors would like to thankMr Samik Some UG studentof CSE department NIT Durgapur for his valuable help intesting the design using HDLQ tool

References

[1] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 5no 3 pp 183ndash191 1961

[2] C H Bennett ldquoLogical reversibility of computationrdquo IBM Jour-nal of Research andDevelopment vol 17 no 6 pp 525ndash532 1973

[3] C S Lent P D Tougaw W Porod and G H BernsteinldquoQuantum cellular automatardquo Nanotechnology vol 4 no 1 pp49ndash57 1993

[4] Z Guan W Li W Ding Y Hang and L Ni ldquoAn arithmeticlogic unit design based on reversible logic gatesrdquo in Proceedingsof the 13th IEEE Pacific Rim Conference on CommunicationsComputers and Signal Processing (PacRim rsquo11) pp 925ndash931August 2011

[5] M Morrison and N Ranganathan ldquoDesign of a reversible ALUbased on novel programmable reversible logic gate structuresrdquoin Proceedings of IEEE Computer Society Annual Symposium onVLSI (ISVLSI rsquo11) pp 126ndash131 Washington DC USA July 2011

[6] Y Syamala andA V N Tilak ldquoReversible arithmetic logic unitrdquoin Proceedings of the 3rd International Conference on ElectronicsComputer Technology (ICECT rsquo11) pp 207ndash211 April 2011

[7] J W Bruce M A Thornton L Shivakumaraiah P S Kokateand X Li ldquoEfficient adder circuits based on a conservativereversible logic gaterdquo in Proceedings of IEEE Symposium onVLSI pp 83ndash88 Washington DC USA 2002

[8] M Haghparast and K Navi ldquoA novel fault tolerant reversiblegate for nanotechnology based systemsrdquo American Journal ofApplied Sciences vol 5 no 5 pp 519ndash523 2008

ISRN Electronics 9

[9] Md S Islam M M Rahman Z Begum and M Z HafizldquoEfficient approaches for designing fault tolerant reversiblecarry look-ahead and carry-skip addersrdquo MASAUM Journal ofBasic and Applied Sciences vol 1 no 3 pp 354ndash360 2009

[10] S K Mitra and A R Chowdhury ldquoMinimum cost fault tolerantadder circuits in reversible logic synthesisrdquo in Proceedings of the25th International Conference on VLSI Design (VLSID rsquo12) pp334ndash339 January 2012

[11] K Walus T J Dysart G A Jullien and R A BudimanldquoQCADesigner a rapid design and simulation tool for quan-tum-dot cellular automatardquo IEEE Transactions on Nanotechnol-ogy vol 3 no 1 pp 26ndash31 2004

[12] T Toffoli ldquoReversible computingrdquo in Proceedings of the 7thColloquium on Automata Languages and Programming pp632ndash644 Springer London UK 1980

[13] M Perkowski M Lukac P Kerntopf et al ldquoA hierarchicalapproach to computer-aided design of quantum circuitsrdquo inProceedings of the 6th International Symposium on Representa-tions andMethodology of Future Computing Technology pp 201ndash209 2003

[14] B Parhami ldquoFault-tolerant reversible circuitsrdquo in Proceedings ofthe 40th Asilomar Conference on Signals Systems and Comput-ers (ACSSC rsquo06) pp 1726ndash1729 November 2006

[15] X Ma and F Lombardi ldquoFault tolerant schemes for QCA sys-temsrdquo in Proceedings of the 23rd IEEE International Symposiumon Defect and Fault Tolerance in VLSI Systems (DFT rsquo08) pp236ndash244 October 2008

[16] M B Tahoori J Huang M Momenzadeh and F LombardildquoTesting of quantum cellular automatardquo IEEE Transactions onNanotechnology vol 3 no 4 pp 432ndash442 2004

[17] M Momenzadeh M Ottavi and F Lombardi ldquoModelingQCA defects at molecular-level in combinational circuitsrdquo inProceedings of the 20th IEEE International Symposium on Defectand Fault Tolerance in VLSI Systems (DFT rsquo05) pp 208ndash216October 2005

[18] M Ottavi L Schiano F Lombardi and D Tougaw ldquoHDLQ aHDL environment for QCA designrdquo Journal on Emerging Tech-nologies in Computing Systems vol 2 no 4 pp 243ndash261 2006

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

8 ISRN Electronics

Table 4 Fault pattern of proposed fault-tolerant adder

Input Output Fault pattern Success rate FT1 2 3 sdot sdot sdot 43 44 45 sdot sdot sdot 76 77 78

1198860

1198860

11988616119886121198860sdot sdot sdot 119886

211988611198860sdot sdot sdot 119886

1211988611198860

3278 41021198861

1198861

11988617119886131198861sdot sdot sdot 119886

311988601198861sdot sdot sdot 119886

111988601198860

3478 43591198862

1198867

1198862311988681198867sdot sdot sdot 119886

511988661198867sdot sdot sdot 119886

711988661198867

3878 48721198863

1198866

1198862211988681198867sdot sdot sdot 119886

411988671198866sdot sdot sdot 119886

611988661198866

3878 48721198864

1198864

11988620119886111198864sdot sdot sdot 119886

611988651198864sdot sdot sdot 119886

511988641198864

3778 47431198865

1198865

11988621119886101198865sdot sdot sdot 119886

711988641198865sdot sdot sdot 119886

511988651198865

3978 50001198866

1198863

11988619119886151198863sdot sdot sdot 119886

111988621198863sdot sdot sdot 119886

311988621198863

4078 5128

11988630

11988617

119886131198861711988619sdot sdot sdot 119886

191198861611988617sdot sdot sdot 119886

171198861611988617

4178 525611988631

11988616

119886121198861611988618sdot sdot sdot 119886

181198861711988616sdot sdot sdot 119886

161198861611988616

4278 5378Average FT = fault tolerance 4738

In the proposed work the QCA layout of the FTRA gateis converted into the corresponding hardware descriptionlanguage notations using the HDLQ Verilog library [18] TheHDLQ design tool Verilog equivalent for QCA consists of aVerilog HDL library of QCA devices that is MV INV FOCrosswire (CW) and L-shape wire with fault injection capa-bilityThe HDLQ-modeled design of the FTRA gate is shownin Figure 9 and an exhaustive testing of the HDLQ modelof the FTRA gate is conducted with 32 input patterns in thepresence of all possible single missingadditional cell defectsThe design is simulated using the Verilog HDL simulatorin the presence of faults to determine the correspondingoutputs

Testing of the FTRA gate generated 78 unique fault pat-terns at the output as shown in Table 4 Due to huge volumeof data the fault pattern table is partially shown In the faultpatterns study shown in the Table 4 119886

119894is the five-bit pattern

with an equivalent decimal value of 119894 For example 1198860repre-

sents 00000 (decimal 0) and 11988631represents 11111 (decimal 31)

In Table 4 first two columns present the correct behaviour ofFTRAgate that is for a particular input vector correspondingexpected output vector Each row of the Table 4 representsthe output generated after the fault injection of different 78modules of the HDLQ model (Figure 9) for example forgiven input 119886

0 after the fault injection of different modules

the generated fault pattern is 1198860 11988616 11988612 119886

1 1198860 From

those fault patterns we observed that there are average 4738successful patterns that produce the correct output evenwhen there is a fault

7 Conclusions

This work presents a novel architecture of fault-tolerantreversible adder (FTRA) gate Experimental results estab-lish the fact that the proposed FTRA achieved signifi-cant improvements in reversible circuits over the existingones A reversible arithmetic logic unit is synthesized basedon the FTRA proposed This is first attempt to synthesize afault-tolerant full addersubtractor using only single revers-ible logic block (FTRA) with optimal quantum cost toavoid wire-crossing bottleneck Also the application of this

fault-tolerant logic in QCA nanotechnology gets an extraadvantage in fault-tolerant computing with effective 4738fault-free output in the presence of all possible single miss-ingadditional cell defects

Though the clocking structure beneath the QCA celllayer is also very important and nontrivial research issue

Acknowledgment

Theauthors would like to thankMr Samik Some UG studentof CSE department NIT Durgapur for his valuable help intesting the design using HDLQ tool

References

[1] R Landauer ldquoIrreversibility and heat generation in the comput-ing processrdquo IBM Journal of Research and Development vol 5no 3 pp 183ndash191 1961

[2] C H Bennett ldquoLogical reversibility of computationrdquo IBM Jour-nal of Research andDevelopment vol 17 no 6 pp 525ndash532 1973

[3] C S Lent P D Tougaw W Porod and G H BernsteinldquoQuantum cellular automatardquo Nanotechnology vol 4 no 1 pp49ndash57 1993

[4] Z Guan W Li W Ding Y Hang and L Ni ldquoAn arithmeticlogic unit design based on reversible logic gatesrdquo in Proceedingsof the 13th IEEE Pacific Rim Conference on CommunicationsComputers and Signal Processing (PacRim rsquo11) pp 925ndash931August 2011

[5] M Morrison and N Ranganathan ldquoDesign of a reversible ALUbased on novel programmable reversible logic gate structuresrdquoin Proceedings of IEEE Computer Society Annual Symposium onVLSI (ISVLSI rsquo11) pp 126ndash131 Washington DC USA July 2011

[6] Y Syamala andA V N Tilak ldquoReversible arithmetic logic unitrdquoin Proceedings of the 3rd International Conference on ElectronicsComputer Technology (ICECT rsquo11) pp 207ndash211 April 2011

[7] J W Bruce M A Thornton L Shivakumaraiah P S Kokateand X Li ldquoEfficient adder circuits based on a conservativereversible logic gaterdquo in Proceedings of IEEE Symposium onVLSI pp 83ndash88 Washington DC USA 2002

[8] M Haghparast and K Navi ldquoA novel fault tolerant reversiblegate for nanotechnology based systemsrdquo American Journal ofApplied Sciences vol 5 no 5 pp 519ndash523 2008

ISRN Electronics 9

[9] Md S Islam M M Rahman Z Begum and M Z HafizldquoEfficient approaches for designing fault tolerant reversiblecarry look-ahead and carry-skip addersrdquo MASAUM Journal ofBasic and Applied Sciences vol 1 no 3 pp 354ndash360 2009

[10] S K Mitra and A R Chowdhury ldquoMinimum cost fault tolerantadder circuits in reversible logic synthesisrdquo in Proceedings of the25th International Conference on VLSI Design (VLSID rsquo12) pp334ndash339 January 2012

[11] K Walus T J Dysart G A Jullien and R A BudimanldquoQCADesigner a rapid design and simulation tool for quan-tum-dot cellular automatardquo IEEE Transactions on Nanotechnol-ogy vol 3 no 1 pp 26ndash31 2004

[12] T Toffoli ldquoReversible computingrdquo in Proceedings of the 7thColloquium on Automata Languages and Programming pp632ndash644 Springer London UK 1980

[13] M Perkowski M Lukac P Kerntopf et al ldquoA hierarchicalapproach to computer-aided design of quantum circuitsrdquo inProceedings of the 6th International Symposium on Representa-tions andMethodology of Future Computing Technology pp 201ndash209 2003

[14] B Parhami ldquoFault-tolerant reversible circuitsrdquo in Proceedings ofthe 40th Asilomar Conference on Signals Systems and Comput-ers (ACSSC rsquo06) pp 1726ndash1729 November 2006

[15] X Ma and F Lombardi ldquoFault tolerant schemes for QCA sys-temsrdquo in Proceedings of the 23rd IEEE International Symposiumon Defect and Fault Tolerance in VLSI Systems (DFT rsquo08) pp236ndash244 October 2008

[16] M B Tahoori J Huang M Momenzadeh and F LombardildquoTesting of quantum cellular automatardquo IEEE Transactions onNanotechnology vol 3 no 4 pp 432ndash442 2004

[17] M Momenzadeh M Ottavi and F Lombardi ldquoModelingQCA defects at molecular-level in combinational circuitsrdquo inProceedings of the 20th IEEE International Symposium on Defectand Fault Tolerance in VLSI Systems (DFT rsquo05) pp 208ndash216October 2005

[18] M Ottavi L Schiano F Lombardi and D Tougaw ldquoHDLQ aHDL environment for QCA designrdquo Journal on Emerging Tech-nologies in Computing Systems vol 2 no 4 pp 243ndash261 2006

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

ISRN Electronics 9

[9] Md S Islam M M Rahman Z Begum and M Z HafizldquoEfficient approaches for designing fault tolerant reversiblecarry look-ahead and carry-skip addersrdquo MASAUM Journal ofBasic and Applied Sciences vol 1 no 3 pp 354ndash360 2009

[10] S K Mitra and A R Chowdhury ldquoMinimum cost fault tolerantadder circuits in reversible logic synthesisrdquo in Proceedings of the25th International Conference on VLSI Design (VLSID rsquo12) pp334ndash339 January 2012

[11] K Walus T J Dysart G A Jullien and R A BudimanldquoQCADesigner a rapid design and simulation tool for quan-tum-dot cellular automatardquo IEEE Transactions on Nanotechnol-ogy vol 3 no 1 pp 26ndash31 2004

[12] T Toffoli ldquoReversible computingrdquo in Proceedings of the 7thColloquium on Automata Languages and Programming pp632ndash644 Springer London UK 1980

[13] M Perkowski M Lukac P Kerntopf et al ldquoA hierarchicalapproach to computer-aided design of quantum circuitsrdquo inProceedings of the 6th International Symposium on Representa-tions andMethodology of Future Computing Technology pp 201ndash209 2003

[14] B Parhami ldquoFault-tolerant reversible circuitsrdquo in Proceedings ofthe 40th Asilomar Conference on Signals Systems and Comput-ers (ACSSC rsquo06) pp 1726ndash1729 November 2006

[15] X Ma and F Lombardi ldquoFault tolerant schemes for QCA sys-temsrdquo in Proceedings of the 23rd IEEE International Symposiumon Defect and Fault Tolerance in VLSI Systems (DFT rsquo08) pp236ndash244 October 2008

[16] M B Tahoori J Huang M Momenzadeh and F LombardildquoTesting of quantum cellular automatardquo IEEE Transactions onNanotechnology vol 3 no 4 pp 432ndash442 2004

[17] M Momenzadeh M Ottavi and F Lombardi ldquoModelingQCA defects at molecular-level in combinational circuitsrdquo inProceedings of the 20th IEEE International Symposium on Defectand Fault Tolerance in VLSI Systems (DFT rsquo05) pp 208ndash216October 2005

[18] M Ottavi L Schiano F Lombardi and D Tougaw ldquoHDLQ aHDL environment for QCA designrdquo Journal on Emerging Tech-nologies in Computing Systems vol 2 no 4 pp 243ndash261 2006

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of