rémi cornat (in2p3/lpc) - prr june’06 preshower fe board design r. bonnefoy, g. bohner, c....
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Rémi CORNAT (IN2P3/LPC) - PRR june’06
Preshower FE Board design
R. Bonnefoy, G. Bohner, C. Cârloganu, E. Conte, R. Cornat, E. Delage, J. Lecoq
M-L. Mercier, P. Perret
2Rémi CORNAT (IN2P3/LPC) - PRR june’06
Overview : FE board
x 64
Clock distribution
ECS : GLUE (LAL)
Each AX receives 8 SPD bits
8 AX1000 (data proc. + L0)
64 ADC + Op. Amp
TRIG : APA450
2*64 trigger bits SPD multiplicity and 2x2 cluster
DAQ & TTC : SEQ (LAL)VFE clk & rst
Power & delatchers I
II
III
IV
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PCB & I/Os
12 layers, class 6 LAL backplane & crate
1 test support on one FE_PGA
Connector for external USB/I2C generator (needs GLUE modifications)
64 analogue inputs
RJ45 connectors
Ethernet CAT6 cable
2 clk & 2 rst to VFE
Differential ECL on cables 64 SPD inputs
Serial LVDS on cables
20 bits to DAQ
Serial LVDS on backplane
TRIG TOP/BOT neighbours
2*16b serial LVDS on cables
TRIG RIGHT/LEFT neigh.
2*18 LVDS on backplane
2 ECAL @+BXID
2*21 bits serial LVDS on cables
SPD multiplicity
21b serial LVDS on backplane
2x2 cluster to VALIDATION
2*13b serial LVDS on cables
4Rémi CORNAT (IN2P3/LPC) - PRR june’06
On board data flow
Point to point parallel links only– Easy to test with injection
and acquisitions RAM in FE, TRIG and SEQ pgas
Production Commissioning
– JTAG scan path available
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Tests connectors
JTAG– Program (APA)– Test (externally
cabled JTAG chain thanks to individual connectors)
Tests (SiliconExplorer)
– Debugging steps
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TTC & clocksECS
I2C : point to point from GLUE to chips
Clocks : LVDS– LAL delay
chips– Converted to
CMOS close to chips
L0Ch B
I2CRST
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ECS
Same as ECAL FE board (SPECS, CROC, GLUE)
LPC made I2C interface– Used on L0DU & VALIDATION board– ACK check– 8b reg. addressed according to their position into
the frame Reg. bank loaded in 1 frame (SW opt.)
8Rémi CORNAT (IN2P3/LPC) - PRR june’06
Power supply
Use of -3.3 and 3.3 V only– Not compatible with
ECAL/HCAL FE boards
-3.3V, 1.5 and 2.5 V made with LHC regulators
SEL sensitive components are protected with self switch-off current limiters
– Switch with feed back acting as « delatchers »
– Partitions of components
-5 1 A / board (ECAL -5V)
+3.3 D 3 A / board (ECAL 3.3V)
+3.3 D
+3.3 A (ECAL +5V)
+3.3 A
+5 Vfree1 Aux for PS CROC
9Rémi CORNAT (IN2P3/LPC) - PRR june’06
Switch characteristics
Current limiter – (2A : MAX869, 1.2A : MAX890, – 0.5A : MAX891,…)
2.7 to 5.5 V Switch resistance : 90 m typ.@3V Programmable current limit (external
resistor)– Minimum limit is 0.2*Imax (240 mA for
MAX890) Fault indicator Enable input (forced switch off is
possible) Thermal shutdown MAX869L was tested at GANIL by
LAL SN74LVC10 tested by ATLAS
Test circuit
74LVC010
Rémi CORNAT (IN2P3/LPC) - PRR june’06
FE pga
AX1000
Digital processing
11Rémi CORNAT (IN2P3/LPC) - PRR june’06
FEpga
AX1000 pga : digital processing & L0/DAQ 8b SPD data Pipe-lines (ECAL vs PS, SPD vs PS) Tests RAMS (injection & acquisition) ECS : 3 banks of resp. 10, 2*34 8b reg. +
RAMs
LAL L0 readout ECS interfaces are LPC made
Worst case : 56 MHz Best case : slack > 300 ps Cells : 53%, RAM : 70%, IO : 50%
Back annotated simulations– Entry point : I2C
12Rémi CORNAT (IN2P3/LPC) - PRR june’06
Digital processing
UUU nncorr 1
8 bits parametersOptimized operators sizes4 pipe-line steps
Offset [0..255] Gain = 1+ G/512, G [0..255] Alpha = A/512, A [0..255] Trigger threshold [0..255]
13Rémi CORNAT (IN2P3/LPC) - PRR june’06
General architecture
I2C1I2csl7b_2
ECS1Psfeeecs_protocol_34_e
rr
STOCKAGE16B4VHamming_partiel4voies4a16
DECODEURHamming_22_16_3_decoder
PIPELINEBYPASSTmr_registerr
RAM+MUX
PIPELINE1pipelineced
PIPELINE2pipelineced
PIPELINE3pipelineced
PIPELINE4pipelineced
ALGO1Psdataalgo_bp
ALGO2Psdataalgo_bp
ALGO3Psdataalgo_bp
ALGO4Psdataalgo_bp
TV1Flags_register
TV1Flags_register
TV1Flags_register
OR
TVERRTmr_tv
ALGOETHAMMING
Muxdreg
Error bit
Error flags
ECS data
Load command bits and data dispatching
Pipeline length bypass
Error bits
Algo. param
eters
40 MHz data
40 MHz data
Trig_out
Data_out
Trig_out
Trig_out
Trig_out
Data_out
Data_out
Data_out
Communication bus (i2c)
PHY
protocol
ACQ RAM
14Rémi CORNAT (IN2P3/LPC) - PRR june’06
HammingFor parameters registers
load_ecs
22 bits words
– 16 data bits– 5 hamming bits– 1 global parity bit– Loaded by 8 bits slices
from I2C 1 bit error correction 2 bits error detection Decoder shared among 12 22b
registers
– Cyclic check and correction using a counter
Hamming decoder
tmr counter
offset gain alphaetthreshold
222222
22
22
2222
Bits Mapping Bits Mapping
Half channel synchronization
Half channel synchronization
offset1 offset2
gain1 gain2
alpha
threshold
88 88 8 8
88
offset gain
synchro
mux
errcod 2
Bits Mapping
Rémi CORNAT (IN2P3/LPC) - PRR june’06
Trigger part
16Rémi CORNAT (IN2P3/LPC) - PRR june’06
L0 trigger
Link ECAL to PS/SPD
Trigger data = 1b/ch
17Rémi CORNAT (IN2P3/LPC) - PRR june’06
Overview : trigger functions
Interconnection between :– SPD and PS (boards corresponding to the same cells) :
24m serial LVDS– Adjacent PS board (T/B : lvcmos 40MHz, R/L : serial LVDS)– ECAL and PS (boards corresponding to the same cells) :
serial LVDS– PS and ECAL validation board : serial LVDS– PS and SPD control board (multiplicity) : serial LVDS
Synchronization : compensate latencies Cells mapping issue : geographic algorithms 2x2 cluster search algorithm for SPD an PS trigger
bits
18Rémi CORNAT (IN2P3/LPC) - PRR june’06
Trigger task
Two cluster addresses sent by ECAL– One per half PS FE Board
SPD data deserilization– Received in FE PGAs : sent to DAQ– Centralized into TRIG PGA
Neighbours algorithm– Transmission between boards– Simple multiplexor…– Need one Tclk
Algorithm validated (Q1’01 prototype) SPD Multiplicity
– Adder tree Data synchronization
– Many pipe-lines…
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Timing model
6 pipe-line length to set
20Rémi CORNAT (IN2P3/LPC) - PRR june’06
P&R results
Worst case : 52 MHz Best case : slack > 55 ps Cells : 38%, RAM : 69%, IO : 90%
P&R : routing resources usage close to a limit (uncertain P&R result)
– Routing is critical– Frozen pin positions (PCB)– Large buses (128b typ) to connect
mapping steps, pipe-lines, RAMS, etc…
– 5% more nets lead to 20% loss in max. frequency
But : current version is ok and seem to be final
Rémi CORNAT (IN2P3/LPC) - PRR june’06
Clock and timing
22Rémi CORNAT (IN2P3/LPC) - PRR june’06
Logical clock tree
Clk taken from the backplane
No LVDS RT fan-out found…
– Delay chips and LV048 – Multidrop LVDS (Up to
2*4 LVDS buffers per branch)
Tree trunk and branches are LVDS
Tree leaves are LVTTL
Delay chips allow to set– VFE (start of analogue
integration time)– VFERST (phase of VFE rst
signal)– ADC (analogue signal
sampling time)– ADC’ (ADC data sampling
time into FE_PGAs)– Sampling times of serial
LVDS data (SPD, ECAL, TOP)
23Rémi CORNAT (IN2P3/LPC) - PRR june’06
Clock inside PGAs
Use of PLL
Dedicated pins to use hardwired clock trees
Clock regions to optimize best case timing slack (TRIG)
SCLECAL
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Clock model
P0
Fe_PGA
25Rémi CORNAT (IN2P3/LPC) - PRR june’06
Clock distribution (schematics)
4*16 ADCs
Global clk
8 FE1 TRIG1 SEQ1 GLUE
4 serializers
SPD inFEpga
VFE
ADC inFEpga
Inputs of TRIGpga
Rémi CORNAT (IN2P3/LPC) - PRR june’06
SEL & SEU protection
27Rémi CORNAT (IN2P3/LPC) - PRR june’06
Radiation test of the Preshower electronics
Have been tested at Ganil in April 2003
– Front-End electronic ADC (AD9203): 4
chips Operational Amplifier
(AD8132): 4 chips– Very-Front-End
electronic New version of the
ASIC integrator: 2 chips with 1 complete channel each
Active PMT Base (AB): 2 basis with 2 HV transistors each
No cumulated dose effects– 26 krad for AB, ASIC and OA– 52 krad for ADC
Some SEL observed for ADC– Not destructive
The 4 ADC have been tested getting back to laboratory
– They all work perfectly Current in the ADC increased
“only” by a factor 3 to 4– Holding the power supply voltage in the
required range
– Estimation : 10 SEL per year– Use of delatchers
No SEL for AB, ASIC and OA
28Rémi CORNAT (IN2P3/LPC) - PRR june’06
Triple voting
Antifuse PGA (FE), RT flash PGA (TRIG, SEQ, GLUE)
Triple voting technique :– Used on control bits and FSM state register– Used on RAM address counters– Hamming counters developed (HDL) – Error bits are summarized (logical OR)
29Rémi CORNAT (IN2P3/LPC) - PRR june’06
EDAC Hamming coding
22 bits words– 16 data bits– 5 hamming bits– 1 global parity bit
1 bit error correction 2 bits error detection Decoder can be shared
with many registers– Cyclic check and
correction using a counter
Saves a lot of flip-flops Needs combinational logic Used for alg. param. reg.
Synthesis results (4 FE channels) :
comb seq
Ham 624 230
tv 980 576
30Rémi CORNAT (IN2P3/LPC) - PRR june’06
Current prototype
Main current switch needs more studies
ECS error rate too high
– Errors seen on SPECS signals before CROC
PCB & PGA intensely tested
Rémi CORNAT (IN2P3/LPC) - PRR june’06
Annexes
Rémi CORNAT (IN2P3/LPC) - PRR june’06
Analogue receiver & digitization
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Analogue receiver & ADC
Q2’01
34Rémi CORNAT (IN2P3/LPC) - PRR june’06
Prototype
Constraints– 1 cm height per channel
64 channels/32 cm
– EMC
Noise σ=0,8 mV lowered to 0,4 mV
PCB hierarchical block– CMS 0805– AD9203– Compact placement
– Ground plane– Signal diff. pairs– Diff. clock
35Rémi CORNAT (IN2P3/LPC) - PRR june’06
New analogue module
Refined component placement
Compatible for both ADC multiplexing and direct connection to Fe_PGA
Optimized differential signal traces
Q4’03