INTRODUCTORY REVIEW PAPER

RELIABILITY PHENOMENA UNDER AC STRESS

CHENMING HU

Department of Electrical Engineering and Computer Sciences, University of California, 502 Cory Hall,Berkeley, CA 94720-1770, USA

(Received 7 February 1997)

AbstractÐReliability phenomena are usually studied as DC e�ects at ®rst. AC e�ects become importantto setting realistic reliability acceptance criteria and predicting circuit reliability as technology scalinggradually erodes the margin of safety. This paper reviews the AC e�ects in hot-electron e�ect, electro-migration, and gate oxide breakdown and stability. # 1998 Elsevier Science Ltd.

INTRODUCTION

Reliability physics of IC has been well studied

under DC stress conditions. In wafer-level testing,DC stress test is also the standard practice. Tocover all possible AC stress conditions ± frequency,

duty factor, rise time, etc. ± would consume toomuch testing time.On the other hand, AC stress, whether in hot-car-

rier e�ect, electromigration, or gate oxide wearout,is the norm in actual IC operation. The di�erencebetween AC and DC reliability can sometimes leadto very di�erent predictions of IC reliability, e.g.

lifetimes di�ering by orders of magnitude. It istherefore important to determine the reliabilityunder AC stress, and it is desirable to do so without

performing exhaustive AC testing.This paper reviews the hot-carrier e�ect, electro-

migration, and oxide reliability under AC stress.

HOT-ELECTRON EFFECT

In the 1980s it was a common practice in the ICindustry to guarantee a 10 yr lifetime under DChot-electron stress at Vds=Vdd (or 110% of Vdd)and the worst-case Vgs for 10% linear Id degra-

dation. With technology scaling to 0.8 mm andbelow, this worst-case DC lifetime criterion hasbecome impossible or incompatible with high-per-

formance MOSFET design. AC consideration hasbeen invoked to justify the acceptance of a DC life-time considerably shorter than 1 yr because the

duty factor in digital circuits is considerably lessthan one.It is interesting to recall that it took 10 yr for the

research community to even accept the fact that theAC to DC lifetime ratio is larger than one.Through the 1980s and early 1990s many research-ers have reported that this ratio is less than one

because alternate injections of electrons and holes

into the oxide create more damage than the worst

case DC stress. Today it is generally agreed that

those studies were ¯awed in voltage overshoot

(inductive noise) and/or unrealistic voltage wave-

forms. Fortuitously, the realistic waveforms in digi-

tal circuits do allow us to apply the DC lifetime

corrected by an AC to DC lifetime ratio that is lar-

ger than one [1, 2].

The remaining question is ``What is the magni-

tude of the AC to DC lifetime ratio?'' A simple

model has been developed for this ratio [3]:

AC to DC lifetime ratio � 4

ftrfor NMOSFET �1�

AC to DC lifetime ratio � 10

ftffor PMOSFET �2�

where f is the switching frequency and tr and tf are

the gate signal rise and fall times. This model

simply states that the e�ective stress time is tr/4 and

tf/10, respectively, i.e. e�ective stress only occurs

during a narrow range of Vg roughly 1/4 and 1/10

of Vdd, respectively. This point is illustrated in

Fig. 1 for NMOSFET.

A more important, though less discussed, ``AC

e�ect'' is the impact of 10% linear DId on logic gate

delay. We have found the corresponding inverter

delay to be 2% or less [4]. We recommend the use

of DIdsat where 10% of DIdeat corresponds to about

3% of inverter delay.

Clearly, the ideal methodology is to develop the

MOSFET using Equations (1) and (2) for a typical,

but not the worst case, tf and use a CAD tool such

as BERT (Berkeley Reliability Tool) [5] to simulate

the hot-electron e�ect on actual speed (and other

characteristics) of a circuit (Fig. 2). The CAD tool

takes into account the stressing waveform [more

accurately than Equations (1) and (2)], the e�ect of

Microelectron. Reliab., Vol. 38, No. 1, pp. 1±5, 1998# 1998 Elsevier Science Ltd

All rights reserved. Printed in Great Britain0026-2714/98 $19.00+0.00PII: S0026-2714(97)00163-7

1

Id degradation on gate delay, the competing e�ect

of PMOSFET drift, and the combined e�ect on the

speed of a large circuit. To illustrate the use of

CAD, Fig. 3 shows the degradation of the critical

path of a benchmark circuit containing a few thou-

sand transistors [6]. A CAD based hot-electron re-

liability methodology would lead to optimum

MOSFET performance consistent with circuit re-

liability.

Table 1 shows the simulated lifetimes of the

degradation of critical path delays [7]. Results are

presented for three benchmark circuits, each con-

taining 1800 to 3400 transistors. The transistor life-

time is 0.15 yr under worst-case DC stress for the

linear current to degrade by 10%. Table 1 shows

that in 10 yr the circuit speed degraded by 0.55% to

0.94%. The maximum transistor linear current

degradation is 10.4% to 13.6% (in 10 yr not

0.15 yr). It would take 49 to 141 yr for the circuit

speed to degrade by 2%, at which time the transis-

tors having the largest current degradation in the

circuits would have lost 24.5% to 28.8% of theirlinear current. To lose 5% of speed would havetaken 405 to 1390 yr. These are far cries from the0.15 yr of DC device lifetimes.

ELECTROMIGRATION

Electromigration capability (design rule) of metalinterconnects and vias is routinely characterizedunder DC stress conditions. By now it is widely

agreed that such a design rule should be interpretedas the average rather than RMS current that ¯owsin the metals that carry time-varying but uni-

directional current [8]. However, the case where thecurrent ¯ows in both directions poses greater chal-lenges for model development [8, 9].

If one interprets the EM design rule as the aver-age current, interconnect and vias that carry pureAC (no DC component) current should have verylong lifetimes. This is indeed the case as dramati-

cally demonstrated in Fig. 4 [10].When the stress current frequency is high enough

so that the metal does not fail during the ®rst half

cycle (otherwise, DC lifetime is observed), EM life-time rises rapidly with increasing frequency until nofailure can be observed. Arrows in Fig. 4 indicate

the time test was terminated (without any failures).Note that test frequency ranges up to 300 MHz andthe AC lifetime is at least 100,000 times the DC life-

time. Essentially, one need not be concerned withthe AC current component in EM reliability. Onlyself-heating and IR drop limit the ability of metalto carry AC current [10]. Figure 5 shows that highly

Fig. 1. NMOSFET age rate during circuit transient.NMOSFET age rate is a function of the substrate current.

The overlap time is a quarter of the rise time.

Fig. 2. Demonstrates that the model is in excellent agree-ment with experimental data over a wide range of tr, f,technology, and power supply voltage. Thus, this model

may be considered universal.

Fig. 3. This 0.5 mm technology exhibits a 10.19% linear DIin 1 yr of DC stress at 5 V. In the critical path of a largecircuit, the actual Id degradation range from 1.4% to3.3% and the critical path speed degraded by only 0.48%.

C. Hu2

asymmetrical W plug vias exhibit the same self-heal-

ing phenomenon.

An accurate AC EM model may be more import-

ant than a DC model. If the DC current buses are

overdesigned, the penalty is silicon area. If the ACcurrent buses (clock buses and signal lines) are

overdesigned, the penalties are silicon area, speed,

and power; because the AC interconnects are sig-

ni®cant to dominant contributors to the capacitiveloads of the circuits.

AC stress studies also o�er new insights into re-

liability physics. For a long time, it was not clear ifTiN, an important material in stacked interconnects

today, exhibited electromigration. Figure 6 com-

pares the behavior of TiN and Al under alternating

current stress [11]. In the case of Al, every reversalof the current polarity causes the metal resistance

to recover some of the degradation induced by the

current stress of the preceding opposite polarity.

That is an indication of the self-healing of the elec-

tromigration phenomenon.

In the case of the TiN line, there is no evidence

of self-healing in Fig. 6. This suggests that increasein line resistance is not due to electromigration,

i.e. not caused by the electron wind or electronmomentum. Further studies [11] suggested that the

cause is thermal migration. The temperature gradi-ent at the location where the line meets the probepad causes a mass transport from the hot line tothe cold pad.

GATE OXIDE

The time dependent lifetime of gate oxide may be10 times longer than the DC lifetime [12, 13]. Thisis not yet considered signi®cant because the pre-

sence of defects can cause the oxide lifetime to varyby many orders of magnitude. Nonetheless, this isan interesting AC reliability phenomenon and has

immediate applications to high ®eld applicationssuch as nonvolatile memory (FN program anderase-AC stress, or FN erase only-DC stress) and

5 V IO circuits using 3.3 V oxide thickness, where a10� di�erence in oxide endurance may be import-ant.Figure 7 shows that time-to-breakdown rises with

frequency until it saturates at a value about 10� lar-ger than the DC lifetime. This has been explained[14] with the need for holes to drift from the anode

to the interior of the oxide where the holes generate

Table 1. Lifetimes of three benchmark CMOS circuits according to the degradation of critical path delay. NMOSFETchannel length is 0.5 mm and has 0.15 yr lifetime to 10% linear current degradation under DC stress. Vdd=5.5 V

CircuitFresh delay (ns) Delay degradation

(10 yr)Maximum transition

degreeAverage transition

degree

c880 7.37 0.55% 10.40% 5.68%c1355 7.80 0.79% 13.40% 7.40%c1908 9.88 0.94% 13.60% 7.15%

Circuit2% Life (yr) Maximum transition

degreeAverage transition

degree5% Life (yr)

c880 141 28.80% 16.80% 1390c1355 66.3 27.40% 16.30% 510c1908 49.4 24.50% 13.80% 405

Fig. 4. Frequency dependence of AC lifetime for Al±2%Siinterconnects. The solid line shows the prediction of the

damage healing model.Fig. 5. Via resistance change versus stress time under DC

and AC stresses for the W-plug structure.

Reliability phenomena under AC stress 3

electron traps that lead to enhanced current ¯owand breakdown. Under AC stress holes do not havethe time to drift far from the anode before the ®eld

is reversed, hence the oxide lifetime improves. Thissame model suggests that more interface traps maybe generated under AC stress than DC stress as

holes are con®ned near the anode interface, wherethey generate interface traps rather than bulk oxidetraps. This surprising AC e�ect is demonstrated in

Fig. 8.

SUMMARY

The AC hot-electron e�ect depends on the stresswaveform in the circuit and the complex relation-ship between current degradation and circuit drift.

Some simple models have been developed for theAC to DC lifetime ratio and the circuit to devicedegradation ratio. However, the ideal reliability en-gineering methodology would be the use of CAD

tools that simulate or verify circuit hot-electron re-

liability.The self-healing e�ect makes the electromigration

due to the AC current component negligible. Clockbuses and signal lines may be designed more aggres-

sively in current density for improved die size,speed, and power. AC testing shows that TiN andTiW degrade by thermal migration rather than elec-

tromigration. A separate AC design rule is war-ranted.A hole-drift model explains why AC oxide life-

time is 10 times larger, but the interface trap gener-ation rate is also much higher than the DC stress.These may be signi®cant for high ®eld applicationssuch as NVM tunnel oxide and high-voltage IOs.

AC reliability studies can help us predict circuitreliability more accurately and design more aggres-sive products without compromising reliability. AC

studies can also help clarify failure physics.

AcknowledgementsÐThis research is sponsored by SRCunder Contracts IJ-148 and BJ-407.

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