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Reliability enhancement of phase change memory for neuromorphic applications
SangBum Kim, Ph.D.
Research Staff Member
Novel memory and cognitive applications
IBM T.J. Watson Research Center [email protected]
© 2017 IBM Corporation
End of Moore’s Law
Moore’s Law is ending : No more processor performance growth.
“More-than Moore” solution : Build a new processor which does a few tasks extremely well. Which task should we choose to accelerate?
2 9/11/2017
D. Patterson, NAE Regional Meeting, 2017.
© 2017 IBM Corporation
Recent Breakthroughs in Artificial Intelligence
Artificial Intelligence became so important and companies are developing a dedicated processors for artificial intelligence. Google: TPU, Intel: Nervana Engine, Qualcomm, Apple
3 9/11/2017
Google CEO Sundar Pichai 2016 October
Wired Magazine, 2016
© 2017 IBM Corporation
Processors dedicated for artificial intelligence
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CPU
GPU, ASIC, FPGA
Neuromorphic
Digital
GPU vs CPU performance comparison
Digital
Now-5 years
Analog
5-10 years
performance/watt for artificial intelligence
(neural network) computation
Von-Neumann Non Von-Neumann
Neuromorphic vs GPU
GPU
Neuromorphic 1
Von-Neumann memory bottleneck
G. Burr et al., IEDM, 2015.
converged logic+memory
© 2017 IBM Corporation
Neuromorphic processor development in IBM
Artificial neural network (ANN) Spiking neural network (SNN) C
on
ven
tio
nal
d
igit
al m
em
ory
d
evic
e
An
alo
g n
on
-vo
lati
le m
em
ory
(N
VM
) d
evic
e
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P. Merolla et al., Science, 2014.
TrueNorth SRAM Off-chip
learning
G. Burr et al., IEDM, 2014.
NVM ML accelerator PCM On-chip
learning
S. Kim et al., IEDM, 2015.
NVM low-power ML PCM On-chip
learning
© 2017 IBM Corporation
Neuromorphic processor development in IBM
Artificial neural network (ANN) Spiking neural network (SNN) C
on
ven
tio
nal
d
igit
al m
em
ory
d
evic
e
An
alo
g n
on
-vo
lati
le m
em
ory
(N
VM
) d
evic
e
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P. Merolla et al., Science, 2014.
TrueNorth SRAM Off-chip
learning
G. Burr et al., IEDM, 2014.
NVM ML accelerator PCM On-chip
learning
S. Kim et al., IEDM, 2015.
NVM low-power ML PCM On-chip
learning
Today’s main topic: NVM + SNN
© 2017 IBM Corporation
Mismatch between algorithms and devices
All the scalable learning algorithms demonstrated so far requires near-perfect devices to match the state-of-the-art clarification accuracy and power & area efficiency.
How to improve synaptic device characteristics?
Can we modify learning algorithms such that they can work with
imperfect synaptic devices?
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© 2017 IBM Corporation
Phase change memory (PCM)
Memory states : Amorphous and poly-crystalline state
Program mechanism : Joule heating
Read mechanism : Resistance
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Crystalline Amorphous
High resistivity Low resistivity
Annealing (SET)
Melt-quenching (RESET)
BE Phase
change
material
TE
Programming
region
Te
mp
era
ture
Time
Tmelt
Tcrys
Read
SET pulse
RESET pulse
Troom
P. Wong et al., IEEE Proc., 2010
(7 at. % N-doped GST)
(Ge2Sb2Te5)
(Ag, In- doped Sb2Te1)
(Ge15Sb85)
Various phase change material Typical cell structure
Program and Read
© 2017 IBM Corporation
Power efficient PCM cell for neuromorphic applications
PCM power consumption can be further optimized for neuromorphic applications.
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PCM with CNT
R (Ω
)
IRESET (µA)
0.9pJ 30µA 1MΩ
P. Wong et al., Nat. Nanotech., 2015
S. Kim et al., IEDM, 2015
At 90nm node (BE CD = ~40nm)
Neuromorphic computing
Storage class
memory
Neuromorphic computing - Large SET R is OK. - Programming energy can be
further scaled down.
We significantly lowered the RESET programming current by heavily doping GST to increase the resistivity.
© 2017 IBM Corporation
PCM neuromorphic core
Synapse NVM PCM
Analog
Neuron / chip 256
Synapse / chip 64k
Technology node 90nm
Unit cell 2T-1R
Neural network type
Spiking
Learning
On-chip
Continuous
STDP mechanism
PCM neuromorphic core
World-first demonstration of sizable spiking neural network using NVM • PCM 2T-1R synaptic operation • On-chip spiking and learning neuron circuit • Fully asynchronous and parallel operation
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2T-1R synaptic unit cell
Invented 2T-1R synaptic unit cell to enable • massively parallel operation • asynchronous LIF and STDP operation
Area-efficient
• [2T-1R / 5-10 bits] vs [SRAM: 6T / 1 bit]
S. Kim et al., IEDM 2015
© 2017 IBM Corporation
Fully asynchronous and parallel operation
Fully asynchronous and parallel operation enabled by Low programming power of PCM cell Separated path for LIF and STDP using 2T-1R
unit cell
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2T-1R Synaptic unit cell
array
Fu
lly a
syn
ch
ron
ou
s o
utp
ut
Fully asynchronous input
Separated path for LIF and STDP Asynchronous and parallel
array operation
In LIF mode
In STDP mode
© 2017 IBM Corporation
NVM’s main role in neuromorphic processor
Heavily used computation in neural network Artificial neural network (Deep learning) : matrix-vector multiplication. Spiking neural network : multiply-and-accumulate.
Resistor network can perform matrix-vector multiplication and multiply-and-accumulate computation much faster in a massively parallel fashion. Conductances should be reliably stored in the resistive memory.
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G11
G21
G31
G12
G22
G32
G13
G23
G33
V1
V2
V3
I1 I2 I3
𝑰𝟏𝑰𝟐𝑰𝟑
=
𝑮𝟏𝟏𝑽𝟏 + 𝑮𝟐𝟏𝑽𝟐 + 𝑮𝟑𝟏𝑽𝟑𝑮𝟏𝟐𝑽𝟏 + 𝑮𝟐𝟐𝑽𝟐 + 𝑮𝟑𝟐𝑽𝟑𝑮𝟏𝟑𝑽𝟏 + 𝑮𝟐𝟑𝑽𝟐 + 𝑮𝟑𝟑𝑽𝟑
Matrix-vector multiplication using Kirchhoff’s law
Resistor network
Multiply-and-accumulate
𝑰𝒌𝒅𝒕 = (𝑮𝟏𝒌𝑽𝟏(𝒕) + 𝑮𝟐𝒌𝑽𝒌(𝒕) + 𝑮𝟑𝒌𝑽𝒌(𝒕))𝒅𝒕
© 2017 IBM Corporation
PCM reliability issues for neuromorphic applications
Resistance drift PCM cell conductance
representing synaptic weight changes over time.
1/f noise PCM cell is a dominant noise
source in the memory cell.
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No
rmalized
R
esis
tan
ce
10-6
Time (s)
10-3 100 103 106
)/()( 00 ttRtR
Drift model
𝜸: drift coefficient
RESET
SET
𝜸 = 𝟎. 𝟏 (typical drift coef.)
Factor of 2 increase every 3 decades in time
The signal-to-noise (𝑰 /𝝈) is estimated to be 19 at 22nm
node.
G. Close et al., IEDM 2010
G. Beneventi et al., IEEE EDL 2012
© 2017 IBM Corporation
PCM cell with metallic liner
Confined cell with metallic liner Enables reliability enhancement : Drift mitigation and noise reduction Cost effective integration
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GST
BE
Metallic
liner
Metallic liner
S. Kim et al., IEDM, 2013
M. BrightSky et al., IEDM, 2015
SangBum Kim et al., IEEE TED, 2016
W. Kim et al., IEDM, 2016
W. Koelmans et al., Nat. Comm., 2015
S. Kim et al., US Patent 9,059,404
S. Kim et al., US Patent 9,257,336
GST : Ge-Sb-Te
© 2017 IBM Corporation
Electrical conduction path with metallic liner
The metallic liner provides an alternative conductive path to the amorphous region.
The effective metallic liner resistance is modulated by the amorphous region thickness.
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metallic liner
With
metallic
liner
No
metallic
liner
SangBum Kim et al., IEDM, 2013
Fin
ite e
lem
en
t m
eth
od
sim
ula
tio
n
[Electrical resistance]
Crystalline GST < metallic liner < Amorphous GST
© 2017 IBM Corporation
Cost-effective integration scheme
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Cost-effective integration scheme No additional mask Small cell size (Metallic liner 2-8nm)
ALD metallic liner and GST deposition ALD deposition tool : ULVAC EntronTM-EX W300
1. Pore formation
2. Metallic liner +
GST deposition
3. Field GST removal
4. GST cap + anneal
5. GST cap removal
6. Top electrode formation
Void-free filling capability of ALD metallic liner and GST
(GexSbyTez)
S. Kim et al., IEDM, 2013 W. Kim et al., IEDM, 2016
© 2017 IBM Corporation
Requirement for metallic liner
Finding the right metallic liner is the most important. Material property requirement for metallic liner
1. Electrical resistivity (Semi-metallic) 2. Low noise and drift (Thermal stability) 3. Wetting capability with the phase change material (Low interface energy) 4. Conformal deposition (ALD deposition)
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ML :
log(
R)
log(t)
Resistance margin
log(
R)
log(t)
Metallic liner resistivity Too High
Too Low
© 2017 IBM Corporation
Drift mitigation with metallic liner
Drift is successfully mitigated with the metallic liner. 0.06 vs 0.01: 6 times smaller resistance drift coefficient is achieved. 0.01 : 7% increase over 3 decades in time Almost negligible
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No metallic liner With metallic liner
R4
R3
R2
R1
γ4=0.06
γ3=0.06
γ2=0.07
γ1=0.05
γ4=0.01
γ3=0.01
γ2=-0.01
γ1=0.01
R4
R3
R2
R1
)/()( 00 ttRtR
Drift model
Drift model
S. Kim et al., IEDM, 2013
© 2017 IBM Corporation
Noise reduction with metallic liner
Noise is successfully reduced with metallic liner. The PCM+ML(8nm) cell shows 4x smaller noise PSD than PCM without ML. But the noise is still much higher than a discrete resistor.
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f/1
dfIfSIf
fPSD
222 /)(/2
1
Signal to noise ratio can be
calculated from the
normalized PSD
No
rma
lize
d P
SD
(Po
we
r sp
ectr
al d
en
sity)
S. Kim et al., IEEE TED, 2015
© 2017 IBM Corporation
Conclusion
NVM neuromorphic chip with on-chip LIF and STDP Neuromorphic core for spike-based machine learning Non-volatile PCM as a synapse Brain-inspired : LIF, STDP, spiking neural network 64k (256-by-256) 2T-1R PCM synaptic cells Verified LIF and STDP operation at the array level
Resistance stabilizer for neuromorphic NVM Resistance needs to be stabilized to reliably store synaptic weights The confined PCM cell with metallic liner mitigates
• Resistance drift • Noise
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© 2017 IBM Corporation
Backup
21 9/11/2017