recosoc'11 montpellier, france implementation scenario for ...11sl… · montpellier, france...

ReCoSoC'11Montpellier, France

Implementation Scenario

for Teaching

Partial Reconfiguration

of FPGA

SUPELEC - Campus de Rennes - FranceSCEE – Signal, Communications et Electronique Embarquée

IETR – UMR CNRS 6164Institut d'Electronique et Télécommunications de Rennes

Pierre Leray, Amor Nafkha, Christophe MoySUPELEC/IETR

22 June 2011

Outline

• Lab experience in PR (for SDR)

• Student Project (on a video application)– application

– hardware platform

ReCoSoC - SUPELEC - 22 June 2011 2IETR - INSTITUT D’ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES


– design flow for PR

– reconfiguration management resources

– implementation results

• Conclusion

Outline









• Conclusion

Experiments on Partial Reconfiguration of FPGA

• Supélec SCEE team (Rennes)• Prototyping PR since 2003• Developed our own design flow

– Virtex devices

– based on Xilinx tools (beyond usual use)


– based on Xilinx tools (beyond usual use)

• Application domain: Software defined radio– SDR domain is extremely demanding in both

processing power and real-time flexibility

– PR has been foreseen for a while as an enabling technology for SDR

– Xilinx decided to develop this technology for SDR market

SDR-oriented publications on Partial Reconfiguration

1. Julien DELORME, Amor NAFKHA, Pierre LERAY, Christophe MOY, “New OPBHWICAP interface for real-time Partial reconfiguration of FPGA”International Conference on ReConFigurable Computing and FPGAs, ReConFig'09, Cancun, Mexico, 9-11 Dec 2009

2. Dominique NUSSBAUM, Karim KALFALLAH, Raymond KNOPP, Christophe MOY, Amor NAFKHA, Pierre LERAY, Julien DELORME, Jacques PALICOT, Jerome MARTIN, Fabien CLERMIDY, Bertrand MERCIER, Renaud PACALET

"Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques"DSD’09, 12th Euromicro Conference on Digital System Design, 27-29 Aug. 2009, Patras, Greece

3. Christophe MOY, Amor NAFKHA, Pierre LERAY, Julien DELORME, Jacques PALICOT, Dominique NUSSBAUM, Karim KALFALLAH, Hervé CALLEWWAERT, Jérôme MARTIN, Fabien CLERMIDY, Bertrand MERCIER, Renaud PACALET

"IDROMel: An Open Platform Addressing Advanced SDR Challenges"SDR Forum Technical Conference'08, 27-30 November 2008, Washington DC, USA

4. Julien DELORME, Jérôme MARTIN, Amor NAFKHA, Christophe MOY, Fabien CLERMIDY, Pierre LERAY, Jacques PALICOT

“A FPGA partial reconfiguration design approach for cognitive radio based on NoC architecture”NEWCAS'08, 22-25 juin 2008, Montréal Canada


5. Amor NAFKHA, Julien DELORME, Renaud SEGUIER, Christophe MOY, Jacques PALICOT

"A heterogeneous reconfigurable platform for cognitive radio systems"5th Karlsruhe Workshop on Software Radios, WSR'08, Karlsruhe, Allemagne, Mars 2008

6. Loïg GODARD, Hongzhi WANG, Christophe MOY, Pierre LERAY

"Common Operators Design on Dynamically Reconfigurable Hardware for SDR Systems"SDR Forum Technical Conference’07, Denver (USA), 5-9 November 2007

7. Jean-Philippe DELAHAYE, Pierre LERAY, Christophe MOY

"Designing a Reconfigurable Processing Datapath for SDR over Heterogeneous Reconfigurable Platforms"SDR Forum Technical Conference’07, Denver (USA), 5-9 November 2007

8. Jean-Philippe DELAHAYE, Jacques PALICOT, Christophe MOY, Pierre LERAY

“Partial Reconfiguration of FPGAs for Dynamical Reconfiguration of a Software Radio Platform”IST Mobile and Wireless Communications Summit'07, 1-5 July 2007, Budapest, Hungary

9. Jean-Philippe DELAHAYE, Pierre LERAY, Christophe MOY, Jacques PALICOT

"Managing Dynamic Partial Reconfiguration on Heterogeneous SDR Platforms"SDR Forum Technical Conference’05, Anaheim (USA), November 2005 - outstanding paper award

PR real-time implementation demos

• European project E2R-phase 2: – Sundance platform (DSP+FPGA+ADAC)

– RT modulation switching (DSP+FPGA PR)

– demos in 2005 and 2006

• French ANR project IDROMel:


• French ANR project IDROMel:– NoC context (based on CEA FAUST chip)

– integration in a NoC HW and protocol context

– real-time reconfiguration of ultra high data rate radio PHY modules (up to 100 Mbps) in 2007

�� PR: from research to education

Outline









• Conclusion

The student lab consists in implementing a flexible real-time video processing.

The video processing is changed on-the-fly by dynamically reconfiguring some FPGA processing.

Project description


A transcoding video processing is performed in a FPGA. The hardware platform is made of a Xilinx ML506 design kit, a host PC and a

screen for display.

� In the first case, the algorithm used to change a 128x128 pixels data stream to a

256x256 pixels data stream is the H-264 semi-pixel upscaling

F G H I J

K

E

j1= a – 5*b + 20*c1 + 20*d1 – 5*e + f

j = Clip (j1 + 512 >>10)

a1 = E – 5*F + 20*G +20*H –5*I + J

a = Clip (a1 + 16 >>5)

a

b

c

Two different types of transcoding


L

M

N

O

x1 = E – 5*K + 20*L +20*M –5*N + O

x = Clip (x1 + 16 >> 5)

c

d

e

f

P R

x j

H-264 semi-pixel upscaling schematic view

� The second context only consists in duplicating 4 times the input data stream.

²

FPGA Virtex5FPGA Virtex5FPGA Virtex5FPGA Virtex5----SX50SX50SX50SX50

XilinxXilinxXilinxXilinx ML506 ML506 ML506 ML506 boardboardboardboard

MicroBlaze

Configuration MemoryConfiguration MemoryConfiguration MemoryConfiguration Memory

Reconfiguration ManagerReconfiguration ManagerReconfiguration ManagerReconfiguration Manager

VideoVideoVideoVideo ProcessingProcessingProcessingProcessing

ICAPController

self reconfiguringapproach

The host PC plays three roles:- development platform,

- video server,

- highest level reconfiguration manager.load bitstreams into configuration

memory at initialization,send reconfiguration orders for on-the-fly

Hardware reconfigurable

platform architecture


Video_128_inVideo_128_inVideo_128_inVideo_128_inReconfigurableReconfigurableReconfigurableReconfigurable

ProcessingProcessingProcessingProcessing UnitUnitUnitUnit

RGB RGB RGB RGB VideoVideoVideoVideo sourcesourcesourcesource

Video_256_outVideo_256_outVideo_256_outVideo_256_out

VideoVideoVideoVideoCoderCoderCoderCoder

DVIDVIDVIDVIControllerControllerControllerController

bitstreamsbitstreamsbitstreamsbitstreams

send reconfiguration orders for on-the-fly video processing adaptation.

The reconfigurable processing unit (PU) performs the video processing

The reconfiguration Manager consists

of a MicroBlaze softcore to manage the

PU reconfiguration , and a hardcore ICAP

controller to perform the dynamic PU

reconfiguration

ICAP ControllerICAP ControllerICAP ControllerICAP Controller

MicroBlazeMicroBlazeMicroBlazeMicroBlaze platformplatformplatformplatform

MicroBlaze

CPU

PLBPLBPLBPLB Read Bitstream attributesin Configuration Table

Send Bitstream attributesto ICAP Controller

Soft driverSoft driverSoft driverSoft driver

Wait forReconfiguration order &Config busy FALSE

The MicroBlaze softcore

perform the bitstream

loading from the

memory to the ICAP

interface

The ICAP Controller

Resources supporting reconfiguration management


ICAP ControllerICAP ControllerICAP ControllerICAP Controller

Length register

Address register

Controller

ConfigurationConfigurationConfigurationConfigurationMemoryMemoryMemoryMemory

ICAPICAPICAPICAPPrimitivePrimitivePrimitivePrimitive

32323232

32323232

400 MB/s400 MB/s400 MB/s400 MB/s

Wait for Length = 0

Direct Transfert Memory to ICAPAddress ++ ; Length --

Config busy TRUE

Length == 0

Config busy FALSE

Hard driverHard driverHard driverHard driverThe ICAP Controller

hardcore, with a DMA

(Direct Memory Access)

architecture, realize

interface between off-chip

memory and ICAP

primitive, which permits to

reach the theoretical

transfer bandwidth (400

MB/s)

Top Module Static Module- MicroBlaze platform- ICAP Controller- Video Interfaces

Reconfigurable Module PU

Configuration A Configuration B

SynthesisSynthesisSynthesisSynthesis

NetlistsNetlistsNetlistsNetlists

Design DescriptionDesign DescriptionDesign DescriptionDesign Description

FloorplanningFloorplanningFloorplanningFloorplanning

Draw Reconfigurable Partition

Partial reconfiguration Design flow steps


Specify any configuration

FloorplanFloorplanFloorplanFloorplan

Place/Route/Place/Route/Place/Route/Place/Route/GenerateGenerateGenerateGenerate BitstreamsBitstreamsBitstreamsBitstreams

Run implementation of Static and Reconfigurable Modules for each configuration

BitstreamsBitstreamsBitstreamsBitstreams

Draw Reconfigurable Partition

The design kit board comprises one Xilinx Virtex5-SX50T FPGA clocked at 100 MHz

32640 slices,132 Blocks RAM of 36kb (4752 kb),

288 DSP blocks,Global bistream size: 2.5 MBytes.

Upscaling reconfigurable operator

Implementation results


Upscaling PU is clocked at 200 MHz for a performance of 200 Mpixels/s.

Its complexity is 1241 slices

The corresponding partial bitstream size is 57 kBytes

Upscaling reconfigurable operator

Reconfiguration time : bitstream size / (400 MB/s) + overhead ( 7.5 µs) = 150 µs

Outline









• Conclusion

Conclusion

• Student lab based on research activities and results

• PR is very promizing, mixing HW processing power and SW high flexibility


power and SW high flexibility

• PR studied in the SDR field but also interesting for any other dynamically flexible embedded system (video)

• Sorry to miss the event

• Many thanks to Guy GOGNIAT for presenting


• Many thanks to Guy GOGNIAT for presenting

• if you want more information:– [email protected]

recosoc'11 montpellier, france implementation scenario for ...11sl… · montpellier, france...

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