record programs

7/26/2019 Record Programs

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PROGRAM FOR HALF ADDER

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity halfdder is

Port ( a,b : in STD_LOGIC;

Sum, carry : out STD_LOGIC);

end halfdder;

architecture Behavioral of halfdder is

begin

sum


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EX NO: 1 HALF ADDER AND FULL ADDER

DATE:

AIM:

To Design a Half adder and Full adder using VHDL programming in ModelSim.

COMPONENTS REQUIRED:

ModelSim tool

ALGORITHM:

STEP1 : Start the program by including required header files.

STEP2 : Write the Architecture for processing inputs a, b&cin and outputs sum, carry

According to the half adder and full adder function

STEP3 : Simulate it using ModelSim

STEP 4 : Verify the Output In The Waveform.


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PROGRAM FOR FULL ADDER

library IEEE;


entity fulladder is

Port ( a ,b,c: in STD_LOGIC;

Sum, carry : out STD_LOGIC);

end fulladder;

architecture Behavioral of fulladder is

begin

sum


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RESULT:

The Half Adder and Full Adder circuits designed using VHDL

Programming in ModelSim and verified its output successfully.


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PROGRAM FOR HALF SUBTRACTOR:

library IEEE;


entity hs is

Port ( a,b : in STD_LOGIC;

diff ,br: out STD_LOGIC);

end hs;

architecture Behavioral of hs is

begin

diff


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EX NO: 2 HALF SUBTRACTOR AND FULL SUBTRACTOR

DATE:

AIM:

To Design a Half Subtractor and Full Subtractor using VHDL programming in ModelSim


ModelSim tool

ALGORITHM:


STEP2 : Write the Architecture for processing inputs a, b&c and d, br

According to the half Subtractor and full Subtractor function




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PROGRAM FOR FULL SUBTRACTOR

library IEEE;


entity fs is

Port (a, b, c : in STD_LOGIC;


end fs;

architecture Behavioral of fs is

begin

diff


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RESULT:

The Half Subtractor and Full Subtractor circuits designed using VHDL



10/37

PROGRAM FOR 8X1 MULTIPLEXER:

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity mux is

port(

a : in STD_LOGIC_VECTOR(7 downto 0);

s : in STD_LOGIC_VECTOR(2 downto 0);

y : out STD_LOGIC

);

end mux;

architecture mux of mux is

begin

process(s,a)

begin

case s is

when "000"=> y y y y y y y ynull;

end case;

end process;

end mux;


11/37

EX NO: 3 MULTIPLEXER AND DEMULTIPLEXER

DATE:

AIM:

To write a program to perform multiplexer and Demultiplexer using VHDL

programming.


ModelSim tool

ALGORITHM:


STEP2 : Write the Architecture for processing inputs according to the multiplexer

and Demultiplexer function




12/37

PROGRAM FOR 1X8 DEMULTIPLEXER

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use ieee.std_logic_unsigned.all;

entity demux is

port(

a : in BIT;

s : in BIT_VECTOR(2 downto 0);

y : out BIT_VECTOR(7 downto 0):="00000000"

);

end demux;

architecture demux of demux is

begin

process(s,a)

begin

case s is

when "000"=> y(0) y(1) y(2) y(3) y(4) y(5) y(6) y(7)null;

end case;

end process;

end demux;


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Output for 8x1 multiplexer

Output for 1x8 Demultiplexer


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RESULT

The Multiplexer and Demultiplexer circuits designed using VHDL



16/37

PROGRAM FOR DECODER:

library IEEE;


entity decoder is

Port ( a,b: in STD_LOGIC;

x ,y, z,s: out STD_LOGIC );

end decoder;

architecture Behavioral of decoder is

begin x


17/37

EX NO: 4 DECODER

DATE:

AIM:

To write a program to perform decoder using VHDL programming.


ModelSim tool

ALGORITHM:


STEP2 : Write the Architecture for processing inputs according to the Decoder function



RESULT

The Decoder circuit designed using VHDL Programming in ModelSim and verified its

output successfully


18/37

PROGRAM FOR PARALLEL ADDER

entity pAdd is

Port ( A,B : in STD_LOGIC_VECTOR(3 DOWNTO 0);

S: out STD_LOGIC_VECTOR(3 DOWNTO 0);

CA : out STD_LOGIC);

end pAdd;

architecture Behavioral of pAdd is

component FA

port( a,b,c : in STD_LOGIC;

s ,ca: out STD_LOGIC);

end component;

signal X: STD_LOGIC :=0;signal c1,c2,c3 : STD_LOGIC;

begin

L0: FA portmap (a =>A(0),b=> B(0),c => X, s=>S(0), ca=> c1);

L1: FA portmap (a =>A(1),b=> B(1),c => c1, s=>S(1), ca=> c2);

L2: FA portmap (a =>A(2),b=> B(2),c => c2, s=>S(2), ca=> c3);

L3: FA portmap (a =>A(3),b=> B(3),c => c3, s=>S(3), ca=> CA);

end pAdd;

OUTPUT:


19/37

EX NO: 5 PARALLEL ADDER

DATE:

AIM:

To write a program to perform 4-bit Parallel binary Adder using VHDL programming.


ModelSim tool

ALGORITHM:


STEP2 : Write the Architecture for processing inputs according to the

parallel adder function



RESULT

The 4-bit parallel adder circuit designed using VHDL Programming in ModelSim and

verified its output successfully


20/37

PROGRAM FOR PARALLEL SUBTRACTOR

entity psub is

Port ( A,B : in BIT_VECTOR(0 TO 3);

D: out BIT_VECTOR(0 TO 3);

BR : out BIT);

end psub;

architecture psub of psub is

component FS

port( a,b,c : in BIT;

d,br: out BIT);

end component;

signal X: BIT := '0';signal c1,c2,c3 : BIT;

beginL0: FS port map (a =>A(0),b => B(0),c =>X, d=>D(0), br=> c1);

L1: FS port map (a =>A(1),b => B(1),c =>c1, d=>D(1), br=> c2);

L2: FS port map (a =>A(2),b => B(2),c =>c2, d=>D(2), br=> c3);

L3: FS port map (a =>A(3),b => B(3),c =>c3, d=>D(3), br=> BR);

end psub;

OUTPUT:


21/37

EX NO: 6 PARALLEL SUBTRACTOR

DATE:

AIM:

To write a program to perform 4-bit Parallel binary Subtractor using VHDL

programming.


ModelSim tool

ALGORITHM:


STEP2 : Write the Architecture for processing inputs according to the

parallel Subtractor function



RESULT

The 4-bit parallel Subtractor circuit designed using VHDL Programming in ModelSim

and verified its output successfully


22/37

/* FLASH THE OUTPUT WITH DELAY*/

#include

void delay()

{

unsigned int i,j;

for(i=0;i


23/37

EX NO: 7 FLASH THE OUTPUT WITH DELAY

DATE:

AIM:

To write a C program to perform flash the output with delay operation using keil

version.


keil version.tool

ALGORITHM:


STEP2 : write the value 0x00 at port 2

STEP3 : write the value 0xff at port 2

STEP 4 : Verify the Output.

RESULT

The flashing of the output with delay function using keil c tool was performed and



24/37

/*ROTATE RIGHT */

#include

#include

void main()

{

char a,b ; // intialisise the variables

a=0xA5;

P0=a;

b=cror_(a,1); //rotate the data with one bit right shift

P1=b; // store the result

}

OUTPUT :

INPUT DATA=0XA5 OUPUT DATA=0XD2


25/37

EX NO: 7 ROTATE RIGHT WITH DELAY

DATE:

AIM:

To write a C program to perform rotate right the input with delay operation using keil

version.


keil version.tool

ALGORITHM:


STEP2 : write the input value at port 0

STEP3 : perform the rotate right operation


RESULT

The rotate right of the input with delay function using keil c tool was performed and



26/37

/*ROTATE RIGHT */

#include

#include

void main()

{

char a,b ; // intialisise the variables

a=0xA5;

P0=a;

b=crol_(a,1); //rotate the data with one bit left shift

P1=b; // store the result

}

OUTPUT :

INPUT DATA=0XA5 OUPUT DATA=0X4B


27/37

EX NO: 9 ROTATE LEFT WITH DELAY

DATE:

AIM:

To write a C program to perform rotate left the input with delay operation using keil

version.


keil version.tool

ALGORITHM:


STEP2 : write the input value at port 0

STEP3 : perform the rotate left operation


RESULT

The rotate left of the input with delay function using keil c tool was performed and



28/37


29/37

EX NO: 9 CODE LOCKING

DATE:

AIM:

To write a C program to perform code locking operation using keil version.


keil version.tool

ALGORITHM:


STEP2 : get the input code

STEP3 : validate the input code and produce the corresponding result



30/37

CODE LOCKING

#include

#include

#define XTAL 11059200 // CPU Oscillator Frequency

#define baudrate 9600 // 9600 bps communication baudrate

#define OLEN 8 // size of serial transmission buffer

unsigned char ostart; // transmission buffer start index

unsigned char oend; // transmission buffer end index

char idata outbuf[OLEN]; // storage for transmission buffer

#define ILEN 8 // size of serial receiving buffer

unsigned char istart; // receiving buffer start index

unsigned char iend; // receiving buffer end index

char idata inbuf[ILEN]; // storage for receiving buffer

bit sendfull; // flag: marks transmit buffer full

bit sendactive; // flag: marks transmitter active

/* * Serial Interrupt Service Routine */

static void com_isr (void) interrupt 4 using 1 {

char c;

/*----- Received data interrupt. ----------------------------------------*/

if (RI) {

c = SBUF; // read character

RI = 0; // clear interrupt request flag

if (istart + ILEN != iend) {

inbuf[iend++ & (ILEN-1)] = c; // but character into buffer

}


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}

/*------ Transmitted data interrupt. ------------------------------------*/

if (TI != 0) {

TI = 0; // clear interrupt request flag

if (ostart != oend) { // if characters in buffer and

SBUF = outbuf[ostart++ & (OLEN-1)]; // transmit character

sendfull = 0; // clear 'sendfull' flag

}

else { // if all characters transmitted

sendactive = 0; // clear 'sendactive'

}

}

}

/*

* Function to initialize the serial port and the UART baudrate.

*/

void com_initialize (void) {

istart = 0; // empty transmit buffers

iend = 0;

ostart = 0; // empty transmit buffers

oend = 0;

sendactive = 0; // transmitter is not active

sendfull = 0; // clear 'sendfull' flag

// Configure timer 1 as a baud rate generator

PCON |= 0x80; // 0x80=SMOD: set serial baudrate doubler

TMOD |= 0x20; // put timer 1 into MODE 2

TH1 = (unsigned char) (256 - (XTAL / (16L * 12L * baudrate)));

TR1 = 1; // start timer 1


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SCON = 0x50; // serial port MODE 1, enable serial receiver

ES = 1; // enable serial interrupts

}

void putbuf (char c) {

if (!sendfull) { // transmit only if buffer not full

if (!sendactive) { // if transmitter not active:

sendactive = 1; // transfer first character direct

SBUF = c; // to SBUF to start transmission

}

else {

ES = 0; // disable serial interrupts during buffer

update

outbuf[oend++ & (OLEN-1)] = c; // put char to transmission buffer

if (((oend ^ ostart) & (OLEN-1)) == 0) {

sendfull = 1;

} // set flag if buffer is full

ES = 1; // enable serial interrupts again

}

}

}

char putchar (char c) {

if (c == '\n') { // expand new line character:

while (sendfull); // wait until there is space in buffer

putbuf (0x0D); // send CR before LF for

}

while (sendfull); // wait until there is space in buffer

putbuf (c); // place character into buffer

return (c);


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}

char _getkey (void) {

char c;

while (iend == istart) {

; // wait until there are characters

}

ES = 0; // disable serial interrupts during buffer

update

c = inbuf[istart++ & (ILEN-1)];

ES = 1; // enable serial interrupts again

return (c);

}

/* Main C function that start the interrupt-driven serial I/O. */

void main (void) {

EA = 1; /* enable global interrupts */

com_initialize (); /* initialize interrupt driven serial I/O */

while (1) {

char c;

c = getchar ();

if (c=='a')

{

printf ("\n code correct \n"); }

else

{

printf ("\n code not correct and locked \n");

}

}

}


34/37

OUT PUT

RESULT

The code locking operation using keil c tool was performed and verified its output

successfully


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PROGRAM FOR FULL SUBTRACTOR

library IEEE;


entity fs is

Port (a, b, c : in STD_LOGIC;


end fs;

architecture Behavioral of fs is

begin

diff


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EX NO: 11 FULL SUBTRACTOR

DATE:

AIM:

To Design a Full Subtractor using VHDL programming in Xilinx ISE


Xilinx ISE ,FPGA kit

ALGORITHM:


STEP2 : Write the Architecture for processing inputs a, b&c and d, br

According to the half Subtractor and full Subtractor function

STEP3 : synthesize it with Spartran 3Ekit

STEP 4 : verify the output

RESULT

The Full Subtractor circuit has been performed by VHDL programming and

synthesized it with Spartran 3E kit and verified its output Successfully.


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