reconfigurable shift switching parallel...

VLSI DESIGN1999, Vol. 9, No. 1, pp. 83-90Reprints available directly from the publisherPhotocopying permitted by license only

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Reconfigurable Shift Switching Parallel ComparatorsR. LIN and S. OLARIUb’*

Department of Computer Science, SUNY at Geneseo, Geneseo, NY 14454;b Department of Computer Science, OM Dominion University, Norfolk, Va 23529

(Received 5 May 1997)

We present novel asynchronous VLSI comparator schemes which are based on recentlyproposed, reconfigurable shift switch logic and the traditional (precharged) CMOSdomino logic. The schemes always produce a semaphore as a by-product of the processto indicate the end of domino process, which requires no additional delay and a minimalnumber of additional devices. For a large percentage of inputs the computations aremuch faster than traditional synchronous comparators due to the full utilization of theinherent speed of the circuits. Also the schemes are simple, area compact and stable.

Keywords: Parallel architectures, reconfigurable architectures, digital signal processing, VLSIdesign, domino logic, computer arithmetic

1. INTRODUCTION

Recently, shift switch logic (defined by statesignals and shift switches, refer to [6-9] and seebelow) has been proposed. It is shown that the newlogic method is an efficient alternative to thetraditional switching logic (i.e., binary signals andlogic gates) for the designs of a number ofarithmetic devices including parallel counters,multipliers, and fast adders [5-10].

In this paper we propose novel VLSI asynchro-nous comparator schemes based on shift switchlogic and traditional (precharged) CMOS dominologic [2, 4, 13, 14], which we call shift 1switchingwith domino logic. The technique allows to

broadcast state signals (on short reconfigurablebuses [3, 7, 10] containing cascaded shift switches)in a form of a chain of pulling-down and/orpulling-up the precharged switches. It possessesthe following attractive features: (1) The compara-tors produce two-bit output xy which representsthe comparison result for two inputs a and b, suchthat xy 01, 10, 11 indicating a > b, a < b, a brespectively, and if the result is not ready xy 00.The comparators also produce (in parallel) a bitsemaphore to indicate the end of each dominopropagation, and the circuits can run asynchro-nously without high frequency clocking schemes;(2) The comparison algorithms consist of twophases, precharge and evaluation (with single

*Corresponding author, e-mail: [email protected]

83

84 R. LIN AND S. OLARIU

control signal called P/E). The precharge startswhen PIE 0 and is done in parallel (in less than afull adder delay). The evaluation begins when P/E and it consists of several domino dischar-ging processes (2 for 32-bit); (3) It is faster thantraditional designs [11-14], since the full inherentspeed of the computation can be utilized; and (4)Due to that a comparator delay can be determinedby individual input data instead of the worst-caseinput, for a large percentage of inputs, thecomputation is significantly faster than the worstcase delay, also the comparator is not delaysensitive. Moreover, the proposed method isapplicable to other asynchronous arithmetic cir-cuits, such as fast adders [8].The remainder of the paper is organized as

follows: Section 2 defines state signals and GPswitches. Section 3 presents a 7-bit comparator.Section 4 presents a 32-bit comparator.

if u 0 (1). A state signal may be denoted by I(w)regardless of type, or I (value only).

DEFINITION 2 A degenerate state signal with value! (0 _< I_< w-l) is state signal ! with the 0-th bitremoved, thus represented by bl, bz,...,bw-1.(Fig. 2), and its value is 0 if there is no unique bitin the sequence, otherwise it is equal to thecorresponding state signal (with bit 0 added). Itcan be seen as a special state signal, and is said n-(p-) type denoted by l(w,)(I(),)ifu- 0 (1).

DEFINITION 3 (shift switch in general) Givenfunction F(X, Y) (U, V), or F(X, Y) U, whereX, Y, U and/or V are (small) state signals, a pass-transistor (or transmission gate) based digital filterwhich implements function F by shifting (in someway) the input state signals to obtains the outputsis called a shift switch of function F.

In this paper we consider only a specific type ofshift switches called GP switch.

2. STATE SIGNALS AND SHIFT SWITCHES

Shift switch logic is defined by state signals whichrepresent small integers and shift switches whichare basic logic units to operate the state signals(refer to [6-9]). To be self-contained we show therelevant definitions below.

DEFINITION A state signal with value I(0 < I_< w-1; w >_ 2) is represented by bit sequencebo, bl,..., bw-i (here we assume the order is eitherright to left or top-down) with the unique bit u

(either 0 or 1) in the/-th position (see Fig. 1). Astate signal is said n-(p-) type denoted by l(w) (I())

DEFINITION 4 A shift switch which implementsfunction GP(X, Y) U, such that U Y if Y > 0and U X if Y= O, is called GP (generate/propagate) shift switch. Figure 3 shows anexample of such a switch.

DEFINITION 5 If a GP shift switch has anadditional input called PIE (precharge/evalua-tion), such that, P/E, X, Y and U are defined byTable I (or II), it is called GP1 (or GP2) switch.

The examples of GP1 and GP2 are depicted inFigures 4(a) and 4(b). They are assumed to workin two phases (precharge and evaluation). Theinput and output values are represented by state

o ---- ---- -- I-------> o---> I I------- I---> o ----> I--).---> ---- I-- o-->

0(4) (r 0(4) or O) (4) 2(4) 3(4)

001 01 0 oo

0(’1 I(’} 2(’)

I---) 0--40---> I--->

0()

0--1-,-.-)

0(20

FIGURE Some state signals.

RECONFIGURABLE ARCHITECTURES 85

<-- <-- <-0 000

X()- Y(_,3_)" Z((_)-

FIGURE 2 Some degenerate state signals (X 0, Y= 1,Z=2, R=0).

u(),i.e. GP(X,Y) 0

y() 01 0 (=I) 001 (=0)

FIGURE 3 A GP shift switch and sample inputs andoutputs.

precharge/evaluation(Ply)

TABLE Shift switch GP1

input

X Y

output

0 0(3 0(:), 0(3(precharge) i.e. 11 000 11

x r//, (x, r)/,(evaluation)

precharge/evaluation(Ply)

TABLE II Shift switch GP2

input

X Y

output

0 0(4 %), 0(4(precharge) i.e. 111 000 111

X(_3> YO)’ GP(X, Y)(3_)’(evaluation)

signals. During the precharge phase (PIE 0),both switches have the same corresponding input/output values (all are 0) and are represented by thestate signals. During the evaluation phase (P!E 1), both switches produce horizontal outputU GP(X, Y), but represented by state signals(GP1) and degenerate state signals (GP2) respec-tively.The significance of using state signals and shift

switches lies in the fact that some basic arithmeticand logic operations (such as adding two smallintegers, and the evaluation of logic functions likeGP) can be done by shifting one state signal X in away controlled by the other state signal Y. Theoperations can be efficiently performed by shiftswitches, essentially letting X pass through a smallnumber of pass-transistors (or trans-gates) that are

preset by Y. Also since both shifting and controlsignals are state signals, we can use the shift-out ofa switch to control another switch, thus we mayorganize an efficient network of shift switches (orenhanced reconfigurable buses) for a desiredarithmetic computation.

3. THE 7-BIT COMPARATOR:A PRECHARGED CMOS SCHEME

A linear array of the proposed GP switches, eachassociated with a CMOS domino logic unit, calledcomp unit, can implement a VLSI-efficient small-size comparator, such as a 7-bit comparator.Figures 5 and 6 show the evaluation phases of acomp unit for bit j (for <j < 6), and a comp unitfor bit 0 respectively. The precharge and evalua-tion are two phases of the computation on each ofthese logic units. During the precharge phase thecontrol signal PIE (precharge/evaluation, whichmay be received from a previous asynchronousdevice) is set to 0. It is easy to verify that a compunit is precharged as follows: gly (generate-l), g0y(generate-0), and py (propagate) are all low (for<j < 6); two output bits (gl0, g00) of comp unit 0

are all high. When PIE is set to 1, the evaluationphase begins. The logic units are discharged asfollows: For comp units j (1 <j < 6): glj (or g0y) isdischarged to high if aj > bj (or by> ay); pj isdischarged to high if aj by; note that state signalcb(j)o (gl,gO,p) is called (the j-th) comp-bitstate signal. For comp unit 0, gl0 (or g00) isdischarged to low if a0 < b0 (or b0 < a0).

Figure 7 shows the 7-bit comparator scheme. Itconsists of six GP1 switches connected with sevencomp units (including comp unit 0). When signalPIE is set to 0 (PIE is set to 1), all GP1 switchesand comp units are precharged as described above.The precharge phase is as the follows: eachpropagation gate in GP1 is off and will be keptoff if the corresponding comp unit bit evaluationsignal cb(j)o (glj, gOj,pj) (0, 0, 1)(1 <j < 6).This ensures a stable discharge during the evalua-tion phase, i.e., the domino discharging can


GP2

xsgmbol

GP(X,Y)(_) X

evalua’tion

(a) precharge (b) evaluation

FIGURE 4 Precharged CMOS schematics of GP1 and GP2. Note that PIE is the enable signal with values 0 and for prechargeand evaluation respectively.

g1 T q gO P

0 0 0

omp

P/E ’ ’]’ ?don’ oare

2 i.e.(glj gOj Pj)=(100)

i.e.(gl gOj Pj)=(010)

0 i.e. (gl gOj PJ)=(OOI)

if aj bj

if bj aj

if bj= aj

FIGURE 5 Comp unit j(1 <j < 6).

glo gOo

ao bo a- b"o

i.e. (gl gOo)= (I 0if

i.e. gl gO (01

if bo>

i.e. (gl gO o) (0 O)if bo=

(a) precharge (b) evaluation

FIGURE 6 Comp unit 0.


FIGURE 7 BlockA(0), a 7-bit comparator (evaluation phase). (a) precharge phase (note: the values of inputs are "don’t care"); (b)evaluation phase.

correctly propagate from the comp units to GP1switches and then generate comp group output

cg(O)(3_), (or cgO) for blockA(0).The evaluation phase is as follows: First, the

discharge of each comp unitj generates evaluationoutput signal cb(j)()= (glj, gOj,pj) (see Fig. 5)which then discharges the corresponding switchGP1 if cb(j)() O, otherwise it turns on thecorresponding propagation gates of the GP1 forpropagation of the comparison result of lower bits.The bus (with GPls) is then partitioned (by thepropagation gates), and the worst case of compevaluation signal propagation (or discharging) willstart from gate A and/or B passing all 6 GPls toproduce cgO. The worst case delay of thecomparator is Tc (time to discharge a compunit) + 7T6p (time to discharge seven cascadedpass-transistors including A or B)+ Tinv (aninverter delay, low to high). The best case delayof the comparator is Tc + Tae +Tinv.

4. THE 32-BIT SCHEME: SHIFT SWITCHWITH DOMINO LOGIC

A 32-bit comparator can be constructed by severalGP switch blocks and organized in two levels (seeFig. 8). The first level consists of six blocks:-blockA(0), i.e., the 7-bit comparator and blockA(i)(for < < 5), The second level is a single blocktermed blockB.

Figure 9 shows blockA(/) (for 1<i<5). Itcontains five cascaded GP2 shift switches and fivecomp units. It produces state signal cg(i)= (ggl,ggO, pg) which represents the group’s comparisonresult, i.e., values 2, 1, 0 representing the relation-ship between the corresponding bit segments of aand b for >, < and =, and is called (the i-th)comp-group output (state) signal. In other words,ggl 1 (or ggO 1, or pg 1) if the group’s bitsegment of a is greater than (or less than, or equalto) the bit segment of b. The worst case and thebest case delays of the first level are dominated bythe longest blockA(0), i.e., T + 7Tae + Tiny andTc + Tae +Tinv respectively. Figure 10 shows thesecond level block, i.e., blockB. It is similar toblockA(0), except the follows:

(1) it has five cascaded GP1 switches and its fivevertical inputs are comp-group output signalsfrom blockA(/) (for <i< 5), and its horizon-tal input (for evaluation) is the degeneratecomp-group output cgO(3_), of blockA(0);

(2) its two outputs are a 2-bit degenerate comp all-groups output signal cg_all(3_), and a sema-

phore. The 2-bit signal cg_all(3), which is thefinal comparison result, has a Talue either 0, or1, or 2, i.e., 11, 10 or 01, which representsa b, a < b and a > b respectively. If cg_all(3),is 00 the semaphore is 0, meaning the resulf isnot ready, otherwise the semaphore is 1,meaning the result is ready;


semaphore 0 (,,,

(a) precharge phase (note: the values of inputs are "don’t care")

semaphore

eg5 ()

1- blookA(5) H blookA(4)

P/E ’1’ 1a27-31, b27-31 a22-26, b22- 26 a17-21, b17-21 aO-6, bO-6 a12-16,b 12-16 a7-11, b7-11

(b) evaluation phase

FIGURE 8 The 32-bit comparator.

sgmbol

P/E-)I,, blookk(i) I<i.5, j=5(i-1) p P/E

WE

FIGURE 9 BlockA(/) (for < < 5; evaluation phase is shown).

FIGURE 10 BlockB (evaluation phase is shown).

The output bits and the semaphore are pro-duced at about the same time. This is the uniquefeature of our scheme. More significantly, the best

case delay of the comparator can be specified as 3times of a cascaded pass-transistors delay plus twotimes of an inverter delay (or 3 TGp + 2Tiny), the


TABLE III Area Comparisons of comparators

Comparators device count (number of transistors)level level 2 total area per

area output bit

asynchronous 662 42 704 352synchronous 417 19 436 436

worst and the average case delays of the compara-tor can be specified as 13Tap + 2Tinv and

6Tae + 2Tiny respectively. This implies that theasynchronous scheme can be adapted to signifi-cantly reduce average case delay of a comparator(by automatically choosing single or doubleinstruction cycles for the computation). This willlead to an expected 60% faster for 50% inputs, or

30% faster for other 50% inputs (by a simulationprogram).Note that if a synchronous comparator is

preferred we can modify the first level of GPswitches to implement only gl and p (i.e., removinggO circuit), thus eight transistors per input bit maybe reduced. However, such a synchronous com-

parator can provide only one output bit indicatingeither a > b or a < b (or alternatively a >_ b or aa < b). In order to provide all three comparisonresults two such comparators may be required.We can count the number of devices (in terms of

pass-transistors) for both asynchronous and syn-chronous comparators as listed in Table III. It isclear that the synchronous schemes have about30% savings in area, however, asynchronousschemes are more compact for area per output bit.

Acknowledgements

The work was supported, in part, by NationalScience Foundation under grants MIP-9630870 andCCR-9522093 and ONR grant N00014-95-1-0779.

References

[1] Hwang, H. (1979). Computer Arithmetic. Principles,Architectures and Designs, New York: Wiley.

[2] Hwang, I. S. and Fischer, A. L. (1989). Ultrafast compact32-bit CMOS adders in multi-output domino logic, IEEEJ. Solid-State Circ., 24(2), 358-369.

[3] Jang, J., Park, H. and Prasanna, V. K. (1994). A bit modelof the reconfigurable mesh, Proc. of the Workshop onReconfigurable Architectures, the 8th International ParallelProcessing Symposium, Cancun, Maxico.

[4] Krambeck, R. H., Lee, C. M. and Law, H. S. (1982).High-Speed Compact Circuits with CMOS, IEEE Journalof Solid-State Circuits, SC-17(3).

[5] Lin, R., Shift switching with domino logic: asynchronousVLSI comparator schemes, to appear in Proc. of The lOthInternation Conference on VLSI Design, January, 1997,Hyderabad, India.

[6] Lin, R. Shift switching and novel arithmetic schemes, In:Proc. of29th Asilomar Conference on Signals, Systems andComputers, Pacific Grove, CA, Nov. 1995. pp. 580-585.

[7] Lin, R., A fast 64 x 64 multiplier without a completematrix reduction on short shift switching buses, In: Proc.of 1995 International Conference on High PerformanceComputing, Dec. 1995, New Delhi, India.

[8] Lin, R. (1996). A fast reconfigurable-bus-based 32-bitCLA adder scheme with domino logic, Proc. of theWorkshop on Reconfigurable Architectures, the lOth Inter-national Parallel Processing Symposium, Hawaii.

[9] Lin, R. and Olariu, S. (1996). A Reconfigurable NetworkArchitecture For Parallel Prefix Counting, Proc. of theWorkshop on Reconfigurable Architectures, the lOth Inter-national Parallel Processing Symposium, Hawaii.

[10] Lin, R. and Olariu, S. (1995). Reconfigurable buses withshift switching-concepts and applications, In: IEEETransactions on Parallel and Distributed Systems, 6(1),93 102.

[11] LSI logic 1.0 micron cell-based products data book, LSIlogic corporation, Milpitas, Califoria, 1991.

[12] Motorola CMOS Logic Data book, Motorola Inc., 1991.[13] Mukherjee, A. (1986). Introduction to nMOS & CMOS

VLS! System Design, Prentice-Hall, NJ.[14] Weste, N. and Eshraghian, K. (1993). PRINCIPLES OF

CMOS VLSI DESIGN, Addison-Wesley Pub. Company.

Authors Biographies

Stephan Olariu received the M.Sc. and Ph.D.degrees in computer science from McGill Uni-versity, Montreal in 1983 and 1986, respectively.In 1986 he joined the Computer Science Depart-ment at Old Dominion University.

Dr. Olariu has published extensively in variousjournals and conference proceedings. His researchinterests include parallel algorithms, parallel algo-rithms, image processing and machine vision,computational graph theory, computational geo-metry, and mobile computing.Rong Lin received the B.S. in mathematics from

Peking university (China), M.S. in ComputerScience from Beijing Polytechnical University(China) and Ph.D. in computer science from Old


Dominion University in 1989. He is currently anassociate professor with the Department of Com-puter Science of SUNY at Geneseo. His current

research interests include VLSI arithmetic, parallelarchitectures and algorithms, digital signal proces-sing, and reconfigurable architectures.

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