reconfigurable processing module (rpm)

1 Somervill 125/MAPLD'05

RSC

Reconfigurable Processing Module(RPM)

Kevin Somervill1 ([email protected])

Dr. Robert Hodson1 ([email protected])

Dr. John Williams2 ([email protected])

Dr. Robert Jones3 ([email protected])

1 NASA Langley Research Center2 The University of Queensland, Australia

3 ASRC Aerospace Corp.

2

RSC125/MAPLD'05 Somervill

Presentation Topics

• RSC Platform Architectural Overview• RPM Architecture Block Diagram• Interface On-Chip Network Diagram• Example Applications

– Soft processor Based– Custom Hardware

• Major Components• System Modeling• Embedded Computing (MicroblazeTM)• Development Challenges and Issues• Current Status

3


RSC Platform Architectural Overview

• Collection of one or more modular stacks of computing elements

• RPM is core reconfigurable component hosting reconfigurable FPGA fabric

4


RPM Architecture Block Diagram

Reconfigurable Application FPGA

(Xilinx 4VFX60)

Interface FPGA(Actel AX2000)

On Chip Bus

SLiP I/F

Mem

or

y I

/F

NIC

Configuration Manager

Bus Arbiter

Configuration Memory

Seri

al I/

F Serial XCVR2.5Gbps

SM

AP

SLo

ut

SLi

n

SLiP I/F

PCI Controller

PCI I/F

Flash

SDRAM512 MB

User Logic

Serial PortRS232

Use

r I/O

3.3V PCI 33MHz 32/64-bit

(24,16) EDAC66 MHz

Dual Fast Simplex Links 66MHz 8/16-bit

Seri

al I/

FSerial Port

RS422

Serial Port

RS422

*Proto Only

Proto: 2V3000

RS232

5


On Chip Network Diagram

• Alternatives and issues– Crossbar logic – potential enhancement to first pass architecture if

greater bandwidth is required– RapidIO – an attractive possibility, but considered to be too costly

and complex for most applications.– Hypertransport – Similar to RapidIO, it was considered to be

excessively more than needed.

(Actel)I/F FPGA

On Chip Bus

I/F Logic

Bus Arbiter I/F Logic

I/F Logic

I/F L

og

ic

Mem

ory

C

on

troller

Configuration Manager

SLiP I/F Controller

PCI Controller

NIC

6


Example Custom Hardware Application

Flash

SDRAM

(24,16) EDAC

66 MHz

3.3V PCI 33 MHz

32/64 bits

Application FPGA(Xilinx)

I/F FPGA(Actel)

On Chip Bus

On-Chip Peripheral Bus

InterruptController

Timer

SLiP I/F

PCI I/F

Mem

or

y I

/F

NIC

Configuration I/F

Cache Controll

er

Bus Arbiter

uP

OPBuPHigh Speed

Serial I/F

LMB

LMB

FSL

Application

Processor

Seri

al

I/F

I/O Processor

7


Example Custom Hardware Application

Flash

SDRAM

(24,16) EDAC

66 MHz

Application FPGA(Xilinx)

I/F FPGA(Actel)

On Chip Bus

SLiP I/F

PCI I/F

Mem

or

y I

/F

NIC

Configuration I/F

Bus Arbiter

FFT/Convolution

Engine

High Speed

Serial I/FFUZZY Logic

Controller

Seri

al

I/F

Data Packetiz

er

Data Filter

3.3V PCI 33 MHz

32/64 bits

8


Major Components

• Components– AX2000 (CCGA624)

• Actel

– 4VFX60 (CF1144)• Xilinx

– 3D-Plus Stacked SDRAM (512MB)

– Flash (8MB at least)

– TLK2711 MGT• Texas Instrument

– Voltage Regulation

• Prototype will use XC2V3000 instead of the AX2000

High Speed Serial Interface

Application FPGA(V4FX60)

PCI-104 Connector

PCI-104 Extension

Interface FPGA

(AX2000)

Voltage Regulation

Memory Subsystem

External I/O

9


Systems Modeling

• Development support with formal modeling– Petri nets providing performability modeling which considers

both reliability and performance aspects in a unified model– Petri nets provides mathematically based rigorous approach

to system evaluation and development

• Petri nets converted to SystemC models– To serve as faster lower level system simulation models– Provides step wise refinement of the model towards RTL

while providing the eventual test bench for the final VHDL– SystemC model provides simplified path to software

evaluation for prospective applications

10


Embedded Processing

• Primary target microprocessor is the MicroblazeTM processor.– Leverage work done with XRTC– Design mitigated with XTMR tool (or manually)

• uClinux (Let the penguins fly!)– Host to uClinux operating system in a pseudo-MP structure– Provides easy path to high level development for instrument

applications (C, sockets, file systems, etc)– Development environment similar (if not identical) to typical

Linux desktop

11


Development Challenges and Issues

• TMR of the reconfigurable logic (especially the Microblaze soft core processor)

• Caching architecture across the SLiP interface.

• Fabrication with fine pitch CGA components (4VFX60)

• Availability of various technologies– Non-volatile memory (FLASH and EEPROM)– Small form factor, high-efficiency DC voltage regulators

12


Design Status as of 8/1/2005

• Currently still working architectural formulation, but the base structure is completed.– Reconfigurable nature of the prototype enables architecture

trades post hardware development.

• Schematics complete and layout proceeding.• Hardware prototypes expected at the end of the fiscal

year.

reconfigurable processing module (rpm)

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