recent system test results from the cms tob detector

Juan Valls - LECC03 Amsterdam

1

Recent System Test Results from the CMS

TOB Detector

Introduction ROD System Test Setup ROD Electrical and Optical Characterization Noise Characterization (ROD vs OTRI) S/N, Signal Efficiencies, Noise Occupancies Conclusions

Juan VallsCERN

9th Workshop on ElectronicsFor LHC Experiments

Juan Valls - LECC03 Amsterdam2

Introduction

CMS SST Total of ~25000 Si modules in

Barrel (10 layers) and Endcap (18 disks)

80000 FE chips, 50000 optical links TOB: 6 layers (~5000 silicon

modules) 10-14 points per track 223 m2 of silicon

(CDF ~2 m2, ATLAS ~60 m2 ) 10M of readout strips

~25 m3

T=-10 o C

RODs: basic TOB readout units(~700 RODs)


RODs Assembly

8 10 12

17

39

511

2 4 6

CCUM

6 (SS) or 12 (DS) silicon modules Interconnection electronics (ICB, ICC) Control electronics (CCUM) Optoelectronics (AOH) Cooling pipe + module cooling elements

CF frame profile

ICBICCs


ROD Assembly (Readout)

Analog Optohybrids (AOH ICs)

24fibers


ROD System Test Setup

FEC2CCUMboard

Optical Readout

ElectricalControls

TOB DS RODLayer 1

HV

LV

C6F14

Cooling Plant

1 kW +5C/+32C

(~3 m)


Thermal Behavior

t (sec)

T (

°C)

LV off LV on LV off

T (Si-pipe) 6 °C

Design figure:

T < 10 °C with irradiated sensorsand highest optohybrid settings

All tests at room temp To be repeated in the cold

DS ROD SS ROD


System Tests

Integrate sensors with FE electronics, interconnecting boards and buses in the final mechanical support

Integrate full optical link for signal distribution (control and readout) Integrate HV and LV power, long cables and test LV power uniformity Verify electrical tests to check integrity of signals (timing and

control) through transmission between cards Tunning of the controls and analogue optical links Validate grounding and detector bias schemes by studying noise Analysis of data from sensors, S/N ratios, signal efficiencies and strip

noise occupancies

Main objectives of pre-production phase (system tests) are the validation of the overall design structure before production


Control and Readout

PLL Delay

MUX 2:1

PLL

APVamplifierspipelines

128:1 MUX

Detector Hybrid A-Opto Hybridprocessingbuffering

TTCRx

ADC

Rx Module

FED

TTCRx

FEC

CCUCCU

CCU CCU

DCU

Control

processingbuffering

Back-End

TTC

DAQ

Digital Control2500 links @40MHz

D-Opto Hybrid

Front-End

Analogue Readout40000 links @ 40MS/s

TRx Module

Front End Drivers

Front End Controllers


Time Alignment Scans Scan through PLL

fine delays (1.04 ns) and with a fixed FED digitization delay

Reconstruct APV tick marks

The DS ROD introduces shift delays of ~2 ns on the trigger arrival time to APVs.

FED 0

FED 1

FED 2


FED Digitizing Point Find the FED optimal

digitization point

Reconstruct APV tick marks by varying FED skew clock delay wrt data (PLL settings fixed)

Choose sampling point close to the back edge of the tick mark

FED 0

FED 1

FED 2


Optical Scan Characterization

Plot ticks and baselines as a function of bias (for a fixed gain)

Get the tick amplitude from the difference between these distributions

baselines

ticks

AOH bias

AOH Gain = 1 (24 fibers)

AOH bias

tick amplitudes


Optical Scan Characterization

1516171819202122232425

0a 0b 1a 1b 2a 2b 3a 3b 4a 4b 5a 5b 6a 6b 7a 7b 8a 8b 9a 9b 10a

10b

11a

11b

Gain 0Gain 1Gain 2

Gain 0 Gain 2Gain 1

Bia

s

150-210 counts

Find optimal settings (gain and bias) for an 800 mV AOH input tick amplitude What does this correspond to at the FED (in ADC counts)? Need to calibrate FED cards: FED gain ~3.5 mV/count, Optolink gain ~0.8V/V


DS ROD Noise

DeconvolutionNon-Inverting

(200 V)

CCUM

difftot

CMN


DS ROD CMNCMN (flat) Calculation

(running average pedestals)

Non-Inverting Inverting

~40%


DS ROD HV ScansHV Bias Scan on DS ROD

6 HV channels for 12 modules(CAEN SY-127, A343 boards)

Total noise (ADC) = f (Vbias)

Full depletion at ~150 VoltsSimilar behavior for all modules

30% larger Noise in the DS ROD wrtOTRI setup


Full Gain Scans

Fit Range: Ical=18 to Ical=70

0.6 – 2.7 MIPs

Ical=29 ~ 25000 elecPeak Mode

Non-Inverting


OTRI ROD

OTRI ROD

~ 850 e/ADC (OTRI)~ 650 e/ADC (ROD)


Noise (DS ROD vs OTRI)

APV25 bare chip on PCB(Cinp=18 pF)Peak: 900 elec.Dec: 1500 elec.

OTRI SetupPeak: 1600 elec.Dec: 2600 elec.

DS ROD SetupPeak: 1600 elec.Dec: 2700 elec.

Peak ModeNon-Inverting



Signal to Noise Ratios

~500 Hz

~0.5 Hz

Use Ru106 beta source and cosmic rays

Simple cluster algorithm based on S/N thresholds

S/N>5

S/N>2

S/N

S/N=14.1 S/N=14.9

S/N=14.7 S/N=15.3

S/N=23.2 S/N=25.9


Efficiencies, Strip Occupancies

The FEDs will run a cluster finding algorithm (zero-suppression) during data taking

Only strips associated with clusters will be readout (LVL1 100 kHz Occupancies < 1.8%)

Signal Efficiencies

ClustersTotal

i

Seedi

Clustersi

i N

THSNTHeff

] [

Strip Occupancies

CMNTHped

pedx

ii

i

i

i

edxTHocc2

2

2

2

1


Signal Efficiencies vs Noise Occupancies

2 (2.3%) = 100%3 (0.14%) = 98%4 (0.003%) = 94.5%

2 (2.3%) = 100%3 (0.14%) = 99.7%4 (0.003%) = 96.4%


Conclusions Mechanical and electrical performance of pre-production RODs

validated in system tests and test-beams at CERN Thermal behavior and cooling performance verified at room

temperature Electrical tests verified Grounding and detector bias schemes validated S/N studied

On the way to production… First production ROD assembled and characterized at CERN last

week Production started ~760 RODs to be assembled at CERN and USA


XROD Software

Noise

Pulse Shape Scan

Frames

Gain Scan

ROD FAST debugging tool

CMS-like DAQ hardware

Access to BE boards TSC, FEC, FED, CCUM

Handles CCU6 and CCU25

Access to FE registers PLL, MUX, APV, DCU, AOH

Handles DCU1 and DCU2

Handles LLD1 and LLD2

Internal/external TSC triggers (and FED internal)

Single GUI Interface


Module Biasing Scheme

NAIS HVConnector on Kapton Cable

Vbias

Vbias

GND

GND(wirebond to bias ring)

BiasConnector

on Kapton Cable

TIBTOB / TEC

recent system test results from the cms tob detector

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