1

Recent Research on Memristor

Based Circuits

Herbert H.C. Iu

School of Electrical, Electronic and Computer Engineering

The University of Western Australia, Australia

Presented by H. Iu

December 2016

2

Contents

Research team

Introduction of memristor

Memristor based chaotic circuit

Universal mutator for transformations among

memristor, memcapacitor and meminductor

Coupled memristors

Future work

3

Research team

Power and Clean Energy (PACE) Research Group

Group Leaders – Prof Tyrone Fernando and Prof Herbert Iu

10 PhD students

Power Electronics, Nonlinear Systems, Smart Grid,

Renewable Energy Systems etc…

1 Emeritus Professor

4

Research areas

Switching dc/dc converters

Power factor correction circuits

Renewable energy

Smart grid

Memristor based circuits

5

Memristor

What is a memristor?

It is the missing 4th element postulated by L.O. Chua in 1971 [1].

Researchers in Hewlett-Packard announced a solid state

implementation of memristors in 2008 [2].

[1] L.O. Chua, “Memristor - The missing circuit element,” IEEE Transactions on Circuit Theory, vol. 18, no. 5, pp. 507-519, 1971. [2] D.B. Strukov, G.S. Snider, G.R. Stewart and R.S. Williams, “The missing memristor found,” Nature, pp. 80-83, Mar. 2008.

6

The four elements in circuit theory

q = i dt, where q is

the charge

= v dt, where is

the flux

7

Circuit theory of memristor

1. Charge-controlled memristor

v = M(q) i, where M(q)= d/dq. M is called memristance.

2. Flux-controlled memristor

i = W() v, where W()= dq/d. W is called memductance.

8

How memristance works? [3] R.S. Williams, “How we found the missing memristor,” IEEE Spectrum, pp. 29-35, Dec 2008.

9

How memristance works? [3] R.S. Williams, “How we found the missing memristor,” IEEE Spectrum, pp. 29-35, Dec 2008.

10

HP memristor

HP memristor is in the form of a partially doped TiO2 thin

film with platinum electrodes.

M(w)= RON (w(t)/D) + ROFF (1- w(t)/D),

w(t)= v (RON /D) q(t),

where D is the total width of TiO2 film, w(t) is the width of the region of

high dopant concentration on the film, ROFF and RON are the limit values

of the memristance for w(t) =0 and w(t)=D, v is the dopant mobility.

w

D

A

V

doped undoped

11

Fingerprint -Pinched hysteresis loop

-1.0 -0.5 0.0 0.5 1.0

-10

-5

0

5

10

Cu

rren

t(×

10

-3)

Voltage

ω0

10ω0

500.0

0.2

0.4

0.6C

han

ge

Flux

12

Classification [4] L. O. Chua, “Everything you wished to know about memristors but are afraid to ask,” Radio Engineering, June 2015.

1. Ideal memristor

2. Generic memristor

3. Extended memristor

13

Ideal memristor

Current-controlled

v = M(q) i; dq/dt = i.

Voltage-controlled

i = W() v; d/dt = v.

14

Generic memristor

Current-controlled

v = M(x) i; dx/dt = f(x,i).

Voltage-controlled

i = W(x) v; dx/dt = g(x,v).

15

Extended memristor

Current-controlled

v = M(x, i) i ; M(x,0) ; dx/dt = f(x,i).

Voltage-controlled

i = W(x, v) v; W(x,0) ; dx/dt = g(x,v).

16

Motivation

Memristor will have a lot of potential applications, and some of them will be related to nonlinear dynamics.

The characteristics and dynamical behaviour of memristor based systems should be studied in detail.

Recent studies show that memristor can play a major role in nonlinear systems.

17

Memristor based chaotic circuit

L

Li

2C 2v1v

1C

R

[5] H.H.C. Iu et al., “Controlling chaos in a memristor based circuit using twin-t notch filter,” IEEE Transactions on Circuits and Systems Part I, vol. 58, no. 6, pp. 1337-1344, 2011.

1

1 2 11

1

2 1 2

2

2

( )( )

( ) ( ) ( )1( ( ( )) ( ))

( ) ( ) ( )1( ( ))

( ) ( )

L

L

d tv t

dt

dv t v t v tW t v t

dt C R

dv t v t v ti t

dt C R

di t v t

dt L

φ(t) denotes the magnetic flux between two terminals of a memristor, assume q= a+bφ3

2( ( )) 3 ( )W t a b t W(φ(t)) is the memductance function,

18

Simulation parameters

19

Phase portraits

Chaotic state

R=1800Ω

Periodic state

R=1600Ω

20

Power spectrum diagrams

Chaotic state

Periodic state

21

Bifurcation diagrams

Phi vs R

v1 vs R

22

Twin-T notch filter

( )inv tnR nR

1

2nR

nC nC

2 nC

( )ov t

1qR

2qR

1( )n tv

2 ( )n tv

2

1 1 2

2 2 1

2 1

( ) ( ) 0.5 ( ) (2 2 0.5) ( ) (2 1) ( ) 2 ( )

( ) ( ) 2 ( ) (2 1) ( ) ( )

( ) ( ) 2 ( ) 2( 1) ( ) 2 ( )

n in in o n n

n n

n in n o n

n n

o in n o n

n n

dv t dv t v t q q v t q v t qv tq

dt dt R C

dv t dv t v t q v t v t

dt dt R C

dv t dv t v t q v t v t

dt dt R C

23

Input-output transfer function

2

2 2

2

2 2

1

( )( )

4 1( )(1 )

o n n

in

n n n n

sV s R C

F sV s

s q sR C R C

24

Schematic of the MCC with notch filter controller

L

Li

2C 2v1v1C

R

nR nR

1

2nR

nC nC

2 nC

1R1R

3R

3R

( )oi t

1qR

2qR

25

Experimental prototype

26

Results of notch filter control

27

Experimental results- phase portraits

v2 vs phi

v2 vs v1

28

Experimental results- power spectrum

Before connection -

Chaotic state

After connection -

Periodic state

29

Memristor emulator [6] D.S. Yu, H.H.C. Iu et al., “A floating memristor emulator based relaxation oscillator” IEEE Transactions on Circuits and Systems Part I, vol. 61, no. 10, pp. 2888-2896, 2014.

y

x zU1

U2

U3

y

x

z

U4

3R 10R

MRiA

B y

x

z

y x

z

4R

1C

1x

2x

2y1

y z

w

AD633

U5

6R

5R

7R

sv

8R

9RU6

ABv

MRi

p

p

1i

2i

y1v

wv

c1v

r10v

4 8 9 7 7MR AB AB s

3 8 10 5 3 1 6

( ) 1

10

R R R R Ri v v

R R R R R C R

AB ABW

W(φ(t)) is the memductance.

4 7 8 9

2

3 5 1 8 10

,10

R R R R

R R C R R

4 7 8 9

s

3 6 8 10

=10

R R R Rv

R R R R

-2 -1 0 1 2-6

-4

-2

0

2

4

6

35.4Hz

120Hz

17.6Hz

vr10(V

)

vAB(V)

Emulator consists of 4 current conveyors, 1 op

amp, 1 multiplier, 1 capacitor and several resistors.

30

Serial and Parallel Connections

-2 -1 0 1 2

-0.2

0.0

0.2

iMR(m

A)

vAB(V)

Parallel

W

Serial

W

A

B

B

A

W

Parallel

Serial

MRi

MRi

W

W

0.90 0.92 0.94 0.96 0.98 1.00

0.05

0.10

0.15

0.20

0.25

0.30

Mem

du

cta

nce

(mS

)

t(s)

Serial

W

Parallel

31

Introduction of Memcapacitor [7] M. Di Ventra, Y. V. Pershin, and L. O. Chua, “Circuit elements with memory: memristors, memcapacitors and meminductors,” Proc. IEEE, vol. 97, no. 10, pp. 1717–1724, Oct. 2009.

32

Introduction of Meminductor

I

33

A Universal Mutator [8] D.S. Yu, Y. Liang, H.H.C. Iu and L.O. Chua, “A Universal Mutator for Transformations among Memristor, Memcapacitor and Meminductor,” IEEE Transactions on Circuits and Systems Part II, vol. 61, no. 10, pp. 758-762, 2014.

x

y

z+1

U3

p

v

x y

z

x

yz

+1

+1

U1

U2

1

2 3 4

5

2 zvp

p

3zv

i

A

B

C

D

E

F

Mutator consists of 3 common

transimpedance operational

amplifiers (TOAs)

Position 4 is used for memory

elements.

Positions 1, 2, 3 and 5 contain only

resistors or capacitors.

34

Case study: MR to MC

2R

x

y

z+1

U3

p

MCv

x y

z

x

yz

+1

+1

U1

U2

2 zvp

p

3zv

MCi

A

B

C

D

mG3R

1C5R

m MRG

At position 4,

Cm=GmC1R3R5/R2

From terminal AB,

35

MR to MC : Experimental Results

-1 0 1-6

-4

-2

0

2

4

6

52.9Hz

38.6Hz

qM

C(u

C)

vMC(V)

27.5Hz

-2 -1 0 1 2

1

2

3

4

5

52.9Hz

38.6Hz

27.5Hz

Cm=1.64F

Cm=3.95F

Cm

(F

)

vMC(V)

Measured pinched hysteretic loops

Variation curve of Cm along with

terminal voltages

36

Summary of Transformations

x

y

z+1

U3

p

v

x y

z

x

yz

+1

+1

U1

U2

1

2 3 4

5

2 zvp

p

3zv

i

A

B

C

D

E

F

37

Coupled Memristors [9] D.S. Yu, H.H.C. Iu, Y. Liang, T. Fernando and L.O. Chua, “Dynamic Behavior of Coupled Memristor Circuits,” IEEE Transactions on Circuits and Systems Part I, vol. 62, no. 6, pp. 1607-1616, June 2015.

( ) ( ) ( )i t W v t

( )( )

dqW

d

1 1 1 2 1( ) ( , ) ( )i t W v t

2 2 1 2 2( ) ( , ) ( )i t W v t

11( )

dv t

dt

22 ( )

dv t

dt

Flux controlled memristor model:

A flux controlled and coupled ideal

MR system:

( )W

38

A Flux Controlled and Coupled Ideal MR system

1 1 2 1 1 1 2 2( , )W

2 2 1 2 2 2 1 1( , )W

1

2MR1 MR2

1A 2A 2B1B

39

Coupled MRs in Serial Connections

Serial MR Circuit with Identical Polarities

1

2

MR1 MR2

B2

A1

1v2v

12 1 2v v v

1 1 1 2 2 2 2 1( , ) ( , )i vW v W

12 1 2

1 1 1 1 2 2 2 2 2 2 1 1( ) ( )i v v

40

Coupled MRs in Serial Connections

Serial MR Circuit with Identical Polarities

1

2

MR1 MR2

B2

A1

1v2v1 12 2 2 2 1 1

1 1 1 2 2 2 1 2

( )

( ) ( )

d v

dt

2 12 1 1 1 2 2

1 1 1 2 2 2 1 2

( )

( ) ( )

d v

dt

41

Coupled MRs in Serial Connections

For the special case of α1=α2=α and κ1=κ2=α,

1

2

MR1 MR2

B2

A1

1v2v

1 12 212

12 1 22

dv

dt

2 12 112

12 1 22

dv

dt

42

Coupled MRs in Serial Connections

Assume that the initial value of φ12 is zero,

1

2

MR1 MR2

B2

A1

1v2v 1 12 2 1 12 1 2

12 ( ) ln(2 )

4

2 12 1 2 12 1 2

12 ( ) ln(2 )

4

Memductance of individual MR can be obtained,

1 1 2 1 1 1 2 2( , )W

2 2 1 2 2 2 1 1( , )W

43

Coupled MRs in Serial Connections

For further simplification we assume β1=β2=β,

1

2

MR1 MR2

B2

A1

1v2v

1 2 12

1

2

1 2 12

1

2v v v

1 2 12W W

The memductance of each coupled MR can be written as,

Two coupled MRs serially connected with identical polarities operate as a new MR with a new memductance value of W12=W1/2=W2/2=(α12(t)+)/2.

44

Coupled MRs in Serial Connections- Simulation Results

Serial MR Circuit with Identical Polarities

1 2

12

1 2

WWW

W W

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6

-4

-3

-2

-1

0

1

2

3

4

W12(with initial flux=0.02Wb)

i (mA)

v1

2,v

1,v

2 (V

)

Identical Polarities

W2

W12

W1

-4 -2 0 2 4 6 8 10 12 14

0.1

0.2

0.3

0.4

1 212

1 2

WWW

W W

Mem

du

cta

nce (

mS

)Identical Polarities

W2

W1

× 10-6

q (C)0.00 0.05 0.10

0.05

0.10

0.15

0.20

0

22

2

2

22

Mem

du

ctan

ce W

12 (

mS

)

12 (Wb)

23

Identical Polarities

Initial Memductance

1

2

MR1 MR2

B2

A1

1v2v

45

Coupled MRs in Parallel Connections

Parallel MR Circuit with Identical Polarities

1

2

MR1

MR2

A1

B2

1v

2v

1i

2i

12v

i

1 2i i i

12 1 2

1 1 1 1 2 2 2 2 2 2 1 1( ) ( )i v v

121 2 1 2 1 2 12

21( ) ( )

2q

46

Coupled MRs in Parallel Connections

Parallel MR Circuit with Identical Polarities

1

2

MR1

MR2

A1

B2

1v

2v

1i

2i

12v

i

1212 12 1 2 1 2 12 1 2

12

( )( ) ( )

dqW

d

Two flux coupled MRs in parallel connection operates as a new flux controlled MR, and the equivalent memductance is equal to the sum of individual memductances.

47

Coupled MRs in Parallel Connections- Simulation Results

Parallel MR Circuit with Identical Polarities

1

2

MR1

MR2

A1

B2

1v

2v

1i

2i

12v

i

-3 -2 -1 0 1 2 3-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

i1,i

2,i

(m

A)

v12 (V)

Identical Polarities

W2

W12

W1

-0.02 0.00 0.02 0.04 0.06 0.08

0.2

0.4

0.6

0.8

1.0

1.2Identical Polarities

Mem

du

cta

nce (

mS

)

12 (Wb)

0

23

2

2

23

48

Conclusion

A memristor based chaotic circuit is contructed.

A universal mutator for transformations of memristror,

memcapacitor and meminductor is developed.

Dynamic behaviour of coupled memristor based circuits

is studied.

49

Future work

Study other circuit elements with memory:

memcapacitor and meminductor.

Develop other applications of memristor based circuits,

e.g. synchronization and consensus of coupled

memristor based circuits.

50

References

[1] L.O. Chua, “Memristor - The missing circuit element,” IEEE Transactions on Circuit Theory, vol. 18,

no. 5, pp. 507-519, 1971.

[2] D.B. Strukov, G.S. Snider, G.R. Stewart and R.S. Williams, “The missing memristor found,” Nature, pp.

80-83, Mar. 2008.

[3] R.S. Williams, “How we found the missing memristor,” IEEE Spectrum, pp. 29-35, Dec. 2008.

[4] L. O. Chua, “Everything you wished to know about memristors but are afraid to ask,” Radio

Engineering, June 2015.

[5] H.H.C. Iu et al., “Controlling chaos in a memristor based circuit using twin-t notch filter,” IEEE

Transactions on Circuits and Systems Part I, vol. 58, no. 6, pp. 1337-1344, 2011.

[6] D.S. Yu, H.H.C. Iu et al., “A floating memristor emulator based relaxation oscillator” IEEE Transactions

on Circuits and Systems Part I, vol. 61, no. 10, pp. 2888-2896, 2014.

[7] M. Di Ventra, Y. V. Pershin, and L.O. Chua, “Circuit elements with memory: memristors, memcapacitors

and meminductors,” Proc. IEEE, vol. 97, no. 10, pp. 1717–1724, Oct. 2009.

[8] D.S. Yu, Y. Liang, H.H.C. Iu and L.O. Chua, “A Universal Mutator for Transformations among

Memristor, Memcapacitor and Meminductor,” IEEE Transactions on Circuits and Systems Part II, vol. 61,

no. 10, pp. 758-762, 2014.

[9] D.S. Yu, H.H.C. Iu, Y. Liang, T. Fernando and L.O. Chua, “Dynamic Behavior of Coupled Memristor

Circuits,” IEEE Transactions on Circuits and Systems Part I, vol. 62, no. 6, pp. 1607-1616, June 2015.