realization of an 8-bit processor - ijetcse · 2017-06-16 · international journal of emerging...

International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE) ISSN: 0976-1353 Volume 24 Issue 9 – JUNE 2017.

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REALIZATION OF AN 8-BIT PROCESSOR USING XILINX

T.Deepa M.E (Applied Electronics)

Department of Electronics and Communication Engineering, Sri Venkateswara College of Engineering,

Sriperumbudur, Chennai, India.

Dr. S. Muthukumar Professor

Department of Electronics and Communication Engineering, Sri Venkateswara College of Engineering,

Sriperumbudur, Chennai, India.

Abstract: This project presents the design of soft processor by using verilog HDL in Xilinx ISE12.2 simulator. The soft processor consists of 8-bit ALU, 8-bit instruction register, 64-bit accumulator, 10-bit program counter, 1KB memory, control unit and temporary registers, which are 8-bit ‘a’ register, 8-bit ‘b’ register, 64-bit ‘aa’ register, 64-bit ‘bb’ register and 64-bit ‘y’ register. It perfo rms 22 different arithmetic and logical instructions such as addition, subtraction, increment, decrement, multiplication, square, and, nand, nor, or, not, ex-or, ex-nor, arithmetic shift left, arithmetic shift right, rotate left, rotate right, compare, logical shift left, logical shift right, add with carry, and subtract with borrow, 10 different floating point instructions such as 32-bit floating point addition, 32-bit floating point subtraction, 32-bit floating point multiplication, 32-bit floating point increment, 32-bit floating point decrement, 64-bit floating point addition, 64-bit floating point subtraction, 64-bit floating point multiplication, 64-bit floating point increment, 64-bit floating point decrement and 5 data transfer instructions. The control unit generates all the control signals needed for the coordination among the entire components of the soft processor. All the modules in the design were coded by using behavioral and structural modeling in verilog HDL language. The design entry, synthesis, and simulation of soft processor have been done by using Xilinx ISE 12.2 software. The soft processor is designed with 17% utilization and totally 1026 slices are used. Its frequency is 6.25 MHz which is obtained, with a minimum period of 160ns.

Keywords: Soft processor (8-bit processor), verilogHDL, Xilinx ISE12.2, Arithmetic and logic unit (ALU), Floating Point (FP) unit, Register Transfer Level (RTL).

I. INTRODUCTION

In the mid-seventies it was easy to define a microprocessor. At that time one could say that a microprocessor is a central processing unit realized on a large-scale integration (LSI) i.e. 50,000 or more transistors on a single integrated chip, operating at a clock frequency of 1 to 5 MHZ, constituting an 8-bit system, with two to seven general-

purpose CPU 8-bit registers. Most of the new microprocessor issue more than one instruction per cycle. Practically all modern microprocessor have on–chip floating point (FP) unit. Most systems have a separate 32-register file for the integer unit, and a separate 32-register file for floating point unit.

II. RELATED WORK

Several papers regarding soft processor has been reviewed. The following papers have been surveyed. In [14] Sahdev D. Kanjariya, Rutarth Patel designed Generic IEEE-754 Based Floating Point Adder, Subtractor and Multiplier. In this paper, architecture of floating point unit is proposed and discussed. This floating point unit is compatible with all three IEEE-754 binary representations. Further based on this architecture, floating point subtractor, adder and multiplier modules are designed and functionally verified in Virtex-4 FPGA. In [15] Sreehari Veeramachaneni, M. B. Srinivas designed arithmetic floating point unit. Floating point adder and subtractor units like fused floating point adder, triple path floating point (FP) adder, etc.., involve exponent comparison or subtraction, mantissa addition or subtraction and incrementing values while rounding as basic operations. To realize these operations, efficient arithmetic units like adders, subtractors, comparators and incrementers are vital. In this paper an efficient design of a floating point adder and a design methodology for 2’s complement block is proposed which helps in design of floating point units. In [16] Prateek Singh, Kalyani Bhole designed Optimized Floating Point Arithmetic Unit. In this paper an arithmetic unit based on IEEE-754 standard for floating point numbers has been implemented on Spartan3E XC3S500e FPGA Board. Here Floating Point Unit (FPU) follows IEEE single precision (32-bit) format. Various arithmetic operations such as, addition, multiplication, subtraction and division on floating point numbers have been performed on arithmetic unit. Novel approach of converting fixed to floating point saves around 30% of slices and can perform 50 Mega floating point operations per second on Spartan 3E FPGA at 50 MHz clock.

International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE)ISSN: 0976

III. DESIGN METHODOLOGYA. ALU design

An 8-bit ALU has been designed using verilog HDL. The Figure.1 shows the block diagram of 8input for 22 operations like addition, subtraction, multiplication, square, increment, decrement, AND, OR, NOT, NOR, etc., are fetched from registers ‘a’ and ‘b’. The inputs for the 10 operations like single and double precision floating point addition, floating point subtraction, etc., are obtained from registers ‘aa’ and ‘bb’. The inputs for the remaining 5 data transfer operations are obtained from registers ‘aa’ and ‘bb’. The output of arithmetic unit and logic unit are given to 64:1 multiplexer. A 64:1 multiplexer requires 6 selection lines which are s0, s1, s2, s3, s4, s5. According to this selection lines logical and arithmeticperform. Finally output from the ALU is stored in ‘y’ register. After the execution of the arithmetic and logical instruction has performed, if the result of the ALU is zero, then the zero flag is set. The sign flag is set, when bit D7 of In a given byte, if D7 bit is 1, the result will be positive number; otherwise it will be negative value. This sign flag is used with signed numbers.

Figure.1 Block diagram of ALU

B. Single precision floating point (FP) unit

32-bit FP addition, 32-bit subtraction and 32multiplication unit has been designed using verilog HDL. Here, the inputs of the FP unit have been represented by using IEEE 754 format. Each 32-bit input has 3 fields which are 1bit sign field, 8-bit exponent field and 23-bit mantissa field.

International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE)ISSN: 0976-1353 Volume 24 Issue 9 – JUNE 2017.

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III. DESIGN METHODOLOGY

bit ALU has been designed using verilog HDL. The Figure.1 shows the block diagram of 8-bit ALU. The input for 22 operations like addition, subtraction, multiplication, square, increment, decrement, AND, OR,

hed from registers ‘a’ and ‘b’. The inputs for the 10 operations like single and double precision floating point addition, floating point subtraction, etc., are

The inputs for the are obtained from

The output of arithmetic unit and logic unit are given to 64:1 multiplexer. A 64:1 multiplexer requires 6 selection lines which are s0, s1, s2, s3, s4, s5. According to this selection lines logical and arithmetic operations will

stored in ‘y’ register. After the execution of the arithmetic and logical instruction has performed, if the result of the ALU is zero, then the zero flag is set. The sign flag is set, when bit D7 of the result is 1. In a given byte, if D7 bit is 1, the result will be positive number; otherwise it will be negative value. This sign flag is

Figure.1 Block diagram of ALU

B. Single precision floating point (FP) unit

bit subtraction and 32-bit multiplication unit has been designed using verilog HDL. Here, the inputs of the FP unit have been represented by using

bit input has 3 fields which are 1-bit mantissa field.

Bias value for 32-bit FP unit =

1. Algorithm for 32-bit FP adder

Consider first operand is ‘aa’ and second operand is ‘bb’. The Figure.2 shows the block diagram of 32

1. Sign of the result will always be thebit of the first operand.

2. The exponent value of the operand ‘aa’ should always be greater than exponent value of the operand ‘bb’, otherwise swap these operands. And then subtract the exponent of opera‘aa’ i.e. e1-e2.

3. Normalize the mantissa of ‘bb’ i.e represent the mantissa m2 in 1.m2 format.

4. According to the difference value obtained from e1e2, left shift the normalized value (1.m2). Output of the right shifter is aligned mantiss

5. Normalize the mantissa of ‘aa’ i.e represent the mantissa m1 in 1.m1 format.

6. Add the normalized value of m1(1.m1) and output of right shifter by using 24

7. The output of the adder is 24if carry is 1, the output of the add 1 with first operand exponent and normalize the mantissa(1.m) . Otherwise the output exponent is e1 and there is no need for normalization.

8. If carry is 1 then the mantissa of the result will be same as [23:1] of the adder output, omantissa is [22:0] of adder output.

Figure.2 Block diagram of 32

2. Algorithm for 32-bit FP subtractor


International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE)

bit FP unit = (2^e-1)-1=(2^8-1)-1=127

bit FP adder

Consider first operand is ‘aa’ and second operand is ‘bb’. shows the block diagram of 32-bit FP adder.

of the result will always be the same as the sign bit of the first operand. The exponent value of the operand ‘aa’ should always be greater than exponent value of the operand ‘bb’, otherwise swap these operands. And then

the exponent of operand ‘bb’ from operand

Normalize the mantissa of ‘bb’ i.e represent the mantissa m2 in 1.m2 format. According to the difference value obtained from e1-e2, left shift the normalized value (1.m2). Output of the right shifter is aligned mantissa. Normalize the mantissa of ‘aa’ i.e represent the mantissa m1 in 1.m1 format. Add the normalized value of m1(1.m1) and output of right shifter by using 24-bit adder. The output of the adder is 24-bit sum and 1-bit carry. if carry is 1, the output of the exponent is e1+1 i.e add 1 with first operand exponent and normalize the mantissa(1.m) . Otherwise the output exponent is e1 and there is no need for normalization. If carry is 1 then the mantissa of the result will be same as [23:1] of the adder output, otherwise the mantissa is [22:0] of adder output.

Figure.2 Block diagram of 32-bit FP adder

bit FP subtractor

Consider first operand is ‘aa’ and second operand is ‘bb’. shows the block diagram of 32-bit FP subtractor.



2. The exponent value of the operand ‘aa’ should always be greater than exponent value of the operand ‘bb’, otherwise swap these operands. And then subtract the exponent of operand ‘bb’ from operand ‘aa’ i.e. e1-e2.

3. Normalize the mantissa of ‘bb’ i.e. represent the mantissa m2 in 1.m2 format.

4. According to the difference value obtained from e1e2, left shift the normalized value (1.the right shifter is aligned mantissa.

5. Normalize the mantissa of ‘aa’ i.e. represent the mantissa m1 in 1.m1 format.

6. Add the normalized value of m1 (1.m1) and output of right shifter by using 24-bit subtractor.

7. The output of the subtactor is 24-bit difference and 1bit borrow. if borrow is 1, the output of the exponent is e1+1 i.e. add 1 with first operand exponent and normalize the mantissa(1.m) . Otherwise the output exponent is e1 and there is no need for normalization.

8. If borrow is 1 then the mantissa of the result will be same as [23:1] of the subtractor output, otherwise the mantissa is [22:0] of subtractor output.

Figure.3 Block diagram of 32-bit FP subtractor

3. Algorithm for 32-bit FP multiplier


1. The EX-OR of first operand (s1) and second operand (s2) sign bits will be the sign bit (s3) of the output.

2. Normalize the mantissa of the first operand ‘aa’ to 1.m1 format and second operand ‘bb’ to 1.m2 format.

3. Multiply the normalized mantissas of both operands by using 24-bit multiplier. The output of the multiplier is 47-bit sum and 1-bit carry.


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of the result will always be the same as the sign

The exponent value of the operand ‘aa’ should always be greater than exponent value of the operand

operands. And then subtract the exponent of operand ‘bb’ from operand

Normalize the mantissa of ‘bb’ i.e. represent the

According to the difference value obtained from e1-e2, left shift the normalized value (1.m2). Output of the right shifter is aligned mantissa. Normalize the mantissa of ‘aa’ i.e. represent the

(1.m1) and output of bit subtractor.

bit difference and 1-bit borrow. if borrow is 1, the output of the exponent is e1+1 i.e. add 1 with first operand exponent and normalize the mantissa(1.m) . Otherwise the output exponent is e1 and there is no need for normalization.

the mantissa of the result will be same as [23:1] of the subtractor output, otherwise the mantissa is [22:0] of subtractor output.

bit FP subtractor

nd operand is ‘bb’. shows the block diagram of 32-bit FP multiplier.

OR of first operand (s1) and second operand (s2) sign bits will be the sign bit (s3) of the output. Normalize the mantissa of the first operand ‘aa’ to .m1 format and second operand ‘bb’ to 1.m2 format.

Multiply the normalized mantissas of both operands bit multiplier. The output of the

bit carry.

4. Add the exponents of first and second operand by using 8-bit adder and subtract the bias value 127 from the adder output.

Bias value for 32-bit FP unit = (2^e

5. If carry is 1, the output of the exponent is e1+1 i.e. adds 1 with first operand exponent and normalize the mantissa (1.m). Otherwise the and there is no need for normalization.

6. If carry is 1 then the mantissa of the result will be same as [46:24] of the multiplier output, otherwise the mantissa is [45:23] of multiplier output.


4. Algorithm for 32-bit FP incrementer

Consider first operand is ‘aa’ and secoThe Figure.5 shows the block diagram of 32



2. The exponent value of the operand ‘aa’ should always be greater than 8' b01111111, otherwise swap these operands. And then Subtract 8' b01111111 from operand ‘aa’ i.e. e1


Add the exponents of first and second operand by r and subtract the bias value 127

bit FP unit = (2^e-1)-1= (2^8-1)-1=127

If carry is 1, the output of the exponent is e1+1 i.e. adds 1 with first operand exponent and normalize the mantissa (1.m). Otherwise the output exponent is e1 and there is no need for normalization. If carry is 1 then the mantissa of the result will be same as [46:24] of the multiplier output, otherwise the mantissa is [45:23] of multiplier output.

Figure.4 Block diagram of 32-bit FP multiplier

bit FP incrementer


Figure.5 Block diagram of 32-bit FP incrementer

of the result will always be the same as the sign bit of the first operand. The exponent value of the operand ‘aa’ should always be greater than 8' b01111111, otherwise swap these operands. And then Subtract 8' b01111111 from operand ‘aa’ i.e. e1-8' b01111111.


3. The input of the right shifter (RS) is 24'b100000000000000000000000.difference value obtained from e1-shift the input of RS. Output of the right shifter (RS) is aligned mantissa.

4. Normalize the mantissa of ‘aa’ i.emantissa m1 in 1.m1 format.

5. Add the normalized value of m1(1.m1) and output of right shifter by using 24-bit adder.

6. The output of the adder is 24-bit sum and 1if carry is 1, the output of the exponent is e1+1 i.e add 1 with first operand exponent and normalize the mantissa(1.m) . Otherwise the output exponent is e1 and there is no need for normalization.

7. If carry is 1 then the mantissa of the result will be same as [23:1] of the adder output, otherwise the mantissa is [22:0] of adder output.

5. Algorithm for 32-bit FP decrementer



2. The exponent value of the operand ‘aa’ should always be greater than 8' b0111111 , otherwise swap these operands. And then Subtract 8' from operand ‘aa’ i.e. e1-8' b01111111.

3. The input of the right shifter (RS) is 24'b100000000000000000000000.difference value obtained from e1-shift the input of RS. Output of the right shifter (RS) is aligned mantissa.


5. Add the normalized value of m1(1.m1) and output of right shifter by using 24-bit adder.

6. The output of the adder is 24-bit sum and 1if carry is 1, the output of the exponent is e1+1 i.e add 1 with first operand exponent and normalize the mantissa(1.m) . Otherwise the output exponent is e1 and there is no need for normalization.

7. If carry is 1 then the mantissa of the result will be same as [23:1] of the adder output, otherwise the mantissa is [22:0] of adder output.


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The input of the right shifter (RS) is 24'b100000000000000000000000. According to the

-8' b01111111, left shift the input of RS. Output of the right shifter (RS)

Normalize the mantissa of ‘aa’ i.e. represent the

Add the normalized value of m1(1.m1) and output of

bit sum and 1-bit carry. if carry is 1, the output of the exponent is e1+1 i.e

first operand exponent and normalize the mantissa(1.m) . Otherwise the output exponent is e1 and there is no need for normalization. If carry is 1 then the mantissa of the result will be same as [23:1] of the adder output, otherwise the



The exponent value of the operand ‘aa’ should always be greater than 8' b0111111 , otherwise swap these operands. And then Subtract 8' b01111111

8' b01111111. The input of the right shifter (RS) is 24'b100000000000000000000000. According to the

-8' b01111111, left shift the input of RS. Output of the right shifter (RS)

Normalize the mantissa of ‘aa’ i.e represent the

d the normalized value of m1(1.m1) and output of

bit sum and 1-bit carry. if carry is 1, the output of the exponent is e1+1 i.e add 1 with first operand exponent and normalize the

1.m) . Otherwise the output exponent is e1 and there is no need for normalization. If carry is 1 then the mantissa of the result will be same as [23:1] of the adder output, otherwise the mantissa is [22:0] of adder output.

Figure.6 Block diagram of

C. Double precision floating point (FP) unit

64-bit FP addition, 64multiplication unit has been designed using verilog HDL. Here, the inputs of the FP unit have been represented by using IEEE 754 format. Each 32-bit input has 3 fields which are 1bit sign field, 11-bit exponent field and 52

Bias for 64-bit FP unit = (2^e

1. Algorithm for 64-bit FP adder

Consider first operand is ‘aa’ and seco‘bb’. The Figure.7 shows the block diagram of 64adder.


2. The exponent value of the operand ‘aa’ should always be greater than exponent value of the operand ‘bb’, otherwise swap these operands. And then subtract the exponent of operand ‘‘aa’ i.e. e1-e2.

3. Normalize the mantissa of ‘bb’ i.e represent the mantissa m2 in 1.m2 format.

4. According to the difference value obtained from e1e2, left shift the normalized value (1.m2). Output of the right shifter is aligned mantissa.


6. Add the normalized value of m1 (1.m1) and output of right shifter by using 53

7. The output of the adder is 53if carry is 1, the output of the add 1 with first operand exponent and normalize the mantissa(1.m) . Otherwise the output exponent is e1 and there is no need for normalization.

8. If carry is 1 then the mantissa of the result will be same as [52:1] of the adder output, omantissa is [51:0] of adder output.


Figure.6 Block diagram of 32-bit FP deccrementer

C. Double precision floating point (FP) unit

bit FP addition, 64-bit subtraction and 64-bit multiplication unit has been designed using verilog HDL. Here, the inputs of the FP unit have been represented by using

bit input has 3 fields which are 1-onent field and 52-bit mantissa field.

bit FP unit = (2^e-1)-1= (2^11-1)-1=1023

bit FP adder

Consider first operand is ‘aa’ and second operand is shows the block diagram of 64-bit FP

of the result will always be the same as the sign bit of the first operand. The exponent value of the operand ‘aa’ should always be greater than exponent value of the operand ‘bb’, otherwise swap these operands. And then subtract the exponent of operand ‘bb’ from operand

Normalize the mantissa of ‘bb’ i.e represent the mantissa m2 in 1.m2 format. According to the difference value obtained from e1-e2, left shift the normalized value (1.m2). Output of the right shifter is aligned mantissa.

ormalize the mantissa of ‘aa’ i.e represent the mantissa m1 in 1.m1 format. Add the normalized value of m1 (1.m1) and output of right shifter by using 53-bit adder. The output of the adder is 53-bit sum and 1-bit carry. if carry is 1, the output of the exponent is e1+1 i.e add 1 with first operand exponent and normalize the mantissa(1.m) . Otherwise the output exponent is e1 and there is no need for normalization. If carry is 1 then the mantissa of the result will be same as [52:1] of the adder output, otherwise the mantissa is [51:0] of adder output.


Figure.7 Block diagram of 64-bit FP adder

2. Algorithm for 64-bit FP subtractor

Consider first operand is ‘aa’ and sec‘bb’. The Figure.8 shows the block diagram of 64subtractor.


2. The exponent value of the operand ‘aa’ should always be greater than exponent value of the operand ‘bb’, otherwise swap these operands. And then subtract the exponent of operand ‘bb’ from operand ‘aa’ i.e. e1-e2.

3. Normalize the mantissa of ‘bb’ i.e. represemantissa m2 in 1.m2 format.

4. According to the difference value obtained from e1e2, left shift the normalized value (1.m2). Output of the right shifter is aligned mantissa.

5. Normalize the mantissa of ‘aa’ i.e. represent the mantissa m1 in 1.m1 format.

6. Add the normalized value of m1 (1.m1) and output of right shifter by using 53-bit subtractor.

7. The output of the subtactor is 53-bit difference and 1bit borrow. if borrow is 1, the output of the exponent is e1+1 i.e add 1 with first operand exponent and normalize the mantissa(1.m) . Otherwise the output exponent is e1 and there is no need for normalization.

8. If borrow is 1 then the mantissa of the result will be same as [52:1] of the subtractor output, otherwise the mantissa is [51:0] of subtractor output.


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bit FP adder

Consider first operand is ‘aa’ and second operand is shows the block diagram of 64-bit FP


The exponent value of the operand ‘aa’ should always be greater than exponent value of the operand ‘bb’, otherwise swap these operands. And then subtract the exponent of operand ‘bb’ from operand

Normalize the mantissa of ‘bb’ i.e. represent the

According to the difference value obtained from e1-e2, left shift the normalized value (1.m2). Output of the right shifter is aligned mantissa. Normalize the mantissa of ‘aa’ i.e. represent the

Add the normalized value of m1 (1.m1) and output of bit subtractor.

bit difference and 1-bit borrow. if borrow is 1, the output of the exponent is e1+1 i.e add 1 with first operand exponent and ormalize the mantissa(1.m) . Otherwise the output

exponent is e1 and there is no need for normalization. If borrow is 1 then the mantissa of the result will be same as [52:1] of the subtractor output, otherwise the mantissa is [51:0] of subtractor output.


3. Algorithm for 64-bit FP multiplier


1. The EX-OR of first operand (s1) and second operand (s2) sign bits will be the sign bit (s3) of the output.

2. Normalize the mantissa of the first operand ‘aa’ to 1.m1 format and second operand ‘bb’ to 1.m2 format.

3. Multiply the normalized mantissas of both opby using 53-bit multiplier. The output of the multiplier is 105-bit sum and 1

4. Add the exponents of first and second operand by using 11-bit adder and subtract the bias value 127 from the adder output. Bias for 64-bit FP unit = (2^e

5. If carry is 1, the output of the exponent is e1+1 i.e. adds 1 with first operand exponent and the mantissa (1.m). Otherwise the output exponent is e1 and there is no need for normalization.

6. If carry is 1 then the mantissa of thesame as [104:53] of the multiplier output, otherwise the mantissa is [103:52] of multiplier output.


Figure.8 Block diagram of 64-bit FP subtractor

bit FP multiplier

Consider first operand is ‘aa’ and second operand is ‘bb’. shows the block diagram of 64-bit FP multiplier.

OR of first operand (s1) and second operand (s2) sign bits will be the sign bit (s3) of the output. Normalize the mantissa of the first operand ‘aa’ to 1.m1 format and second operand ‘bb’ to 1.m2 format. Multiply the normalized mantissas of both operands

bit multiplier. The output of the bit sum and 1-bit carry.

Add the exponents of first and second operand by bit adder and subtract the bias value 127

bit FP unit = (2^e-1)-1=(2^11-1)-1=1023

If carry is 1, the output of the exponent is e1+1 i.e. adds 1 with first operand exponent and normalizes the mantissa (1.m). Otherwise the output exponent is e1 and there is no need for normalization. If carry is 1 then the mantissa of the result will be same as [104:53] of the multiplier output, otherwise the mantissa is [103:52] of multiplier output.


Figure.9 Block diagram of 64-bit FP multiplier

4. Algorithm for 64-bit incrementer

The operation of 64-bit incrementer is incrementer. Only the number of input bits increasesaccording to double precision, it has 1-bit exponent and 52-bit mantissa. The Figure.10diagram of 64-bit FP incrementer.

Figure.10 Block diagram of 64-bit FP incrementer

5. Algorithm for 64-bit decrementer

The operation of 64-bit decrementer is similar to 32decrementer. Only the number of input bits increasesaccording to double precision, it has 1-bit exponent and 52-bit mantissa. The Figure.11block diagram of 64-bit FP decrementer.


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bit FP multiplier

bit incrementer is similar to 32-bit e number of input bits increases

bit sign bit, 11-bit The Figure.10 shows the block

bit FP incrementer

rementer is similar to 32-bit e number of input bits increases

bit sign bit, 11-bit The Figure.11 shows the


D. Data transfer instruction

This soft processor performs 5 data transfer instruction, which are Move data between registersdata to register, Move immediate data to memoryLoad. E. Proposed processor architecture The proposed system architecture is shown in Figure. 12It executes 22 different arithmetic and logical instructions such as addition, subtraction, increment, decrement, multiplication, square, ex-or, exarithmetic shift right, etc., 10 floating point instructions such as single and double precision addition, subtraction, etc.,data transfer instructions.

The following steps are performed in order to fetch instruction in memory location 87H

1. The address for the program2. Program counter places

memory location on the address bus. 3. To enable read operation

the memory read control signalmemory.

4. The instruction (58H) stored in the memory location is placed on the data bus and transferred to instruction register (IR)from memory,.

5. The instruction present in the instruction registerdecoded and executed according to the binary pattern of the instruction.


Figure.11 Block diagram of 64-bit FP decrementer

This soft processor performs 5 data transfer instruction, are Move data between registers, Move immediate

, Move immediate data to memory, Store,

. Proposed processor architecture chitecture is shown in Figure. 12.

It executes 22 different arithmetic and logical instructions subtraction, increment, decrement,

or, ex-nor, not, arithmetic shift left, 10 floating point instructions such

as single and double precision addition, subtraction, etc., and 5

performed in order to fetch the in memory location 87H

address for the program counter has to be given. places the 10-bit address 87H of the

memory location on the address bus. o enable read operation the control unit must send

emory read control signal (MEMRD=1) to

H) stored in the memory location is placed on the data bus and transferred to instruction register (IR), after getting read signal

he instruction present in the instruction register is decoded and executed according to the binary pattern


Figure.12 Block diagram of 8-bit processor

IV. SIMULATION RESULTS

Figure. 13 Simulation result of 8-bit processor (64-bit

Figure. 14 Simulation result of 8-bit processor (64-bit


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bit processor

IV. SIMULATION RESULTS

bit FP addition operation)

bit FP addition operation)

Figure. 15 Simulation result of 8-bit processor

Figure. 16 RTL of 8

V. CONCLUSION

The soft processor has been designed using verilog HDL and it is simulated using Xilinxmodules in the design were coded by using structural and behavioral modeling in verilog HDL language. It executes 22 different arithmetic and logical instructions such as addition, subtraction, increment, decrement, multiplication, square,nand, nor, or, not, ex-or, exarithmetic shift right, rotate left, rotate right, compare, logical shift left, logical shift right, add witborrow, 10 different floating point instructions such as 32floating point addition, 32-bit floating point subtraction, 32floating point multiplication, 3232-bit floating point decrement, 6464-bit floating point subtraction, 64multiplication, 64-bit floating point increment, 64point decrement and 5 data transfer instructionsprocessor which is designed operates 6.25 MHz with a minimum period of 160ns and totally 1026slices were utilized.

REFERENCES

[1]Qasem Abu Al-Haija, Hasan AlNashri, and Sultan Al-Muhaisen in “An Engineering Design of 4-Bit Special Purpose Microprogrammed Processor” Elsevier, 2013.

[2]Paul Metzgen in “A High Performance 32Programmable Logic”, ACM, 2004

[3]Lafifa Jamal, Md. Masbaul Alam, Hafiz Md. Hasan Babu“An efficient approach to design a reversible conprocessor”, Elsevier 2013.

[4]Shridhar Devamane , Akshada Hanchate ,Usha Vagare ,Shalaka Ujagare ,Pushpa Teggelli, “Design and Implementation of FPGA based Barrel shifter”, Journal of Advanced Research in Computer Engineering & Technology (IJARCET), 2015.


processor (64-bit FP addition operation)

of 8-bit processor

V. CONCLUSION

processor has been designed using verilog HDL and it is simulated using Xilinx ISE 12.2 software. All the

s in the design were coded by using structural and behavioral modeling in verilog HDL language. It executes 22 different arithmetic and logical instructions such as addition, subtraction, increment, decrement, multiplication, square, and,

or, ex-nor, arithmetic shift left, arithmetic shift right, rotate left, rotate right, compare, logical

ift left, logical shift right, add with carry, and subtract with different floating point instructions such as 32-bit

bit floating point subtraction, 32-bit floating point multiplication, 32-bit floating point increment,

bit floating point decrement, 64-bit floating point addition, bit floating point subtraction, 64-bit floating point

bit floating point increment, 64-bit floating data transfer instructions. The soft

sor which is designed operates at a frequency rate of period of 160ns and totally 1026

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