The Designer’s Guideto VHDL

Second Edition

The Morgan Kaufmann Series in Systems on SiliconSeries Editors: Peter J. Ashenden, Ashenden Designs Pty. Ltd. and Adelaide University,and Wayne Wolf, Princeton University

The rapid growth of silicon technology and the demands of applications are increasingly forcingelectronics designers to take a systems-oriented approach to design. This has led to new chal-lenges in design methodology, design automation, manufacture and test. The main challengesare to enhance designer productivity and to achieve correctness on the first pass. The MorganKaufmann Series in Systems on Silicon presents high quality, peer-reviewed books authored byleading experts in the field who are uniquely qualified to address these issues.

The Designer’s Guide to VHDL, Second EditionPeter J. Ashenden

Readings in Hardware/Software Co-DesignEdited by Giovanni De Micheli, Rolf Ernst, and Wayne Wolf

Forthcoming Titles

The System Designer's Guide to VHDL-AMS: Analog, Mixed-Signal,and Mixed-Technology ModelingPeter J. Ashenden, Gregory D. Peterson, and Darrell A. Teegarden

Rosetta User’s Guide: Model-Based Systems DesignPerry Alexander, Peter J. Ashenden, and David L. Barton

Rosetta Developer’s Guide: Semantics for Systems DesignPerry Alexander, Peter J. Ashenden, and David L. Barton

The Designer’s Guideto VHDL

Second Edition

Peter J. AshendenEDA CONSULTANT, ASHENDEN DESIGNS PTY. LTD.

VISITING RESEARCH FELLOW, ADELAIDE UNIVERSITY

Senior Editor Denise E. M. PenrosePublishing Services Manager Scott NortonAssistant Publishing Services Manager Edward WadeEditorial Assistant Courtney GarnaasSeries Art Direction, Cover Design & Photography Chen Design Associates, SFText Design Rebecca Evans & AssociatesCopyeditor Ken DellaPentaProofreader Erin MilnesPrinter Courier Corporation

This book was author typeset using FrameMaker 6.0 for Windows.

Figure 18-8 and Appendix B reprinted with permission from IEEE Std. 1076-2001, IEEE Standard VHDL Language Ref-erence Manual, Copyright 2001 by IEEE. Section C.1 of Appendix C reprinted with permission from IEEE Std. 1164-1993, IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164), Copyright 1993 byIEEE. Section C.2 of Appendix C reprinted with permission from IEEE Std. 1076.3-1997, IEEE Standard VHDL Synthe-sis Packages, Copyright 1997 by IEEE. Section C.3 of Appendix C reprinted with permission from IEEE Std. 1076.2-1996, IEEE Standard VHDL Mathematical Packages, Copyright 1997 by IEEE. The IEEE disclaims any responsibilityor liability resulting from the placement and use in the described manner.

The DLX tools, dasm, dlnk and dloc, included on the CD-ROM Copyright 2001 by Adelaide University.

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© 1996, 2002 by Academic PressAll rights reservedPublished 1996. Second edition 2002

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Library of Congress Cataloging-in-Publication Data

Ashenden, Peter J.The designer's guide to VHDL / Peter J. Ashenden.-- 2nd ed.

p. cm.Includes bibliographical references and index.ISBN 1-55860-674-2 1. VHDL (Computer hardware description language) 2. Electronic digital

computers--Computer simulation. I. Title.

TK7888.3 .A863 2002621.39'2--dc21

2001022449

This book is printed on acid-free paper.

To my wife Katrina

Foreword vii........................................................................

Foreword to the First Edition ix.......................................

Preface xix............................................................................

1 Fundamental Concepts ?..............................................

Modeling Digital Systems 2.......................................................

Domains and Levels of Modeling 4..........................................

Modeling Languages 7..............................................................

VHDL Modeling Concepts 8......................................................Elements of Behavior 9...........................................................Elements of Structure 10..........................................................Mixed Structural and Behavioral Models 12.............................Test Benches 13.......................................................................Analysis, Elaboration and Execution 14...................................

Learning a New Language: Lexical Elements andSyntax 16......................................................................................

Lexical Elements 17..................................................................Comments 17...........................................................................Identifiers 18.............................................................................Reserved Words 19..................................................................Special Symbols 20..................................................................Numbers 20..............................................................................Characters 21...........................................................................Strings 22..................................................................................Bit Strings 22............................................................................Syntax Descriptions 23.............................................................

Exercises 26.................................................................................

2 Scalar Data Types and Operations ?...........................

Constants and Variables 30........................................................

Constant and Variable Declarations 30....................................Variable Assignment 32............................................................

Scalar Types 32............................................................................Type Declarations 33................................................................Integer Types 33.......................................................................Floating-Point Types 36............................................................Physical Types 37.....................................................................Time 39.....................................................................................Enumeration Types 40..............................................................Characters 41...........................................................................Booleans 43..............................................................................Bits 44.......................................................................................Standard Logic 45.....................................................................

Type Classification 46.................................................................Subtypes 46..............................................................................Type Qualification 48................................................................Type Conversion 49..................................................................

Attributes of Scalar Types 49......................................................

Expressions and Operators 52...................................................

Exercises 54.................................................................................

3 Sequential Statements ?...............................................

If Statements 58............................................................................

Case Statements 61.....................................................................

Null Statements 66.......................................................................

Loop Statements 67.....................................................................Exit Statements 68....................................................................Next Statements 71..................................................................While Loops 72.........................................................................For Loops 74.............................................................................Summary of Loop Statements 76.............................................

Assertion and Report Statements 77.........................................

Exercises 83.................................................................................

4 Composite Data Types and Operations ?...................

Arrays 86.......................................................................................Multidimensional Arrays 88.......................................................Array Aggregates 89.................................................................Array Attributes 92....................................................................

Unconstrained Array Types 94...................................................Strings 95..................................................................................Bit Vectors 95...........................................................................Standard-Logic Arrays 96.........................................................String and Bit-String Literals 96................................................Unconstrained Array Ports 97...................................................

Array Operations and Referencing 98........................................Array Slices 100..........................................................................Array Type Conversions 101......................................................

Records 102....................................................................................Record Aggregates 104..............................................................

Exercises 105.................................................................................

5 Basic Modeling Constructs 1.......................................

Entity Declarations 108..................................................................

Architecture Bodies 110................................................................Concurrent Statements 111........................................................Signal Declarations 111..............................................................

Behavioral Descriptions 113.........................................................Signal Assignment 113...............................................................Signal Attributes 115...................................................................Wait Statements 118..................................................................Delta Delays 121........................................................................

Transport and Inertial Delay Mechanisms 124...........................Process Statements 130.............................................................Concurrent Signal Assignment Statements 131.........................Conditional Signal Assignment Statements 132.........................Selected Signal Assignment Statements 135.............................Concurrent Assertion Statements 138........................................Entities and Passive Processes 139...........................................

Structural Descriptions 140..........................................................Component Instantiation and Port Maps 141.............................

Design Processing 149..................................................................Analysis 149...............................................................................Design Libraries, Library Clauses and Use Clauses 151...........Elaboration 153...........................................................................Execution 156.............................................................................

Exercises 157.................................................................................

6 Case Study: A Pipelined Multiplier Accumulator ?....

Algorithm Outline 168....................................................................MAC Entity Declaration 170........................................................

A Behavioral Model 171.................................................................Testing the Behavioral Model 176..............................................

A Register-Transfer-Level Model 179...........................................Modules in the Register-Transfer-Level Model 181....................The Register-Transfer-Level Architecture Body 188..................Testing the Register-Transfer-Level Model 191.........................

Exercises 193.................................................................................

7 Subprograms ?..............................................................

Procedures 196..............................................................................Return Statement in a Procedure 201........................................

Procedure Parameters 202............................................................

Signal Parameters 206...............................................................Default Values 209.....................................................................Unconstrained Array Parameters 210........................................Summary of Procedure Parameters 212....................................

Concurrent Procedure Call Statements 213................................

Functions 215.................................................................................Functional Modeling 218.............................................................Pure and Impure Functions 218.................................................The Function Now 219................................................................

Overloading 220.............................................................................Overloading Operator Symbols 222...........................................

Visibility of Declarations 223........................................................

Exercises 227.................................................................................

8 Packages and Use Clauses ?.......................................

Package Declarations 232.............................................................Subprograms in Package Declarations 236...............................Constants in Package Declarations 237.....................................

Package Bodies 239.......................................................................

Use Clauses 241.............................................................................

The Predefined Package Standard 243........................................

IEEE Standard Packages 244........................................................Std_Logic_1164 Multivalue Logic System 245...........................Standard VHDL Synthesis Packages 246..................................Standard VHDL Mathematical Packages 250............................Real Number Mathematical Package 250..................................Complex Number Mathematical Package 253...........................

Exercises 255.................................................................................

9 Aliases ?.........................................................................

Aliases for Data Objects 258.........................................................

Aliases for Non-Data Items 261....................................................

Exercises 264.................................................................................

10 Case Study: A Bit-Vector Arithmetic Package ?.......

The Package Interface 268............................................................

The Package Body 271..................................................................

An ALU Using the Arithmetic Package 280.................................

Exercises 282.................................................................................

11 Resolved Signals ?......................................................

Basic Resolved Signals 286..........................................................Composite Resolved Subtypes 290............................................Summary of Resolved Subtypes 294.........................................

IEEE Std_Logic_1164 Resolved Subtypes 294...........................

Resolved Signals and Ports 297...................................................Resolved Ports 298....................................................................Driving Value Attribute 300.........................................................

Resolved Signal Parameters 300..................................................

Exercises 302.................................................................................

12 Generic Constants ?....................................................

Parameterizing Behavior 310........................................................

Parameterizing Structure 313.......................................................

Exercises 315.................................................................................

13 Generic Constants Components andConfigurations 5...............................................................

Components 318............................................................................

Component Declarations 318.....................................................Component Instantiation 319......................................................Packaging Components 321.......................................................

Configuring Component Instances 322.......................................Basic Configuration Declarations 323.........................................Configuring Multiple Levels of Hierarchy 325.............................Direct Instantiation of Configured Entities 328............................Generic and Port Maps in Configurations 329............................Deferred Component Binding 335..............................................

Configuration Specifications 337.................................................Incremental Binding 338.............................................................

Exercises 344.................................................................................

14 Generate Statements ?................................................

Generating Iterative Structures 350.............................................

Conditionally Generating Structures 355....................................Recursive Structures 359...........................................................

Configuration of Generate Statements 362.................................

Exercises 367.................................................................................

15 Case Study: The DLX Computer System ?...............

Overview of the DLX CPU 374.......................................................DLX Registers 374......................................................................DLX Instruction Set 375..............................................................Data Transfer Instructions 375...................................................Arithmetic and Logical Instructions 376......................................Control Transfer Instructions 378...............................................Instruction Encoding 379............................................................DLX External Interface 379.........................................................

A Behavioral Model 382.................................................................The DLX Types Package 382.....................................................

The DLX Entity Declaration 383.................................................The DLX Instruction Set Package 384........................................The DLX Behavioral Architecture Body 392...............................Overview of the Interpreter 393..................................................Bus Read and Write Procedures 394.........................................Resetting the Interpreter 396......................................................Fetching an Instruction 396........................................................Incrementing the PC 397............................................................Decoding the Instruction 397......................................................Executing the Instruction 398.....................................................

Testing the Behavioral Model 407................................................The Test-Bench Clock Generator 408........................................The Test-Bench Memory 408.....................................................The Test-Bench Architecture Body and Configuration 413........

A Register-Transfer-Level Model 416...........................................The Arithmetic and Logic Unit 417..............................................The Registers 421......................................................................The Register File 425.................................................................The Multiplexer 426....................................................................The Extenders 427.....................................................................The Architecture Body 428.........................................................The Controller 434......................................................................The Instruction Fetch Control Procedure 441.............................Procedures to Execute Relational Instructions 442....................Procedures to Execute Arithmetic and Logic Instructions 445...Procedures to Execute Branch Instructions 446.........................Procedures to Execute Load and Store Instructions 447...........The Configuration Declaration 450.............................................

Testing the Register-Transfer-Level Model 452..........................

Exercises 456.................................................................................

16 Guards and Blocks ?...................................................

Guarded Signals and Disconnection 460....................................

The Driving Attribute 464............................................................Guarded Ports 465.....................................................................Guarded Signal Parameters 467................................................

Blocks and Guarded Signal Assignment 469..............................Explicit Guard Signals 472..........................................................Disconnection Specifications 474...............................................

Using Blocks for Structural Modularity 475................................Generics and Ports in Blocks 478...............................................Configuring Designs with Blocks 479.........................................

Exercises 482.................................................................................

17 Access Types and Abstract Data Types ?................

Access Types 488..........................................................................Access Type Declarations and Allocators 488...........................Assignment and Equality of Access Values 490.........................Access Types for Records and Arrays 492................................

Linked Data Structures 494...........................................................Deallocation and Storage Management 498..............................

Abstract Data Types Using Packages 499...................................Container ADTs 504...................................................................Example: An Ordered-Collection ADT 504.................................

Exercises 512.................................................................................

18 Files and Input/Output ?.............................................

Files 516..........................................................................................File Declarations 516..................................................................Reading from Files 517...............................................................Writing to Files 520.....................................................................Files Declared in Subprograms 523...........................................Explicit Open and Close Operations 524....................................File Parameters in Subprograms 527.........................................Portability of Files 529................................................................

The Package Textio 529.................................................................Textio Read Operations 531.......................................................Textio Write Operations 541.......................................................Reading and Writing User-Defined Types 543...........................

Exercises 544.................................................................................

19 Case Study: Queuing Networks ?..............................

Queuing Network Concepts 550...................................................

Queuing Network Modules 551.....................................................Random Number Generator 551................................................A Package for Token and Arc Types 555...................................The Token Source Module 557..................................................The Token Sink Module 561.......................................................The Queue Module 563..............................................................The Token Server Module 569...................................................The Fork Module 571..................................................................The Join Module 575..................................................................

A Queuing Network for a Disk System 578..................................

Exercises 584.................................................................................

20 Attributes and Groups ?.............................................

Predefined Attributes 586..............................................................Attributes of Scalar Types 586....................................................Attributes of Array Types and Objects 587.................................Attributes of Signals 587.............................................................Attributes of Named Items 588...................................................

User-Defined Attributes 595..........................................................Attribute Declarations 596..........................................................Attribute Specifications 596........................................................The Attribute Foreign 606...........................................................

Groups 608.....................................................................................

Exercises 611.................................................................................

21 Miscellaneous Topics ?..............................................

Buffer and Linkage Ports 616.......................................................

Conversion Functions in Association Lists 618.........................

Postponed Processes 623.............................................................

Shared Variables 626.....................................................................

Exercises 636.................................................................................

A Synthesis 639....................................................................

Use of Data Types 640...................................................................Scalar Types 640........................................................................Composite and Other Types 641................................................

Interpretation of Standard Logic Values 642...............................

Modeling Combinatorial Logic 643...............................................

Modeling Sequential Logic 644.....................................................Modeling Edge-Triggered Logic 645...........................................Level-Sensitive Logic and Inferring Storage 647........................Modeling State Machines 649....................................................

VHDL Modeling Restrictions 650..................................................Design Units 651........................................................................Processes and Subprograms 652..............................................Concurrent Statements 652........................................................Names and Expressions 653......................................................Metacomments 654....................................................................

B The Predefined Package Standard 655...........................

C IEEE Standard Packages 659...........................................

Std_Logic_1164 Multivalue Logic System1 659..........................

Standard 1076.3 VHDL Synthesis Packages2 662......................Bit-Vector Numeric Operations 662............................................Standard-Logic-Vector Numeric Operations 665........................

Standard 1076.2 VHDL Mathematical Packages3 665................Real Mathematical Operations 665............................................Complex Mathematical Operations 667......................................

D Related Standards 671.....................................................

IEEE VHDL Standards 671.............................................................IEEE Standard 1076 VHDL 671.................................................VHDL Programming Language Interface 672.............................IEEE Standard 1076.1 VHDL-AMS 672.....................................IEEE Standard 1076.2 Mathematical Packages 673..................IEEE Standard 1076.3 Synthesis Packages 673........................IEEE Standard 1076.4 VITAL 673..............................................IEEE P1076.5 VHDL Utility Library 674......................................IEEE 1076.6 VHDL Synthesis Interoperability 674.....................IEEE P1577 Object-Oriented VHDL 675....................................IEEE P1551 System and Interface Description 676...................IEEE Standard 1164 Multivalue Logic System 676....................IEEE Standard 1029.1 WAVES 676...........................................

Other Design Automation Standards 677....................................IEEE Standard 1364 Verilog 677................................................IEEE P1364.1 Verilog Synthesis Interoperability 678.................OVI Verilog-AMS 678.................................................................IEEE Standard 1499 OMF 678...................................................SLDL Initiative 679......................................................................OVI Design Constraints 679.......................................................Virtual Socket Interface Alliance 679..........................................IEEE P1497 Standard Delay Format 680...................................OVI Advanced Library Format 680.............................................IEEE Standard 1481 Delay and Power Calculation 680.............SI2 Open Library Architecture 681.............................................

CHDStd 681................................................................................EIA-682 Electronic Design Interchange Format (EDIF) 681.......EIA-567-A Component Modeling and Interface 681...................EIA/IS-103-A Library of Parameterized Modules 682.................

E VHDL Syntax 683...............................................................Index to Syntax Rules 683..........................................................

Design File 685...............................................................................

Library Unit Declarations 685.......................................................

Declarations and Specifications 686............................................

Type Definitions 689......................................................................

Concurrent Statements 690..........................................................

Sequential Statements 692............................................................

Interfaces and Associations 693..................................................

Expressions 694.............................................................................

F Differences among VHDL-87, VHDL-93 andVHDL-2001 697......................................................................

Lexical Differences 697.................................................................

Syntactic Differences 698..............................................................

Semantic Differences 699..............................................................

Differences in the Standard Environment 700............................

VHDL-93 Facilities Not in VHDL-87 701........................................

VHDL-2001 Facilities Not in VHDL-87 or VHDL-93 701...............

Features under Consideration for Removal 701.........................

G Answers to Exercises 703................................................

H Software Guide 723...........................................................

Software Overview 723..................................................................

Installation 724...............................................................................Computer Requirements 724......................................................Installation on Linux Systems 724..............................................Installation on Windows Systems 725........................................Registration and Update of Exploration/VHDL 726....................

Example VHDL Code 727...............................................................

Exploration/VHDL Quick Start Guide 728....................................Starting Exploration 728.............................................................Source Code Analysis 729.........................................................Compilation 731..........................................................................Structural Navigation and Static Profiling 733............................Simulation 735............................................................................Process Debugging Window 735................................................State Trace Window 737............................................................Current Value Window 738.........................................................Batch Files Using TCL 739.........................................................Library System 740.....................................................................Updating, Upgrading & Further Information 741.........................Automated and Manual Updates 741.........................................Automated and Manual Upgrades 741.......................................Email and Web Addresses 741..................................................Notice Concerning Registration 741...........................................

References 743.....................................................................

Index 745...............................................................................

vii

Foreword

by Paul MenchiniMenchini & Associates, Durham, North Carolina

In the five years since the publication of the first edition of The Designer’s Guide toVHDL, the pressures on designers leading to the initial creation of VHDL have contin-ued to increase. Electronic systems have become pervasive in consumer and businessappliances, with ever-tighter constraints on cost, performance and schedule. Medicaland aircraft systems, where correctness and reliability concerns are paramount, arenow heavily reliant on digital electronic controls. New and larger field-programmabledevices have opened up entirely new application domains, with the concomitant needfor new groups of designers to learn VHDL. At the same time, the commercial lifetimeof any given design continues to shrink, as new and improved versions of or compet-itors to a product enter the marketplace with increasing rapidity.

In response, there have been many changes to VHDL. Although the base lan-guage has remained relatively stable, with the only changes being a reworking of theshared variables of VHDL-93 and a number of bug fixes and other, minor updatescoming in VHDL-2001, there has been much activity in related areas.

A number of new packages and standards built on top of the basic language havebeen developed: numeric_bit, numeric_std, math_real, math_complex and vital.VHDL-AMS, a superset of VHDL, extends VHDL to the domain of analog and mixed-signal modeling. A first-level standard synthesis subset has been defined, and workis underway to extend this definition to add more capability. These additions makeVHDL uniquely capable of the modeling required of systems on silicon.

In this second edition of The Designer’s Guide to VHDL, Dr. Ashenden builds uponthe considerable strengths of the first edition by addressing all of these changes (withthe exception of VHDL-AMS, which will be the subject of another volume in the Mor-gan Kaufmann Series in Systems on Silicon). He describes, in detail, the new

viii Foreword

packages adopted by the IEEE since the first edition, the new implementation ofshared variables adopted in 2000 and the changes coming with VHDL-2001, now inthe final stages of approval. The appendix on synthesis has been completely rewrittento correspond to IEEE Standard 1076.6, the standard synthesis subset description.

In addition, the DLX processor case study has been revised to more closely followcurrent design practices, and to allow a synthesizable version of the processor modelto be more easily derived.

Finally, this new edition is made even more valuable by the inclusion of all sourcecode on a CD-ROM, which also accesses FTL System’s Exploration simulator.

The second edition of The Designer’s Guide to VHDL sets a new standard in VHDLtexts. I am certain that you will find it a very valuable addition to your library.

ix

Foreword to the First Edition

by Paul MenchiniResearch Triangle Park, North Carolina

Digital electronic systems are increasing exponentially in their complexity over time.This fact, coupled with decreasing product lifetimes and increasing reliability require-ments, has forced designers to dramatically increase their productivity and the qualityof their designs.

VHDL was developed in response to these trends. Borrowing complexity man-agement and error detection techniques from the software engineering world, VHDLwas developed to eliminate irrelevant detail, allow technology-independent descrip-tion, catch errors earlier, and promote portable and interoperable models from thegate to the system level.

In response, EDA tools have been designed to take an ever-greater share of theburden from designers. A single representation medium can now drive design proc-esses from specification down to detailed digital design.

Originally developed as the United States Department of Defense’s standard hard-ware description language (HDL), VHDL has evolved through two additional roundsof IEEE standardization into one of the two preeminent HDLs in use throughout theworld. Continued development in the areas of detailed timing models, synthesis di-rectives, analog capabilities, and so forth mean the VHDL will continue to provide theexpressive facilities needed by state-of-the-art designs well into the next century. Newtools leveraging on VHDL’s precise definition continue to be introduced and offer in-creased simulation performance, increased synthesis capabilities, and entirely new ca-pabiliites, such as the formal verification of the functional equivalence of models.

Because VHDL uses concepts not commonly found in hardware description, de-signers approaching VHDL for the first time need a sure guide to the features usingthese concepts. One of the few books on VHDL that does not rely heavily on

x Foreword to the First Edition

experience with programming languages, A Designer’s Guide to VHDL is ideal for thenonprogrammer wishing to learn VHDL.

This book explores in detail the latest version of VHDL, VHDL-93 (IEEE Std. 1076-1993). Assuming no prior knowledge of VHDL, Professor Ashenden walks the readerthrough VHDL, first addressing simple modeling issues, then moving on to the morecomplex. As VHDL contains many features, the reader is greatly aided by the inclusionof four fully worked case studies. These case studies put VHDL’s features in contextand show how they work in concert to model digital systems of varying levels of com-plexity and varying levels of detail.

Appendices cover the use of VHDL in synthesis, as well as other standards builtupon the VHDL framework. As an aid to the experienced user of VHDL, other appen-dices contain syntax summaries and a list of differences from the initial IEEE standard,IEEE Std. 1076-1987.

As an aid to the experienced user of VHDL, appendices contain syntax summariesand a list of differences from the initial IEEE standard, IEEE Std. 1076-1987.

Welcome to VHDL!

xix

Preface

VHDL is a language for describing digital electronic systems. It arose out of the UnitedStates government’s Very High Speed Integrated Circuits (VHSIC) program. In thecourse of this program, it became clear that there was a need for a standard languagefor describing the structure and function of integrated circuits (ICs). Hence the VHSICHardware Description Language (VHDL) was developed. It was subsequently devel-oped further under the auspices of the Institute of Electrical and Electronic Engineers(IEEE) and adopted in the form of the IEEE Standard 1076, Standard VHDL LanguageReference Manual, in 1987. This first standard version of the language is often re-ferred to as VHDL-87.

Like all IEEE standards, the VHDL standard is subject to review every five years.Comments and suggestions from users of the 1987 standard were analyzed by theIEEE working group responsible for VHDL, and in 1992 a revised version of the stand-ard was proposed. This was eventually adopted in 1993, giving us VHDL-93. A sec-ond round of revision of the standard was started in 1998. That process wascompleted in 2001, giving us the current version of the language, VHDL-2001, de-scribed in this book.

VHDL is designed to fill a number of needs in the design process. First, it allowsdescription of the structure of a system, that is, how it is decomposed into subsystemsand how those subsystems are interconnected. Second, it allows the specification ofthe function of a system using familiar programming language forms. Third, as a re-sult, it allows the design of a system to be simulated before being manufactured, sothat designers can quickly compare alternatives and test for correctness without thedelay and expense of hardware prototyping. Fourth, it allows the detailed structureof a design to be synthesized from a more abstract specification, allowing designersto concentrate on more strategic design decisions and reducing time to market.

This book presents a structured guide to the modeling facilities offered by theVHDL language, showing how they can be used for the design of digital systems. Thebook does not purport to teach digital design, since that topic is large enough by itselfto warrant several textbooks covering its various aspects. Instead, the book assumes

xx Preface

that the reader has at least a basic grasp of digital design concepts, such as might begained from a first course in digital design in an engineering degree program. Someexposure to computer programming and to concepts of computer organization willalso be beneficial. This book is suitable for use in an introductory or intermediate-level course in digital or computer design. It will also serve practicing engineers whoneed to acquire VHDL fluency as part of their changing job requirements.

I am particularly pleased to be able to include this book in the Morgan KaufmannSeries in Systems on Silicon. Modeling for simulation and synthesis is a vital part of adesign methodology for large-scale systems. VHDL allows models to be expressed ata range of levels of abstraction, from gate-level up to algorithmic and architectural lev-els. It will continue to play an important role in the design of silicon-based systemsfor some time to come.

Structure of the Book

The Designer’s Guide to VHDL is organized so that it can be read linearly from frontto back. This path offers a graduated development, with each chapter building onideas introduced in the preceding chapters. Each chapter introduces a number of re-lated concepts or language facilities and illustrates each one with examples. Scatteredthroughout the book are four case studies, which bring together preceding materialin the form of extended worked examples.

Chapter 1 introduces the idea of a hardware description language and outlines thereasons for its use and the benefits that ensue. It then proceeds to introduce the basicconcepts underlying VHDL, so that they can serve as a basis for examples in subse-quent chapters. The next three chapters cover the aspects of VHDL that are most likeconventional programming languages. These may be used to describe the behaviorof a system in algorithmic terms. Chapter 2 explains the basic type system of the lan-guage and introduces the scalar data types. Chapter 3 describes the sequential controlstructures, and Chapter 4 covers composite data structures used to represent collec-tions of data elements.

In Chapter 5, the main facilities of VHDL used for modeling hardware are coveredin detail. These include facilities for modeling the basic behavioral elements in a de-sign, the signals that interconnect them and the hierarchical structure of the design.The combination of facilities described in these early chapters is sufficient for manymodeling tasks, so Chapter 6 brings them together in the first case study, in which amultiplier/accumulator circuit is designed.

The next group of chapters extends this basic set of facilities with language fea-tures that make modeling of large systems more tractable. Chapter 7 introduces pro-cedures and functions, which can be used to encapsulate behavioral aspects of adesign. Chapter 8 introduces the package as a means of collecting together relatedparts of a design or of creating modules that can be reused in a number of designs.It also describes a number of packages standardized by the IEEE for use in VHDL de-signs. Chapter 9 then covers aliases as a way of managing the large number of namesthat arise in a large model. The material in this group of chapters is brought togetherin the next case study in Chapter 10, in which a package of binary arithmetic opera-tions is developed.

Structure of the Book xxi

The third group of chapters covers advanced modeling features in VHDL.Chapter 11 deals with the important topic of resolved signals, and Chapter 12 de-scribes generic constants as a means of parameterizing the behavior and structure ofa design. While these language facilities form the basis of many real-world models,their treatment in this book is left to this late chapter. Experience has shown that theideas can be difficult to understand without a solid foundation in the more basic lan-guage aspects. Chapter 13 deals with the topics of component instantiation and con-figuration. These features are also important in large real-world models, but they canbe difficult to understand. Hence this book introduces structural modeling throughthe mechanism of direct instantiation in earlier chapters and leaves the more generalcase of component instantiation and configuration until this later chapter. InChapter 14, generated regular structures are covered. Chapter 15 brings the materialin this group of chapters together in the third case study, in which a register-transfer-level model of a CPU is described.

The fourth group of chapters covers language facilities generally used for system-level modeling. Chapter 16 is a detailed treatment of the related topics of guardedsignals and blocks. Chapter 17 introduces the notion of access types (or pointers) anduses them to develop linked data structures. This leads to a discussion of abstract datatypes as a means of managing the complexity associated with linked data structures.Chapter 18 covers the language facilities for input and output using files, includingbinary files and text files. Chapter 19 is a case study in which a queuing networkmodel of a computer system is developed.

The final pair of chapters draws the tour of VHDL to a close by covering the re-maining language facilities. Chapter 20 describes the attribute mechanism as a meansof annotating a design with additional information. Chapter 21 is a miscellany of ad-vanced topics not covered in the previous chapters.

Whereas a complete reading of this book provides a complete coverage of thelanguage, there are several shorter paths through the material. Some suggested min-imal paths for readers with different requirements are as follows.

• For an introductory course in digital modeling using VHDL: Chapters 1 to 5, 7,8, 11 and 12, plus the case study in Chapter 6. Chapters 9 and 10 may be in-cluded if time permits.

• For a more advanced course: add Chapters 13 and 14, and as much of the casestudy in Chapter 15 as time permits.

• For readers proficient in using conventional programming languages: treatChapters 2 to 4 as review.

• For readers with some previous introductory-level background in VHDL: treatChapters 1 to 4 as review.

Each chapter in the book is followed by a set of exercises designed to help thereader develop understanding of the material. Where an exercise relates to a partic-ular topic described in the chapter, the section number is included in square brackets.An approximate “difficulty” rating is also provided, expressed using the followingsymbols:

➊ quiz-style exercise, testing basic understanding

xxii Preface

➋ basic modeling exercise—10 minutes to half an hour effort

➌ advanced modeling exercise—one half to two hours effort

➍ modeling project—half a day or more effort

Answers for the first category of exercises are provided in Appendix G. The re-maining categories involve developing VHDL models. Readers are encouraged to testcorrectness of their models by running them on a VHDL simulator. This is a muchmore effective learning exercise than comparing paper models with paper solutions.

One pervasive theme running through the presentation in this book is that mod-eling a system using a hardware description language is essentially a software designexercise. This implies that good software engineering practice should be applied.Hence the treatment in this book draws directly from experience in software engineer-ing. There are numerous hints and techniques from small-scale and large-scale soft-ware engineering presented throughout the book, with the sincere intention that theymight be of use to readers.

Changes in the Second Edition

The first edition of this book was published in 1995, just as VHDL-93 was gaining ac-ceptance. This edition is updated to reflect the changes in VHDL-2001. Many of thechanges in the language standard correct ambiguities in the previous standard thatcaused incompatibility between VHDL tools from different vendors. There are alsochanges that enhance the usability of the language. The text and examples in thisbook have been revised where necessary to reflect the changes in the language. Fur-thermore, since publication of the first edition, a number of VHDL-related standardshave been published and gained widespread acceptance. Chapter 8 has been extend-ed to include a description of the IEEE standard synthesis and math packages, andAppendix A has been completely rewritten to cover the IEEE Synthesis Interoperabil-ity Standard. The DLX case study in Chapter 15 has undergone a major revision inthe light of these developments. Appendix D has also been significantly revised andextended to reflect the current vast array of standards in use in the EDA community.

New to this second edition is the inclusion of a CD-ROM, containing source codeof all of the example models in the book, supplemental resources related to the textand examples and the Exploration VHDL analyzer and simulator tools from FTL Sys-tems, Inc. These tools allow the reader to experiment with the example models andto verify designs suggested in the exercises. An introductory Quick Start Guide is in-cluded in Appendix H (see Section H.4).

Resources for Help and Information

While this book attempts to be comprehensive in its coverage of VHDL, there will nodoubt be questions that it does not answer. For these, the reader will need to seekother resources. A valuable source of experience and advice, often overlooked, isone’s colleagues, either at the workplace or in user groups. User groups generallyhold regular meetings that either formally or informally include a time for questionsand answers. Many also run e-mail lists and on-line discussion groups for problemsolving. There are a number of VHDL user groups around the world, many operating

Acknowledgments xxiii

under the auspices of the VHDL International organization (www.vhdl.org). The partof the organization for VHDL users is the VHDL International Users’ Forum (www.vh-dl.org/viuf/). It sponsors conferences, design contests and other activities.

VHDL International is one of a number of organizations that sponsor the EDA In-dustry Working Groups Web server (www.eda.org). The server has links to Webpages and repositories of several VHDL standards groups and user groups.

Readers who have access to the Usenet electronic news network will find thenews group comp.lang.vhdl a valuable resource. This discussion group is a source ofannouncements, sample models, questions and answers and useful software. Partic-ipants include VHDL users and people actively involved in the language standardworking group and in VHDL tool development. The “frequently asked questions”(FAQ) file for this group is a mine of useful pointers to books, products and otherinformation. It is archived at www.eda.org.

One resource that must be mentioned is IEEE Standard 1076, IEEE Standard VHDLLanguage Reference Manual, sometimes referred to as the “VHDL Bible.” It is the au-thoritative source of information about VHDL. However, since it is a definitional doc-ument, not a tutorial, it is written in a complex legalistic style. This makes it verydifficult to use to answer the usual questions that arise when writing VHDL models.It should only be used once you are somewhat familiar with VHDL. It can be orderedfrom the IEEE at standards.ieee.org.

This book contains numerous examples of VHDL models that may also serve asa resource for resolving questions. The VHDL source code for these examples andthe case studies, as well as other related information, is available for on-line access at

www.mkp.com/vhdl2e

Although I have been careful to avoid errors in the example code, there are nodoubt some that I have missed. I would be pleased to hear about them, so that I cancorrect them in the on-line code and in future printings of this book. Errata and gen-eral comments can be e-mailed to me at

peter@ashenden.com.au

Acknowledgments

The seeds for this book go back to 1990 when I developed a brief set of notes, TheVHDL Cookbook, for my computer architecture class at the University of Adelaide. Atthe time, there were few books on VHDL available, so I made my booklet availablefor on-line access. News of its availability spread quickly around the world, and with-in days, my e-mail in-box was bursting. At the time of writing this, 10 years later, Istill regularly receive messages about the Cookbook. Many of the respondents urgedme to write a full textbook version. With that encouragement, I embarked upon theexercise that led to the first edition of this book. I am grateful to the many engineers,students and teachers around the world who gave me that impetus, and who madethe first edition such a success. I hope this second edition will continue to meet theneed for a comprehensive guide to VHDL.

In the first edition, I had the opportunity to extend thanks to the many peoplewho assisted in development of the book. They included my colleagues at the Uni-

xxiv Preface

versity of Adelaide; my research collaborator, Phil Wilsey, and his students at the Uni-versity of Cincinnati; the staff then at Morgan Kaufmann Publishers, in particular BruceSpatz and Cheri Palmer; the reviewers of the manuscript for the first edition, namely,Poras Balsara of University of Texas, Paul Menchini of Menchini & Associates, DavidPitts of GTE Labs and University of Lowell and Philip Wilsey of University of Cincin-nati; David Bishop for his contribution to the material on synthesis and Model Tech-nology, Inc., for use of their V-System VHDL analyzer and simulator to check theexample models. I remain grateful to all of these people and organizations for theirvaluable contributions to the first edition.

Since then, I have had the good fortunate to continue working with many people,leading to this second edition. I would like to express my sincere thanks to my re-search collaborators and my colleagues in the EDA standards community, all of whomcontribute to a lively intellectual environment in which VHDL plays an important role.They are too numerous to name individually, but I must single out Phil Wilsey for hissupport and convivial times over good coffee around the world and Perry Alexanderfor allowing me to take over his home office to edit drafts while traveling. I continueto enjoy an excellent working relationship with the staff at Morgan Kaufmann Pub-lishers, and especially with Senior Editor Denise Penrose. The quality production ofthis book is due to their efforts. Thanks are also due to John Willis and his team atFTL Systems for VHDL tools for testing the example code and to include on theCD-ROM.

The first edition was dedicated to my wife Katrina. As I said in the first editionpreface, I used to think that authors dedicating their books to their partners was some-what contrived, but that Katrina’s understanding, encouragement and support taughtme otherwise. I remain deeply grateful for her continued support and am honoredto dedicate also this second edition to her.

Fundamental Concepts

In this introductory chapter, we describe what

we mean by digital system modeling and see

why modeling and simulation are an important

part of the design process. We see how the

hardware description language VHDL can be

used to model digital systems and introduce

some of the basic concepts underlying the lan-

guage. We complete this chapter with a de-

scription of the basic lexical and syntactic

elements of the language, to form a basis for the

detailed descriptions of language features that

follow in later chapters.

2 Chapter 1 — Fundamental Concepts

1.1 Modeling Digital Systems If we are to discuss the topic of modeling digital systems, we first need to agree onwhat a digital system is. Different engineers would come up with different definitions,depending on their background and the field in which they were working. Some mayconsider a single VLSI circuit to be a self-contained digital system. Others might takea larger view and think of a complete computer, packaged in a cabinet with peripheralcontrollers and other interfaces.

For the purposes of this book, we include any digital circuit that processes orstores information as a digital system. We thus consider both the system as a wholeand the various parts from which it is constructed. Therefore, our discussions covera range of systems from the low-level gates that make up the components to the top-level functional units.

If we are to encompass this range of views of digital systems, we must recognizethe complexity with which we are dealing. It is not humanly possible to comprehendsuch complex systems in their entirety. We need to find methods of dealing with thecomplexity, so that we can, with some degree of confidence, design components andsystems that meet their requirements.

The most important way of meeting this challenge is to adopt a systematic meth-odology of design. If we start with a requirements document for the system, we candesign an abstract structure that meets the requirements. We can then decomposethis structure into a collection of components that interact to perform the same func-tion. Each of these components can in turn be decomposed until we get to a levelwhere we have some ready-made, primitive components that perform a requiredfunction. The result of this process is a hierarchically composed system, built fromthe primitive elements.

The advantage of this methodology is that each subsystem can be designed inde-pendently of others. When we use a subsystem, we can think of it as an abstractionrather than having to consider its detailed composition. So at any particular stage inthe design process, we only need to pay attention to the small amount of informationrelevant to the current focus of design. We are saved from being overwhelmed bymasses of detail.

We use the term model to mean our understanding of a system. The model rep-resents that information which is relevant and abstracts away from irrelevant detail.The implication of this is that there may be several models of the same system, sincedifferent information is relevant in different contexts. One kind of model might con-centrate on representing the function of the system, whereas another kind might rep-resent the way in which the system is composed of subsystems. We will come backto this idea in more detail in the next section.

There are a number of important motivations for formalizing this idea of a model.First, when a digital system is needed, the requirements of the system must be speci-fied. The job of the engineers is to design a system that meets these requirements.To do that, they must be given an understanding of the requirements, hopefully in away that leaves them free to explore alternative implementations and to choose thebest according to some criteria. One of the problems that often arises is that require-ments are incompletely and ambiguously spelled out, and the customer and the de-

1.1 Modeling Digital Systems 3

sign engineers disagree on what is meant by the requirements document. Thisproblem can be avoided by using a formal model to communicate requirements.

A second reason for using formal models is to communicate understanding of thefunction of a system to a user. The designer cannot always predict every possible wayin which a system may be used, and so is not able to enumerate all possible behaviors.If the designer provides a model, the user can check it against any given set of inputsand determine how the system behaves in that context. Thus a formal model is aninvaluable tool for documenting a system.

A third motivation for modeling is to allow testing and verification of a design us-ing simulation. If we start with a requirements model that defines the behavior of asystem, we can simulate the behavior using test inputs and note the resultant outputsof the system. According to our design methodology, we can then design a circuitfrom subsystems, each with its own model of behavior. We can simulate this com-posite system with the same test inputs and compare the outputs with those of theprevious simulation. If they are the same, we know that the composite system meetsthe requirements for the cases tested. Otherwise we know that some revision of thedesign is needed. We can continue this process until we reach the bottom level inour design hierarchy, where the components are real devices whose behavior weknow. Subsequently, when the design is manufactured, the test inputs and outputsfrom simulation can be used to verify that the physical circuit functions correctly. Thisapproach to testing and verification of course assumes that the test inputs cover all ofthe circumstances in which the final circuit will be used. The issue of test coverageis a complex problem in itself and is an active area of research.

A fourth motivation for modeling is to allow formal verification of the correctnessof a design. Formal verification requires a mathematical statement of the requiredfunction of a system. This statement may be expressed in the notation of a formallogic system, such as temporal logic. Formal verification also requires a mathematicaldefinition of the meaning of the modeling language or notation used to describe adesign. The process of verification involves application of the rules of inference ofthe logic system to prove that the design implies the required function. While formalverification is not yet in everyday use, it is an active area of research. There havealready been significant demonstrations of formal verification techniques in real de-sign projects, and the promise for the future is bright.

One final, but equally important, motivation for modeling is to allow automaticsynthesis of circuits. If we can formally specify the function required of a system, itis in theory possible to translate that specification into a circuit that performs the func-tion. The advantage of this approach is that the human cost of design is reduced, andengineers are free to explore alternatives rather than being bogged down in designdetail. Also, there is less scope for errors being introduced into a design and not beingdetected. If we automate the translation from specification to implementation, we canbe more confident that the resulting circuit is correct.

The unifying factor behind all of these arguments is that we want to achieve max-imum reliability in the design process for minimum cost and design time. We needto ensure that requirements are clearly specified and understood, that subsystems areused correctly and that designs meet the requirements. A major contributor to exces-sive cost is having to revise a design after manufacture to correct errors. By avoiding

4 Chapter 1 — Fundamental Concepts

errors, and by providing better tools for the design process, costs and delays can becontained.

1.2 Domains and Levels of ModelingIn the previous section, we mentioned that there may be different models of a system,each focusing on different aspects. We can classify these models into three domains:function, structure and geometry. The functional domain is concerned with the op-erations performed by the system. In a sense, this is the most abstract domain of de-scription, since it does not indicate how the function is implemented. The structuraldomain deals with how the system is composed of interconnected subsystems. Thegeometric domain deals with how the system is laid out in physical space.

Each of these domains can also be divided into levels of abstraction. At the toplevel, we consider an overview of function, structure or geometry, and at lower levelswe introduce successively finer detail. Figure 1-1 (devised by Gajski and Kuhn, seereference [6]) represents the domains on three independent axes and represents thelevels of abstraction by the concentric circles crossing each of the axes.

Let us look at this classification in more detail, showing how at each level we cancreate models in each domain. As an example, we consider a single-chip microcon-troller system used as the controller for some measurement instrument, with data in-put connections and some form of display outputs.

FIGURE 1-1

Domains and levels of abstraction. The radial axes show the three different domains of modeling. Theconcentric rings show the levels of abstraction, with the more abstract levels on the outside and moredetailed levels toward the center.

Processor-Memory-Switch

FunctionalStructural

Geometric

Register-Transfer

Gate

Transistor

Polygons

Sticks

Standard Cells

Floor Plan

Algorithm

Register-Transfer Language

Boolean Equation

Differential Equation

1.2 Domains and Levels of Modeling 5

At the most abstract level, the function of the entire system may be described interms of an algorithm, much like an algorithm for a computer program. This level offunctional modeling is often called behavioral modeling, a term we shall adopt whenpresenting abstract descriptions of a system’s function. A possible algorithm for ourinstrument controller is shown in Figure 1-2. This model describes how the controllerrepeatedly scans each data input and writes a scaled display of the input value.

At this top level of abstraction, the structure of a system may be described as aninterconnection of such components as processors, memories and input/output de-vices. This level is sometimes called the Processor Memory Switch (PMS) level, namedafter the notation used by Bell and Newell (see reference [2]). Figure 1-3 shows astructural model of the instrument controller drawn using this notation. It consists ofa processor connected via a switch to a memory component and to controllers for thedata inputs and display outputs.

In the geometric domain at this top level of abstraction, a system to be implement-ed as a VLSI circuit may be modeled using a floor plan. This shows how the compo-nents described in the structural model are arranged on the silicon die. Figure 1-4shows a possible floor plan for the instrument controller chip. There are analogousgeometric descriptions for systems integrated in other media. For example, a personalcomputer system might be modeled at the top level in the geometric domain by anassembly diagram showing the positions of the motherboard and plug-in expansionboards in the desktop cabinet.

FIGURE 1-2

loopfor each data input loop

read the value on this input;scale the value using the current scale factor for this input;convert the scaled value to a decimal string;write the string to the display output corresponding to this input;

end loop;wait for 10 ms;

end loop;

An algorithm for a measurement instrument controller.

FIGURE 1-3

A PMS model of the controller structure. It is constructed from a processor (P), a memory (M), an in-terconnection switch (S) and two input/output controllers (Kio).

inputs

outputs

P M

Kio

Kio

S

6 Chapter 1 — Fundamental Concepts

FIGURE 1-4

A floor plan model of the controller geometry.

The next level of abstraction in modeling, depicted by the second ring inFigure 1-1, describes the system in terms of units of data storage and transformation.In the structural domain, this is often called the register-transfer level, composed of adata path and a control section. The data path contains data storage registers, anddata is transferred between them through transformation units. The control sectionsequences operation of the data path components. For example, a register-transfer-level structural model of the processor in our controller is shown in Figure 1-5.

In the functional domain, a register-transfer language (RTL) is often used to spec-ify the operation of a system at this level. Storage of data is represented using registervariables, and transformations are represented by arithmetic and logical operators.For example, an RTL model for the processor in our example controller might includethe following description:

MAR ← PC, memory_read ← 1PC ← PC + 1wait until ready = 1IR ← memory_datamemory_read ← 0

This section of the model describes the operations involved in fetching an instruc-tion from memory. The contents of the PC register are transferred to the memory ad-dress register, and the memory_read signal is asserted. Then the value from the PCregister is transformed (incremented in this case) and transferred back to the PC reg-ister. When the ready input from the memory is asserted, the value on the memorydata input is transferred to the instruction register. Finally, the memory_read signal isnegated.

In the geometric domain, the kind of model used depends on the physical medi-um. In our example, standard library cells might be used to implement the registersand data transformation units, and these must be placed in the areas allocated in thechip floor plan.

Pad Frame

SP

Kio (in)

M

Kio (out)

1.3 Modeling Languages 7

The third level of abstraction shown in Figure 1-1 is the conventional logic level.At this level, structure is modeled using interconnections of gates, and function ismodeled by Boolean equations or truth tables. In the physical medium of a customintegrated circuit, geometry may be modeled using a virtual grid, or “sticks,” notation.

At the most detailed level of abstraction, we can model structure using individualtransistors, function using the differential equations that relate voltage and current inthe circuit, and geometry using polygons for each mask layer of an integrated circuit.Most designers do not need to work at this detailed level, as design tools are availableto automate translation from a higher level.

1.3 Modeling LanguagesIn the previous section, we saw that different kinds of models can be devised to rep-resent the various levels of function, structure and physical arrangement of a system.There are also different ways of expressing these models, depending on the use madeof the model.

As an example, consider the ways in which a structural model may be expressed.One common form is a circuit schematic. Graphical symbols are used to representsubsystems, and instances of these are connected using lines that represent wires.This graphical form is generally the one preferred by designers. However, the samestructural information can be represented textually in the form of a net list.

FIGURE 1-5

A register-transfer-level structural model of the controller processor. It consists of a general-purpose reg-ister (GPR) file; registers for the program counter (PC), memory address (MAR), memory data (MDR),temporary values (Temp) and fetched instructions (IR); an arithmetic unit; bus drivers and the controlsection.

Temp

GPR (0 to 31)

Control Section

PC

IR MAR

MDR

Bus Drivers

8 Chapter 1 — Fundamental Concepts

When we move into the functional domain, we usually see textual notations usedfor modeling. Some of these are intended for use as specification languages, to meetthe need for describing the operation of a system without indicating how it might beimplemented. These notations are usually based on formal mathematical methods,such as temporal logic or abstract state machines. Other notations are intended forsimulating the system for test and verification purposes and are typically based onconventional programming languages. Yet other notations are oriented toward hard-ware synthesis and usually have a more restricted set of modeling facilities, since someprogramming language constructs are difficult to translate into hardware.

The purpose of this book is to describe the modeling language VHDL. VHDL in-cludes facilities for describing structure and function at a number of levels, from themost abstract down to the gate level. It also provides an attribute mechanism that canbe used to annotate a model with information in the geometric domain. VHDL is in-tended, among other things, as a modeling language for specification and simulation.We can also use it for hardware synthesis if we restrict ourselves to a subset that canbe automatically translated into hardware.

1.4 VHDL Modeling ConceptsIn the previous section, we looked at the three domains of modeling: function, struc-ture and geometry. In this section, we look at the basic modeling concepts in eachof these domains and introduce the corresponding VHDL elements for describingthem. This will provide a feel for VHDL and a basis from which to work in later chap-ters. As an example, we look at ways of describing a four-bit register, shown inFigure 1-6.

Using VHDL terminology, we call the module reg4 a design entity, and the inputsand outputs are ports. Figure 1-7 shows a VHDL description of the interface to thisentity. This is an example of an entity declaration. It introduces a name for the entityand lists the input and output ports, specifying that they carry bit values (‘0’ or ‘1’) intoand out of the entity. From this we see that an entity declaration describes the externalview of the entity.

FIGURE 1-6

A four-bit register module. The register is named reg4 and has six inputs, d0, d1, d2, d3, en and clk, andfour outputs, q0, q1, q2 and q3.

reg4

d0 q0q1q2q3

d1d2d3

enclk

1.4 VHDL Modeling Concepts 9

FIGURE 1-7

entity reg4 isport ( d0, d1, d2, d3, en, clk : in bit;

q0, q1, q2, q3 : out bit );end entity reg4;

A VHDL entity description of a four-bit register.

Elements of Behavior

In VHDL, a description of the internal implementation of an entity is called an archi-tecture body of the entity. There may be a number of different architecture bodies ofthe one interface to an entity, corresponding to alternative implementations that per-form the same function. We can write a behavioral architecture body of an entity,which describes the function in an abstract way. Such an architecture body includesonly process statements, which are collections of actions to be executed in sequence.These actions are called sequential statements and are much like the kinds of state-ments we see in a conventional programming language. The types of actions that canbe performed include evaluating expressions, assigning values to variables, condition-al execution, repeated execution and subprogram calls. In addition, there is a sequen-tial statement that is unique to hardware modeling languages, the signal assignmentstatement. This is similar to variable assignment, except that it causes the value on asignal to be updated at some future time.

To illustrate these ideas, let us look at a behavioral architecture body for the reg4entity, shown in Figure 1-8. In this architecture body, the part after the first begin key-word includes one process statement, which describes how the register behaves. Itstarts with the process name, storage, and finishes with the keywords end process.

The process statement defines a sequence of actions that are to take place whenthe system is simulated. These actions control how the values on the entity’s portschange over time; that is, they control the behavior of the entity. This process canmodify the values of the entity’s ports using signal assignment statements.

The way this process works is as follows. When the simulation is started, the sig-nal values are set to ‘0’, and the process is activated. The process’s variables (listedafter the keyword variable) are initialized to ‘0’, then the statements are executed inorder. The first statement is a condition that tests whether the values of the en andclk signals are both ‘1’. If they are, the statements between the keywords then andend if are executed, updating the process’s variables using the values on the input sig-nals. After the conditional if statement, there are four signal assignment statementsthat cause the output signals to be updated 5 ns later.

When all of these statements in the process have been executed, the processreaches the wait statement and suspends; that is, it becomes inactive. It stays suspend-ed until one of the signals to which it is sensitive changes value. In this case, the proc-ess is sensitive to the signals d0, d1, d2, d3, en and clk, since they are listed in the waitstatement. When one of these changes value, the process is resumed. The statementsare executed again, starting from the keyword begin, and the cycle repeats. Noticethat while the process is suspended, the values in the process’s variables are not lost.This is how the process can represent the state of a system.

10 Chapter 1 — Fundamental Concepts

Elements of Structure

An alternative way of describing the implementation of an entity is to specify how itis composed of subsystems. We can give a structural description of the entity’s im-plementation. An architecture body that is composed only of interconnected subsys-tems is called a structural architecture body. Figure 1-9 shows how the reg4 entitymight be composed of latches and gates. If we are to describe this in VHDL, we willneed entity declarations and architecture bodies for the subsystems, shown inFigure 1-10.

Figure 1-11 is a VHDL architecture body declaration that describes the structureshown in Figure 1-9. The signal declaration, before the keyword begin, defines theinternal signals of the architecture. In this example, the signal int_clk is declared tocarry a bit value (‘0’ or ‘1’). In general, VHDL signals can be declared to carry arbi-trarily complex values. Within the architecture body the ports of the entity are alsotreated as signals.

In the second part of the architecture body, a number of component instances arecreated, representing the subsystems from which the reg4 entity is composed. Eachcomponent instance is a copy of the entity representing the subsystem, using the cor-responding basic architecture body. (The name work refers to the current working li-brary, in which all of the entity and architecture body descriptions are assumed to beheld.)

The port map specifies the connection of the ports of each component instanceto signals within the enclosing architecture body. For example, bit0, an instance ofthe d_latch entity, has its port d connected to the signal d0, its port clk connected tothe signal int_clk and its port q connected to the signal q0.

FIGURE 1-8

architecture behav of reg4 isbegin

storage : process isvariable stored_d0, stored_d1, stored_d2, stored_d3 : bit;

begin if en = '1' and clk = '1' then

stored_d0 := d0;stored_d1 := d1;stored_d2 := d2;stored_d3 := d3;

end if;q0

1.4 VHDL Modeling Concepts 11

FIGURE 1-9

A structural composition of the reg4 entity.

FIGURE 1-10

entity d_latch isport ( d, clk : in bit; q : out bit );

end d_latch;

architecture basic of d_latch isbegin

latch_behavior : process isbegin

if clk = '1' thenq

12 Chapter 1 — Fundamental Concepts

(continued from page 11)

entity and2 isport ( a, b : in bit; y : out bit );

end and2;

architecture basic of and2 isbegin

and2_behavior : process isbegin

y

1.4 VHDL Modeling Concepts 13

stances. The control section is described behaviorally, using a process that assigns tothe control signals for the data path.

Test Benches

In our introductory discussion, we mentioned testing through simulation as an impor-tant motivation for modeling. We often test a VHDL model using an enclosing modelcalled a test bench. The name comes from the analogy with a real hardware testbench, on which a device under test is stimulated with signal generators and observedwith signal probes. A VHDL test bench consists of an architecture body containingan instance of the component to be tested and processes that generate sequences ofvalues on signals connected to the component instance. The architecture body mayalso contain processes that test that the component instance produces the expected

FIGURE 1-12

entity multiplier isport ( clk, reset : in bit;

multiplicand, multiplier : in integer;product : out integer );

end entity multiplier;

––––––––––––––––––––––––––––––––––––––––––––––––––––

architecture mixed of multiplier is

signal partial_product, full_product : integer;signal arith_control, result_en, mult_bit, mult_load : bit;

begin –– mixed

arith_unit : entity work.shift_adder(behavior)port map ( addend => multiplicand, augend => full_product,

sum => partial_product,add_control => arith_control);

result : entity work.reg(behavior)port map ( d => partial_product, q => full_product,

en => result_en, reset => reset);

multiplier_sr : entity work.shift_reg(behavior)port map ( d => multiplier, q => mult_bit,

load => mult_load, clk => clk);

product

14 Chapter 1 — Fundamental Concepts

values on its output signals. Alternatively, we may use the monitoring facilities of asimulator to observe the outputs.

A test bench model for the behavioral implementation of the reg4 register isshown in Figure 1-13. The entity declaration has no port list, since the test bench isentirely self-contained. The architecture body contains signals that are connected tothe input and output ports of the component instance dut, the device under test. Theprocess labeled stimulus provides a sequence of test values on the input signals byperforming signal assignment statements, interspersed with wait statements. Eachwait statement specifies a 20 ns pause during which the register device determines itsoutput values. We can use a simulator to observe the values on the signals q0 to q3to verify that the register operates correctly. When all of the stimulus values havebeen applied, the stimulus process waits indefinitely, thus completing the simulation.

Analysis, Elaboration and Execution

One of the main reasons for writing a model of a system is to enable us to simulateit. This involves three stages: analysis, elaboration and execution. Analysis and elab-oration are also required in preparation for other uses of the model, such as logic syn-thesis.

In the first stage, analysis, the VHDL description of a system is checked for variouskinds of errors. Like most programming languages, VHDL has rigidly defined syntaxand semantics. The syntax is the set of grammatical rules that govern how a modelis written. The rules of semantics govern the meaning of a program. For example, it

FIGURE 1-13

entity test_bench isend entity test_bench;

architecture test_reg4 of test_bench is

signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;

begin

dut : entity work.reg4(behav)port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 );

stimulus : process isbegin

d0

1.4 VHDL Modeling Concepts 15

makes sense to perform an addition operation on two numbers but not on two proc-esses.

During the analysis phase, the V