re-configurable soc design platformtwins.ee.nctu.edu.tw/courses/soc_sys_overview_04fall... ·...

2003/12/12 Platform-based SoC Design 1

Re-configurable SoC Design Platform

ChihChih--Wei LiuWei Liu

VLSI Signal Processing GroupDepartment of Electronics Engineering

National Chiao Tung University, Taiwan, R.O.C.E-mail: [email protected]


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Outline• Introduction• Configurable Platform• Example• Conclusion


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Silicon Pendulum• standardization

flexibilitytime to marketcost effectiveness

• customizationperformancedifferentiationvalue addition

ASIC

ProgrammableProcessors

ConfigurableHardware

Flexibility

Per

form

ance

(spe

ed, p

ower

& a

rea,

etc

)


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SoC: System on Chip• System

– A collection of all kinds of components and/or subsystems that are appropriately interconnected to perform the specified functions for end users.

• SoC– Hardware:

• Analog: ADC/DAC, RF, …• Digital: Processor, Interface, Accelerator, …• Storage: SRAM, DRAM, Flash, ROM, …

– Software:• RTOS, Driver, Application, …


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Example: Mobile PhoneSource: EI-SONICS

• Voice only; 2 processors• 4 year product life cycle• Short talk time

Yesterday

DSP

Radio

FlashMemory

Processor

• Voice, data, video, SMS• <12 month product life cycle• Lower power; longer talk

time

Today

• 5 Processors• Memory• Graphics• Bluetooth• GPS• Radio

Single Chip


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SOC Complexity / AbstractionYesterday Today

•Processor-centric (1 or 2)•Simple I/O•Manageable Complexity

•Many processing units•Large amount of I/O•Overwhelming Complexity!

Source: EI-SONICS


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Conquer the SoC Complexity• Use a known real entity

– A pre-designed component (IP, VC reuse)– A platform (architecture reuse)

• Partition– Based on functionality– Hardware and software

• Modeling– At different level– Consistent and accurate


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IP, VC, PE,…,• Memory controller• Interrupt controller• Power management controller• Internal memories• Bridges• Caches• Other functions


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Why Platform-based Design?• Market needs

– Diverse products in various application domains

– Short development cycle– Producing a feasible design– Cost down– Reusing architecture and components of

hardware and software designs


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Platform• A platform is a suite of reusable parts (IP)

of many system designs in a limited spectrum of applications

Memory(shared data)

Peripheral IP

Peripheral Bus

Peripheral IP

Peripheral IPPeripheral IP

System IP

System IP

ProcessorMemory(OS/drivers/program)

Co-Processor

Bridge

Bridge Peripheral Bus

I/O I/O

I/O I/O

Source: SOC Design Overview /MOE, R.O.C.


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Platform-based Methodology• Significant element of Plug-and-Play• VCs with Standard interface• Well-defined backbone, interconnection

network• Configurable VCs, or IPs• High-level system verification• Hardware/software codesign• System-level Virtual prototyping for

performance evaluation


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(Re-)Configurable Hardware• Configurable hardware

some functions can adapt to precisely fit a problem, either– statically (off-line or just at the design time with the

support of a compiler a/o a hardware generator)– dynamically (at run-time involving a local controller or a

host processor with a memory subsystem, even with the OS support)

• Reconfigurable hardwarethe functions can be changed after fabrication or shipment (i.e. field configurable)


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Configurability Metrics• Structural

– PE only– interconnection only– both

• Temporal – once (design time)– statically scheduled (run time)– dynamically scheduled (run time)– evolutionary (run time)

• Spatial (minimum addressable configuration point)

– full– partial


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Why Configurable?• All IPs are typically customized to meet

specific SoC specification• Software upgradability• Short product cycles• E.g. External memory controller supports

– memory types (sync. Or async.)– Sizes,– Widths,– Banks,– Etc.


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Benefit of configurable platform

Source: K. Sekar, et al., “Dynamic Platform Management for configurable Platform-Based system-on-chips, ICCAD’03


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General-Purpose Configurable Platform

• Design-time configurable– Xtensa, Tensilica– PICO, HP LAB– Excalibur, Altera

• Run-time Configurable– SA-1110, Intel– M-Core


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Domain-Specific Platform• Radio Processor, outer receiver for

radio access• Channel Processor, for radio channel-

related signal processing• Intel IXA, network Processor• Trimedia for multimedia processor• …• Cost to develop new platform from one

domain to another is substantial.


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Dynamic Platform Management (DPM)• Components:

– Configurable processors,– Parameterized caches,– Configurable memory hierarchies,– Configurable bus architecture,– Programmable logic,– Parameterized co-processors,– …

• DPM: – a customized software to characterize each component

within the platform in order to optimally manage and configure platform resources


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Dynamic platform management


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General-Purpose Metamer• PE granularity

(usually imply # of functionalities)

• Interconnection routability– neighbor (1-D) / mesh (2-D)– crossbar– bus

• Initialization mechanism• …

I/O

global interconnection

interconnect interconnect

interconnect interconnectinterconnect

interconnect

Registers Registers Registers

PE PE PE PE

PE PE PE PE

PE PE PE PE

I/O I/O

I/O


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PE Granularity• Smallest unit of the reconfigurable fabric that can be

reprogrammed• tradeoffs between flexibility and reconfiguration

overhead

AG

MEMc(n)

AG

MEMy(n)

MAC

x(n)

CLBCLB

CLB CLB

MUX

reg0

reg1

Adder

Buffer

Reconfigurable Dataflow Reconfigurable Datapath Reconfigurable Logic


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SystemC-Based Computing Platform for Configurable Baseband SoC

Radio Processor

Advanced Signal Processing Dept.Advanced Signal Processing Dept.SoCSoC Technology CenterTechnology Center

Industrial Technology Research InstituteIndustrial Technology Research Institute


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Outline• Introduction• A Configurable Architecture• A Configurable Coprocessing Datapath• Virtual Prototyping• Summary


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Technology and System Outlook

Wireless Information

SocietyS-UMTS

Satellite Broadband

DAB

4G and BeyondSatelliteDAB-T

DAB-S

Broadcasting

GSM

GPRS/EDGE

UMTS

UMTS++

Cellular

xMDS

MWS

Broadband WFA

Wireless Local Loop

Personal Area Networks

Baby LANs

Wireless Area Networks

Broadband W-LAN

Bluetooth

IR

Indoor

OFDM+WCDMA2007

2007

20072000

2000

Re-configurable Radio

2000


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Trend• Platform-based Configurable Computing Platform

for Multi-Standards Baseband SoC– IP reuse– Hardware/Software Co-design– A Quantitative approach


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Alternative Computing Platform

Source: 交大任建葳教授

MCU-relatedCoprocesors

foreground memory(Cache)

65028051

MIPSARM

Microcontroller Subsystem

communication &background memory

MotorolaOak

ADITI

programmemory

datamemory

DSP Processors

foregroundmemory

(SIU)

ParallelFunctional

Units

Configurable DSP Datapath

ASIC 4ASIC 3

ASIC 2ASIC 1

interfaceunit

Dedicated Hardware

Control-orientedComputation-intensive

function computation, signal processing

MMX-likeDatapath

• Control-dominated subsystem– controls & coordinates

system tasks– performs reactive tasks

(e.g. user interface)• Data-dominated subsystem

– regular & predictable transformational tasks

– well-defined DSP kernels with high parallelism

Source: 交大任建葳教授


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Radio Processor－A Re-Configurable OFDM-Based PHY Processor

XD

SL

Cab

le M

odem

DAB,DVB

WLAN,BWAW

WR

FRe-configurableOFDM PHY

Convolutional CodeRaw Data

Data Scramble

(Bit - Stream)

Outer Codin

g

Reed-Solomon

Code

Outer Data Interleaving

Inner Codin

g

Data mappingInner Data Interleaving x-PSK, m-

QAM

IFFT Cyclic extension

RF

FFT/IFFT is shared for TX/RX

• A re-configurable OFDM-based PHY processor suitable for several systems is proposed:– DAB/DVB– XDSL– WLAN–

……


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Proposed Configurable ArchitectureM

ain

Pro

cess

or

Radio Processor Subsystem

Kernel

Global ControlUnit

Test Register

Operation Bus

Data Interconnection Network Controller

Switch Box

AH

B B

us In

terf

ace

Task

Task Command (# of functions, data grain, time limit.....)

CommandInterpreter

Addressable

test register

Operation

Buffer

Data

Buffer

IRQ

Controller

Function unit kernel# 1

I/F Control Unit

Local Control Unit

Function unit kernel# n

I/F Control Unit

Local Control Unit

Function unit kernel# 2

I/F Control Unit

Local Control Unit

I/F Control Unit

Local Control Unit


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Different Types of FUs• Configurable data processing FU

– The flexibility is limited, so is the configuration overhead.– The performance is closed to ASIC– Configurable outer receiver

• Programmable data processing FU– Bit/Stream-based DSP-lite co-processor– Programmable inner receiver

• Configurable data routing FU– Interconnection data network

• Programmable control FU– Used to control the simple procedure between FUs


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Length-Scalable，Latency-Specified 64 ~ 2n Point FFT/IFFT Function Unit

Radix-2butterfly

PE

Mux

Radix-2butterfly

Mux

Mux

Mux

Reg

Reg

Reg

Reg

De-Mux

De-Mux

De-Mux

De-Mux

DataLeft

Rotator

DataRight

Rotator

RAM-A

Mux

Addressgenerator

Address rotatorRAM-B

Mux

RAM-C

Mux

RAM-D

Mux

De-Mux

input data frominput FIFO

output data tooutput FIFO

twiddlefactorROM


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Constraint Length-Scalable Soft Input Soft Output Viterbi Decoder Function Unit

Radix-2butterfly

PE

Mux

Radix-2butterfly

Mux

Mux

Mux

Reg

Reg

Reg

Reg

De-Mux

De-Mux

De-Mux

De-Mux

DataLeft

Rotator

DataRight

Rotator

RAM-A

Addressgenerator

Addressrotator

RAM-B RAM-C RAM-D

Reg

Reg

Reg

Reg

HybridTrace-Back

Unit

decodeddata

BranchMetric

Calculation


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Scalable M-Input / N-Output Data Interface

NA

NA

NA

NA

NA

NA

NA

V V V V V VNA

NA

NA

V V V V

BIT COUNTER

OUT POINTER

IN POINTER

DATA OUT

DATA IN

Bit Counter：Indicate How Many Valid bits Within the InterfaceData In：Data Input of InterfaceData Out：Data Output of InterfaceOut Pointer：Indicate Where to Start to Transfer the Output DataIn Pointer：Indicate Where to Start to Store the Input Data


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Features of Radio Processor

Radio Processor

Dedicated H/W Accelerators

•Spreading•Scrambling•Interleaving•Channel Codec•Radio MoDem•FFT•….

Task Header

CMD(Time, function sequence, configuration parameters, ...)

Command Queue

command

CMD #1

CMD #2

CMD Interpreter

Control Unit

Bit-Level Processing Unit

IFFT/FFT Channel Codec

Control Signal

Memory/Storage

Data Queue

Memory/Storage

Data Queue

Memory/Storage

Data Queue

To AFE

Reuse Data

DataSequenceing

Scalar Function Unit

Memory/Storage

Data Queue

Configurable Block Programmable Block

Reuse Data

Reuse Data

Reuse Data

DataSequenceing

DataSequenceing

DataSequenceing

Radio Processor

Data

I C U

L C UDN e t w o r k

Command

Data Flow

• Heterogeneous Configurable Architecture

• Scalable Infrastructure with Unified Design Environment

• Customizable Design• Flexible Instruction Set• Limited Main-Processor

Resource Requirement

FY91


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Proposed Channel Processor

Controller

Configurable InterconnectionNetwork

Configurable InterconnectionNetwork

Storage BlockStorage Block

Task Interpreter

Functional Units

Task

Channel ProcessorConfigurable DSP

Datapaths

•Clock recovery•Diversity Selection•Timing Sync.•Initial cell search•Channel estimation•Multi-user interfacecanceller

•Rake receiver•….

FY92


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Channel Processor

Configurable Stream Interface Unit (CSIU)

Scalable Function Units (data-driven datapaths)

Task Interpreter (controller)

•The controller coordinates the system tasks and all interfaces.•Data-driven datapaths (Adders, MACs, Complex multipliers….)as slave accelerators attached to the controller.•Task Interpreter translates the original control-originate task into dataflow and drives the scalable function units.•The configurable stream interface unit is an embedded memory together with configurable interconnection routing that interacts with the task interpreter. •The computation time of the undertaken task is predictable such that it is easy scheduling for the subsystem.


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Scalable Performance• The number of configurable

coprocessing datapaths are scalablein order to meet the performance requirement.

• Each configurable coprocessingdatapath can be reconfigured for different DSP application.

• The performance boost is achieved by parallel processing via SIMD-likefunction units.

Controller

Controller

CSIU FunctionUnits

CSIU FunctionUnits

Configurable Coprocessing Datapath

CSIU FunctionUnits


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The Design Flow• The data-driven

acceleration is well synchronized with the micro-controller.

• The task ideally suited for coprocessing share the following characteristics:

– Computationally intensive

– Very little use of input, output, or internal registers

• The HW/SW interfacing could be automatic generated.

• Data movement is completely controlled by MCU (i.e. no explicit data coherence mechanism is required)

C/C++ Code(Application-specific)

C/C++ Code(Application-specific)

Pre-processing(Compilation/Profiling)

Pre-processing(Compilation/Profiling)

Kernel Loop Extraction(Task Dispatch)

Kernel Loop Extraction(Task Dispatch)

Source Code Replacement(HW/SW Interfacing)

Source Code Replacement(HW/SW Interfacing)

Post-processing(machine code on CPU)

Post-processing(machine code on CPU)

Task Pre-Analysis/Pre-Transformation(Control/Data Dependent Graph)

Task Pre-Analysis/Pre-Transformation(Control/Data Dependent Graph)

Primitive Function Unit DeterminationPrimitive Function Unit Determination

Data Scheduling/Datapath Partitioning(Load Balancing)

Data Scheduling/Datapath Partitioning(Load Balancing)

Dataflow Control OptimizationDataflow Control Optimization

Optimal Task Datapath MappingOptimal Task Datapath Mapping

Coprocessing Datapath GenerationCoprocessing Datapath Generation

Micro-Controller

Data-Driven Acceleration

HW/SW Co-Simulation/Co-VerificationHW/SW Co-Simulation/Co-Verification

Task


Datapaths


•Rake receiver•….


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A Unified Wireless Open Platform

Analog RF Circuits Communication Algorithms Protocols

phonebookRTOS

SIG

Keypad,Display

API,Control

analog digital

DSP cores

µP core (ARM)

FSM

ALU

Coders

AD

Reconfigurable Transceiver - RF Front-end + Programmable ADC/DAC

NetworkProcessor

Framing

Radio Processor


DatapathsDedicated H/W

Accelerators

•Spreading•Scrambling•Interleaving•Channel CODEC•Radio MoDem•FFT•…


•Rake receiver•…


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Proposed Architecture

AHB

ARM

TIC

LCU

ICU

vectorprocessing unit

Inter-connection

scalar and logic processing unit



storage unit

DSP controller

......

AHB Slave

RegistersCommand Interpreter

(GCU)commandqueue

DSP-Lite PE

LCU

ICU

I/OInter-facePE

LCU

ICU

ReconfigurableN*64FFTPE

LCU

ICU

Inter-leaverPE

LCU

ICU

ViterbiPE


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Proposed Design Flow (draft)

SystemArchitecture

Bus Platform

System Spec

IC-Spec

RTL Coding

SynthesisLayout

Specific System

TIC Pattern

Tube PatternSystemC Pattern

Function Pattern

HW/SW-CoSim

Verilog Pattern

Demo Program

FPGA Verification

Custom Tool transfer

Custom tool

transfer or

CAD tool

Must be verilog pattern

Verilog Pattern

C/Matlab Code

SystemC(Behavior)

SystemC(Cycle Accurate)

RTL Code

Synthesized Code

SystemC(Functional)

Design Flow Tools Test Bench


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HW & SW Co-Verification

ARMulator AMBA

(systemC)

DSM AMBA

(Verilog)

ARM core AMBA

(FPGA)Debugger

JTAG

DebuggerRDI

Test Bench

Performance observer

Virtual PrototypingFast Rapid Prototyping


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Virtual Prototyping

• A software platform to support HW/SW co-verification environment.– Synthesizable AMBA SystemC model

• Bus function model• Generic AMBA platform• Instruction Set Simulator

– Performance Observer


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The Platform

AMBA Model (in systemC)

MemoryController

TIC MemoryModule

Performance Observer

ARMulator RDI Debugger(AXD)

Test BenchTransfer Tool

C Codeor TIC talk

command language

TIC box

Tube

Automated Response Checking Model

Bus Function Model:

Create sequence of transactions on the bus.


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Overview of Virtual Prototyping• Components

– AHB components– APB Bridge– APB components– EMC– TIC– Performance

Observer– Behavioral Modules

• Memory Modules• TUBE• Tic box• Test bench transfer

tools

Flash Memory

A

HB

Timers

Remap/Pause

AHB Bus Controller

Bus Arbiter

Decoder

M2S/S2M Multiplexer

APB

AHB2APB Bridge

InterruptController

SRAM

TestInterface

Controller

ISS

AM

BA

Wrapper

ExternalMemory

Controller

DefaultSlave

TUBE

TIC Box

Interface between ISS

and systemC

Test Bench Transfer Tool

C Code or Tic Talk Command Language

Performance Observer

Our Design


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Features• Bus/Processor independent

– Low requirement on processor computation power. (move data only)– Bus substitution can be achieved by modifying the AHB slave interface only.

• Flexible architecture– Expandable architecture simplify the mounting of new function units.– Distributed command decoding scheme.– Numerous well built configurable function units are provided.– A highly flexible function unit dedicated for inner transceiver algorithm will be

available this year.

• Complete simulation and verification environment– SystemC environment is well built except the ISS.– Verilog environment is complete including ARM.– Bus function model (TIC box) is available in both SystemC and Verilog version.

• Silicon proofed– Test chip @ TSMC 0.18 CMOS technology, with 750k gate count (not including

SRAM module)


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Features (Cont.)• A transceiver PHY platform:

– Available function units currently:• 1. Scrambler/De-scrambler.• 2. FEC / Viterbi decoder: 1/2, 2/3, 9/16, 3/4 coding rates with 64

states Viterbi decoder.• 3. Interleaver: 48/96/192/288/384/576/768/1152 points.• 4. Modulator: BPSK/QPSK/16QAM/64QAM.• 5. FFT: 64/256/2048/4096 points FFT.• 6. I/O Interface.

– An array based processing unit targeted on inner transceiver of communication system will be built this year.

• An easy algorithm to hardware design platform:– A design and verification methodology from algorithm to RTL via

SystemC is provided.– Co-simulation can be performed in SystemC and Verilog using

ARM ISS or bus function model (Test-Interface-Controller).


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Benefits• Simplify backbone design:

– A platform provides an architecture reference which is proved to be a applicable architecture.

– Simple modification is enough to be suitable to similar systems.

• Save repetitive design time:– Existing IPs for the platform can be adopted to accelerate the build up

time.– Based on existing platform ease the replace of custom design.

• Ease the verification:– The environment provided by a platform helps to verify the custom

modification in each step.

• Early evaluation:– A virtual prototyping provides early system performance data and H/S

partitioning information.


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Conclusion

• Platform-based design facilitates complex system designs in SOC– Reuse a platform architecture, hardware IPs,

interconnection, and software IPs– Simplify design method and techniques– Focus on system design, analysis,

optimization, and verification– Reduce design time, cost, and risks

re-configurable soc design platformtwins.ee.nctu.edu.tw/courses/soc_sys_overview_04fall... ·...

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