re-configurable application specific computing (rasc/fpga)

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Silicon Graphics, Inc. Re-Configurable Application Specific Computing (RASC/FPGA) David Alexander Director of Engineering

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Re-Configurable Application Specific Computing (RASC/FPGA). David Alexander Director of Engineering. Scalar General Purpose uP (Today). General Purpose Peer I/O (Today). Others…. Graphics (Today). APU/Configurable (FPGA/RASC) (Today-2006). - PowerPoint PPT Presentation

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Page 1: Re-Configurable Application Specific Computing (RASC/FPGA)

Silicon Graphics, Inc.

Re-Configurable Application Specific Computing (RASC/FPGA)

David AlexanderDirector of Engineering

Page 2: Re-Configurable Application Specific Computing (RASC/FPGA)

slide no. 2

Scalable Global Shared Memory Structure10s of Thousands of ports

Globally addressableFlat & high bandwidthFlexible & configurable

Multi-Paradigm ComputingTerascale to Petascale Data Set...Bring Function to Data

• Globally addressable, universally accessible, high-bandwidth flat address space• Addressing the transition from Terascale to Petascale computing• Tightly coupling “best-of-breed” computation, I/O, and visualization paradigms

to memory

Scalable Global Shared Memory Structure

ScalarGeneral Purpose uP

(Today)

General PurposePeer I/O

(Today)

Graphics(Today)

APU/Configurable(FPGA/RASC)

(Today-2006)

Others…

Page 3: Re-Configurable Application Specific Computing (RASC/FPGA)

slide no. 3

NUMAlink FabricGlobal

Shared Memory

NL4 Ports(6.4GB/s x 2)

FPGA, DSP, or

ASICTIO ASIC

6.4GB/s

Scratch/FIFOMemory

I/O

Products:• Athena…V2-6000 based, rack mount module…shipping today• Abacus…Virtex 4 based, blade…in development pipeline

Solution variants:• Roll-your-own-code customers

– User developed bitstreams using a variety of environments/tools– Subroutine or std library abstractions (MKL, VSIPL)

• Commercial apps cust…co-dev. specific use “appliance” with ISV/partners

Addressing the Performance Challenge Integration into NUMAlink

Page 4: Re-Configurable Application Specific Computing (RASC/FPGA)

slide no. 4

Development EnvironmentEase of Use

• 3rd Party Development Tools– Celoxica, Impulse Acceleration, Mitrion, Starbridge/Viva, Nallatech– Support for user-developed HDL modules– Timing and routing…Synplicity & Xilinx ISE tools

• FPGA aware version of GDB– Capable of debugging the FPGA and System Software– Capable of multiple CPUs and multiple FPGAs

• Developing an FPGA-aware version of our performance tuning tool…Open Speedshop

• RASC Abstraction Layer– API developed…participation in OpenFPGA.org to drive standards– Developing a set of standard libraries (such as VSIPL, MKL)

Page 5: Re-Configurable Application Specific Computing (RASC/FPGA)

slide no. 5

Nallatech & SGI Partnership

• Collaborative development of a compatible HW/SW infrastructure and development environment– Creation of seamless, extended product line– New multi-FPGA product which marries Nallatech’s DIME architecture with

SGI’s NUMA architecture– Portability algorithm and applications implementations across both

companies’ full FPGA product line– Streamline collaborative development of future products

• Enhanced algorithm/appliance implementation capabilities for appliance and program-specific opportunities

• Facilitate the definition and evolution of industry standards