rca engineer - fbcoverup.com · precise, closed -loop manufacturing systems for wafer processing....

RCA EngineerVol. 26 No.2 Sept./Oct. 1980

41,

....

1

Reproduced for educational purposes only. Fair Use relied upon.

Roger Stewart at the Solid State Technology Center (SSTC) gaveus a black -and -white scanning electron photomicrograph of aCMOS/SOS buried -contact memory cell. Our printer added colorvia a special posterization process. Then we superimposedphotographs showing the design, fabrication, testing andapplication aspects of large scale integration (LSI) for this specialissue.

We've printed the original photograph, labeled it, and putRoger's schematic diagram below it so that you can see the fivecross -coupled transistors forming the memory cell. There arethree layers of material. The epitaxial silicon (epi) layer is the baselayer, the polysilicon (poly) forms "word lines- that run top tobottom in the photo in the middle layer and the aluminum metallines, "the bit lines," run diagonally on the top layer. Poly crossesepi where the transistors are located.

Good CMOS technology efficiently interconnects the threelayers of material. Before, CMOS makers painstakingly inter-connected all layers to metal. Today at RCA, with the help of AndyDingwall (see article with Roger Stricker, p. 71) and other SSTCand division researchers, poly and epi in buried contact with eachother form an efficient subterranean connection.

anai EngineerA technical journal published byRCA Research and EngineeringBldg. 204-2Cherry Hill, NJ 08358TACNET: 222-4254 (609-338-4254)

RCA Engineer Staff

Tom King EditorMike Sweeny Associate EditorLouise Carr Art EditorFrank Strobl Contributing EditorBetty Gutchigian CompositionDorothy Berry Editorial Secretary

Pete Bingham

Jay Brandinger

John Christopher

Bill Hartzell

Jim Hepburn

Hans JennyArch Luther

Howie Rosenthal

Ed Troy

Bill Underwood

Joe Volpe

Bill Webster

Ed Burke

Walt Dennen

Charlie Foster

John Phillips

Editorial Advisory Board

Division Vice -President, Engineering,Consumer Electronics DivisionDivision Vice -President, "SelectaVision"VideoDisc OperationsVice -President, Technical Operations,RCA Americom

Division Vice -President, Engineering,Picture Tube DivisionVice -President, Advanced Programs,RCA GlobcomManager, Engineering InformationDivision Vice -President, Engineering,Commercial CommunicationsSystems DivisionStaff Vice -President, Engineering

Director, Operations Planning andSupport, Solid State DivisionDirector, EngineeringProfessional Programs

Director. Product Operations.Missile and Surface Radar

Vice -President, Laboratories

Consulting Editors

Administrator, MarketingInformation and Communications,Government Systems DivisionDirector, Public Affairs,Solid State DivisionManager. Systems and ProceduresManager, Proposals and Publicity.Automated Systems

To disseminate lo RCA engineers technical information of professional value Topublish in an appropriate manner important technical developments at RCA. and the roleof the engineer To serve as a medium of interchange of technical information betweenvarious groups at RCA To create a community of engineering interest within thecompany by stressing the interrelated nature of all technical contributions To helppublicize engineeling achievements in a manner that will promote the interests andreputation of RCA in the engineering field To provide a convenient means by which theRCA engineer may review his professional work before associates and engineeringmanagement To announce outstanding and unusual achievements of RCA engineersin a manner most likely to enhance their prestige and professional status

Henry Kressel

Human resources interconnect for VLSI

The economic power of nations used to de measured by steelproduction or shipbuilding. Now we are entering an age wrenmicroelectronics-wafer fabrication and shipbuilding-willbecome an important gauce of national technological com-petence. Microelectronics has reached center stage in corporateand national economic planning because complex integratedcircuits form the heart of electronic systems.

Microelectronics success requires silicon - the most common rawmaterial, and the dedicated efforts of very skillful teams ofspecialists in materials, computer science and electronic design -the scarcest resource. RCA has its share of the scarce humanresources vital to success in microelectrorics, and a distingL ishedrecord of innovation. RCA's management is dedicated to in-creasing our microelectronic ability both for the marketplace andfor our internal needs.

The eighties will be the decade of circuitry featuring very largescale integration (VLSI) N.4.ith more than 100,000 metal -oxidesemiconductor (MOS) transistors per chip. The timely realizationof such ccmplex devices requires a highly -disciplined team effortthat addresses, starting in the early deve opmental stages, issuesof design, manufacture, reliability and testing. The production ofthese VLSI devices with micron -sized features will require in-creasingly complex equipment, computer -aided design aid ourunderstanding of physical and chemica' phenomena that, beforenow, were inconsequential in integrated circuit fabrication. Thisissue of the RCA Engineer presents sutjects ranging from theadvancec process technology plans for the SSTC to theapplications of custom integrated circuits to communicationssystems, broadcast equipment and consumer electronic products.

The successful manufacturers of VLSI devices will have masterful-ly manaced the efforts of many specialists to achieve c'oselydefined goals. The chain of interlocking skills will begin in theresearch laboratory, extend into the factory and end with thesuccessful VLSI system performance. Working closely with theSolid State Division and other use's, the David Sarnoff ResearchCenter in Princeton, and the Solid State Technology Center(SSTC) in Somerville will continue to play vital roles in expandingRCA's solid state abilities.

Henry KresselStaff Vice -PresidentSolid State TechnologyRCA Laboratories

Highlights

TEST VECTOR

SAO 14

SA1 10

SA1 3

in this issue...

Fabrication technologies include improved photo-lithographic and etching techniques for ICs with two -to -three micron gate -lengths; process techniques and im-proved cleanliness to reduce defects in the dielectric andinterconnect layers on IC chips; and computer -aided, ultra -precise, closed -loop manufacturing systems for waferprocessing. See articles on pages 4, 8, 18, 24, 29.

Computer -aided design and testing tools must keep up withthe growth in IC complexity and the demands for: system,logic, circuit and process design; physical implementation(layout); test generation (fault coverage) and test dataanalysis; and verification/simulation at all levels. Moreimportantly, the new tools and approaches must bepractical enough to be accepted and used routinely. Seearticles on pages 33, 42, 46, 53.

Applications for the new LSl and VLSI technologies in thisissue include 72 CMOS gate -universal -array applicationsimplemented by nine different RCA division -locations; theGovernment Communications Systems' TENLEY/SEELEYprogram applications; CMOS random-access memories(RAMs); and more. See articles on pages 58, 64, 71.

In future issues...communications trends, mechanical engineering, humanaspects of engineering, computer -aided design andmanufacturing.

EaCE,a EngineerVol. 26INo. 2 Sep .IOct. 80

overview 4 VLSI dimensions, designs and decisionsI. Kalish

fabrication technologies 8 Advanced process technology at the Solid State Technology CenterE.C. Douglas

18 What electron -beams can do for LSIR.A. Geshner

24 The road to LSI: a photographic journeyW.A. Bosenberg

29 Computer -aided wafer processingR. McFarlane

computer -aided design 33 The evolution of design automation toward VLSIand testing L.M. Rosenberg

42 A system for the automated design of complex integrated circuitsA.E. HeathIR.P. Lydick

46 A multi -technology checking program for large-scale integrated circuitsB.S. Wagner

53 LSI testing methods and equipmentR.H BergmanIT.R. Mayhew

applications 58 The gate -universal -array for digital CMOSG. Skorup

64 Custom LSI: an effective tool for digital communications equipmentE.J. MozziIC.A. Schmidt

71 Advances in CMOS static memory developmentR.E. StrickerIA.G.F. Dingwall

general interest 75 Electro-optical techniques for measurement and inspectionD.P. Bortfeldi I. Gorogl P.D. SouthgateIJ.P. Beltz

departments 81 Patents

82 Pen and Podium

83 News and Highlights

Copyright 1980 RCA CorporationAll rights reserved

I. Kalish

VLSI dimensions, designsand decisions

VLSI circuits designed without error and fabricated withoutflaw pose tough technical problems, but the decisionsand cost -considerations that go into VLSI implementation inreal electronic systems may be the hardest ones of all.

Abstract: VLSI memory development hasmeant new fabrication and designproblems but, for the most part, VLSIfabrication is upon us. The extreme com-plexity of VLSI circuitry poses design,simulation and testing problems butcomputer -aided design has attacked theseproblems. The hard decisions are betweencatalog parts and custom designs, betweenNMOS and CMOS technology.

Twenty years of vigorous innovation,creative exploitation of the laws of natureand man's tools have carried semiconduc-tor technology from the excitement of asingle resistor -transistor logic (RTL) gatein a package to the routine expectation of100,000 -gate complexes. This transitionsignals the advent of VLSI, Very LargeScale Integration.

VLSI dimensions

The development of fabrication methodsto make hundreds of thousands of com-ponents per package has meant more thanjust supplying systems designers with morefunctions at lower cost. It has drasticallyaltered the strategy mid the timing of thesemiconductor product generation cycle.Figure 1 summarizes the traditional stepsleading to a semiconductor product.

Reprint RE -26-2-1

Final manuscript received August 12. 1980.

Engineers use the electrical needs of asystem to define the product. In the designphase, they generate a schematic and makea layout to establish the masks needed forfabrication. If evaluation confirms that thedesign meets system goals, the device canproceed into production. If the evaluationreveals design shortcomings, then thatphase of the cycle is repeated.

To develop simple semiconductorfunctional electronic blocks, mostengineers worked to define and refine thefabrication phase. They optimizedtechnology to achieve the highest deviceperformance consistent with practicalmanufacturing yields. Usually the defini-tion, design and evaluation phases wouldtake less than one year of engineeringeffoi-t. VLSI has altered the effort alloca-tion drastically. With the exception ofmemory development-and that excep-tion is a major one - the developers of aVLSI circuit must assume that no newtechnology needs to be developed for itsfabrication. It presupposes that atechnology exists, usually as a result of amemory development effort, capable offabricating and interconnecting thousandsof components simultaneously. Thattechnology is defined in terms of process-ing schedules for the factory and in terms ofdesign rules for the designer. Table I listssome important design rules associatedwith MOS technologies. Their significancein determining the minimum device struc-ture is illustrated in Fig. 2.

The design rules, together with modeling

PRODUCT DEFINITION

DESIGN

FABRICATION

EVALUATION

PRODUCTION

Fig. 1. Steps leading to a semiconductorproduct.

equations, provide the circuit designer withthe transconductances, resistances andcapacitances associated with the chosen

Table I. VLSI design rules.

1980 1985

Channel length

Minimum contact

2-5pm 1-2µm

4pm x 4pin 2prn x 2pm

Metal width and spacing 10pm 6pm

Minimum feature spacing 1pm .5pm

4 RCA Engineer 26-2 Sept./Oct. 1980

MINIMUM FEATURE__.,SPACING 11

CHANNEL LENGTH

CONTACT

METAL

SPACING WIDTH

Fig. 2. Significance of VLSI design rules Indetermining minimum device structure.

technology and, therefore, permit the validprediction of both circuit performance andchip size. Thus, the following problemsremain: given 100,000 transistors of knownelectrical ability, how can we apply andinterconnect all transistors to achieve adesired system function, and how can weverify, through appropriate testing, thatthe complex arrays will function satisfac-torily even under worst -case conditions ofboth system -environment and process -related parametric variations? Thesuccessful solutions to these problems canrequire ten -to -twenty engineering yearsand a real-time expenditure of one -to -threeyears. The availability of human technicalresources is the major problem limiting thegrowth of VLSI technology.

VLSI designs

Unlike other forms of VLSI, the develop-ment of semiconductor memories hasmeant the development of new technology.System requirements for semiconductormemories have been clearly defined -more, More, MORE! The acronyms have

evolved from PMOS to NMOS to high -density NMOS to SOS and the featureshave diminished from mils to microns inresponse to a still insatiable demand formore bits -per -package. A specific memorydesign's universal applications and high -volume use have justified mammoth in-vestments for engineering and for capital toestablish the needed fabricationtechnology.

In the last five years, memory -cell sizeshave shrunk from five square -mils -per -bitto less than one square -mil -per -bit, making64K memories commercially feasible. Acombination of circuit design, advanced

technology and innovative device struc-tures has increased this functional density.For example, dynamic memories offer thegreatest functional density because

capacitors store the information, thusmaking one -transistor memory cells possi-ble. But customers need memories that canretain information indefinitely, so circuitrywas developed to refresh (replace) thecharge that tends to leak away. In addition,circuit advances in the sense amplifiers ofmemory circuits permitted the detection ofextremely small packets of charge, makingit possible to use minimum -sized storagecapacitors. Clearly, advancedtechnology - mask -making, photolitho-graphic resolution improvements andanisotropic plasma -etching techniques -has reduced minimum feature sizes.

Figure 3 shows how innovative devicestructures improve density. Both structuresexemplify arrays of static memory cells

L

designed using the limits of RCA'sdevelopmental three -micron CMOS IItechnology. The cells in Fig. 3a use astraightforward isoplanar silicon -gateCMOS technology and, because of theadvanced design rules of the CMOS IItechnology, can be as dense as two square -mils -per -bit. The cells in Fig. 3b, in addi-tion to exploiting advanced design rules,assume the increased process complexity ofa two -level polysilicon process that can beused to achieve more efficient circuitcrossovers and smaller load elements. Thisdesign approach results in a density of 0.6square -mil -per -bit, a density compatiblewith the practical production of a 64Kstatic memory. Figure 4, a scanning elec-tron photomicrograph of a multiplepolysilicon structure, illustrates vertical aswell as horizontal structures in devicedesign.

VLSI exploits technologies developed

TC1259 ALL METAL INTERCONNECTIONS - CELL AREA 2.24 MIL'

16 p.

DOUBLE POLY CELL

l9µ

rz

ACTIVE AREA

POLY I

POLY 2

METAL CONTACT

BURIEC CONT

N+

METAL

(b)

(a)

Fig. 3. Arrays of staticmemory cells designedusing RCA's devel-opmental three -micronCMOS II technology.

Kalish: VLSI dimensions, designs and decisions 5

0.7p.

POLY

CHANNEL OXIDE

Fig. 4. SEM of multiple polysilicon structure.

for high density memories to achieve com-plex logic functions. Also, as mentionedearlier, the design and evaluation phasesdemand a major engineering effort.Human talent for creative genius often isaccompanied by human fraility and thepotential for error. So, even a massiveinvestment of talent in a complex micro-processor program would not guaranteesuccess in a reasonable amount of time.This problem has been attacked throughthe innovative development of a number ofprograms for computer -aided design(CAD). These programs permit thedesigner to calculate the performance of agiven schematic in terms of a potentialtechnology, to validate an approach toimplementing a given logic function, todefine the topological interconnectionsneeded to achieve a function using stan-dard logic blocks, to generate thephotomask patterns needed for devicefabrication, and to define, automatically,test routines that will evaluate the finisheddevices. Table II describes some of theCAD programs now actively used by RCALS1 and VLSI designers.

VLSI decisions

Assuming that VLSI circuits can bedesigned without error, then fabricatedwithout flaw, we will consider other aspectsof VLSI implementation in a real elec-tronic system. For example, should we usea standard catalog part or a custom design?The advantages of a custom part includethe potential for a minimum parts count, apossible proprietary advantage in the useof an exceptionally high-performancedesign approach, and unique system -interface requirements. The advantages ofcatalog parts include lower cost, morepredictable delivery, an establishedreliability history and more fully

Table II. CAD programs for LSI and VLSI.

Program name Function

R -CA?

LOGSIM

TESTGEN

ART

CRITIC

APAR

AUTOROM

Circuit simulation program

Logic simulationTime -based (gate delays)

Logic simulationWorst cast hazard analysis

Mask artwork manipulation

Design -rule checking

Automatic placement and routing programsMP2D, PP2D

Automatic generation of pattern -generatorand test programs from bit -pattern file

characterized designs. The disadvantagesof custom designs include higher costbecause the parts are usually made in lowervolume, unreliable delivery because thedesign and evaluation cycles are unpredic-table, and an increased probability thatunanticipated bugs will be discovered dur-ing system prove -out. VLSI catalogfunctions include random access memories( RA Ms), read only memories (ROMs) and

microprocessors. Except in high volumeapplications such as automotive elec-tronics, custom designs of such parts arerarely justified. Where LSI or VLSIcustom parts are justified, different ap-proaches can be taken to minimize risks.One of these approaches is the use ofuniversal arrays.

A universal array is a circuit consistingof a matrix of identical logic elements, such

111,2%t

00 SD 'LILLE

11 la la la 4 a

Cr CB

CIS

a

tt

aa

a

a

Fig. 5. Closed -cell logic (C2L) circLI: used to implement the PRIMUS color weather radardisplay program.


as gates. We can use the same array toimplement many logic functions simply bymodifying one mask level - the metalliza-tion used to interconnect the elements. Thissignificantly reduces the engineering designtime and, because the basic circuit elementshave been proved out in other con-figurations, assures that the design willperform as predicted. The disadvantages ofthe universal -array approach are poorpacking density and, because devicegeometries cannot be customized, less thanthe maximum speed inherent in a giventechnology. Where reduced package countis a primary system goal, however, theuniversal -array approach has been usedvery effectively. Figure 5 is a photograph ofone of the closed -cell logic (C2L) circuitsused by RCA's Van Nuys Avionics Divi-sion to implement its successful PRIMUScolor weather radar display program.

Figure 6 illustrates an automatic stan-dard cell layout program that minimizesthe need for design engineering. This ap-proach, APAR (automatic placement androuting), also uses standardized buildingblocks to accomplish complex logic. In-stead of the handful of different elementsavailable in the universal -array approach,hundreds of different building blocks areavailable. These blocks are not located inprediffused positions on a silicon wafer.They are software definitions in a com-puter memory. A computer program isused to transform the logical requirementsof a function into an array of optimallychosen and optimally interconnectedelements.

A disadvantage of the APAR approachis that new masks have to be generated forall processing levels. This increases initialengineering costs and processing time, butthese increases represent only a small partof the total design cycle and are usuallyjustified by the increased density and per-formance of APAR designs. Figure 6illustrates the application of APAR toimplement a general processing unit func-tion using SOS technology. Clearly, theAPAR packing density is an improvementover the universal -array packing density.The large percentage of chip area devotedto metal interconnections is particularlysignificant. The number of components ona memory -structure chip is primarilylimited by the size of the elements. Incontrast, VLSI areas are limited by in-efficient interconnections between randomlogic elements.

System requirements and cost -considerations primarily determine thetechnology chosen for VLSI. Most in-dustry LSI approaches exploit the high

Fig. 6. The APAR circuit -design approach uses standardized building blocks to accomplishcomplex logic.

density and performance of the dynamicNMOS approach for most applications,and use bipolar technologies where max-imum speed is crucial. CMOS approachesexcel where power, noise margin andambient operating ranges are more impor-tant. The high component count of VLSImakes power a primary considerationbecause capacitively dissipated power willsignificantly limit the density advantage of

dynamic NMOS approaches. The bipolarspeed advantage is being eroded in-creasingly by the performance of short -channel (one -to -three microns) MOSstructures. For these reasons, a high -density version of the CMOS technologythat exploits short -channel, isoplanar andmultiple -level interconnection options willemerge as the mainstream VLSItechnology.

lz Kalish has been involved in the design and development of semiconductor devicessince joining RCA in 1953. He is presentlyManager of the IC Design and ProcessDevelopment group of the Solid StateTechnology Center where he is responsiblefor the development of the next generationof VLSI technology needed to implementhigh performance memories and micro-processors in both bipolar and field effectdevices. lz has authored several papers onsemiconductor devices and a book,Microminiature Electronics.Contact him at.IC Design and Process DevelopmentSolid State Technology CenterSomerville. N.J.TACNET: 325-6243

Kalish: VLSI dimensions, designs and decisions 7

E.C. Douglas

Advanced process technologyat the Solid State Technology Center

Teams at the Solid State Technology Center are exploringformable tools and process innovations to fabricate the nextgeneration of high -density complementary metal -oxidesemiconductor circuits.

Abstract: The component density ofmetal -oxide -semiconductor integratedcircuits ( MOS IC) has been increasingrapidly in recent years and these trendstoward larger circuit complexity andsmaller individual component size haverequired a continuous refinement and ad-vancement of process technology. Thispaper describes how RCA's Solid StateTechnology Center ( SSTC) is meeting thechallenge of very large scale integrated(VLSI) circuits with developmentprograms in key technology areas.

The challenge ofhigh -density technologyThe metal -oxide -semiconductor integratedcircuit ( MOS IC) industry has beencharacterized by an extremely rapidgrowth from medium scale integration( MSI) in 1965, (10' to 102 gates per chip) tovery large scale integration (VLSI)manufacturable today, (104 to 10` gates perchip). Figure 1 shows the trend of thisgrowth in gate complexity for both RCA'sCMOS technology' and the NMOStechnology' that is popularly used by otherMOS IC manufacturers. Figure I also

Reprint RE -26-2-2Final manuscript received June 18. 1980.

shows the actual and the projected growthsof MOS IC die size'. These trends towardlarger circuit complexity and smaller in-dividual component size have required acontinuous refinement and advancementof process technology in order to maintainhigh yields and to achieve manufacturing

106

105

104

I103

102

10

1

0I1960 1965 1970 1975

YEAR

cost effectiveness. If these trends are tocontinue at the pace projected in Fig. I,then the challenge to be met is the develop-ment of advanced process technologywhich can produce larger sizes of defectlesschips and, at the same time, can achievesmaller feature sizes within the chip.

VLSI

LSI

MSI

SSI

1982PROJECTION

64K DYNAMIC RAM 16 K CMOSSTATIC

RAM .)16 BIT NMOS /1P

16 K DYNAMIC RAM-

NMOS /1 PROCESSOR

4K NMOS RAM

I CHIPCALCULATOR

x

4008(A SERIES)

4015 cp

- RCA CMOSX -NMOS

X

4K CMOSSTATIC RAM _

C2L 1802 CMOS/1 PROCESSOR/

1K CMOSSTATIC RAM /

LOVAG CMOS ,/WATCH CHIPS/ 0.8 -

MIL2/GATE

MIL2/GATE

2.56 MIL2/GATE

1980

500 X 5000.2 -MIL /GATE

400X 400 wN(7)

Q.

300 X 300 5

200 X 200

100X100

1985

Fig. 1. Both the size and the density of integrated circuit chips has been increasingrapidly with time.


A graphic illustration of the nature ofthis challenge is shown in Fig. 2 where thegeometric structure of bulk transistors ofgate lengths running from 7.5 to 2i.tm areshown. In order to keep up with theprojected growth, photolithographic tech-niques and etching techniques which cancontrollably pattern 3µm and 2µm gatelength structures must now be in thedevelopment stage. Since chip area is

expected to increase by a factor of ^ 4 by1985, process techniques must now be inthe development stage which reduce thenumber of defects in the various dielectricand interconnect layers on the chips. Inaddition, increased cleanliness is required,both in layer -formation techniques and inthe overall operation of the fabricationfacility.

RCA's Solid State Technology Center ismeeting the VLSI challenge on a broadfront. Working on some projects in closecooperation with the ResearchLaboratories in both Princeton andZurich, major process developmentprograms are presently being pursued inthe following areas:

Fine -line photolithography Low-pressure chemical -vapor deposition

(LPCVD)

GUARD BAND

AREA = 8.75 mil2/

15 X 10 ii.ma

7,7

w. -I AREA14mil2I\\ \ I

e I

I

.?\N.

I5X5i6m2

L r...., ----I-I L_Sprn

AREA= 62 rmi2

3X4µm2

_..1 L-3µm

4.114_____r-- 1 AREA .19mil22 X 2p.m2

_...1 L 2 wn

Fig. 2. A graphic illustration of the decreasein the area required for a bulk transistor asthe gate length is decreased.

Table I. Characteristics of contact and projection systams.

TechniqueMinimum

feature size(Am)

Source wavelength(A)

Overlay tolerance(Am)

Major limitations

Contact Submicron Hg 0.5-0.75 defects, runout, mask cost,linewidth variation

Proximity 3-4 HgXe

0.5-0.75 minimum geometry, defects,linewidth control

Projection1:1 2-3 Hg 0.5-0.75 minimum geometry1:1 (deepUV)

2400 9 source, optics, resistavailability

Direct stepon wafer

1.25-1.8 4040 0.125-0.35 accommodation of waferdistortion

(DSW)

X-ray -0.3 4-8 9 source complexity,mask structure,registration

Electronbeamdirect writeon wafer

0.1-0.2 0.1-0.3 cost, throughput

Direct digital control of thermal oxida-tion and diffusion

Plasma etching Silicide metallization Upgrading of white room fabrication

facilityIn the following sections, the activities in

each of these areas will be described andwill be related to the overall SSTC goal ofdeveloping advanced processing for largerarea, higher density integrated circuits.

Fine -line photolithography

As the density of integrated circuits in-creases, limits are placed on both the

minimum feature size that can bephotoprinted and the control which can beachieved in the photoprinting process.Table 13 summarizes the characteristics andmajor limitations of the photoprintingtechniques which are presently being in-vestigated by the IC industry. Proximityprinting, 1:1 projecting printing, anddirect -step -on wafer techniques are active-ly being studied at SSTC. In addition tousing various types of photoprinters,automatic equipment is being used to coatwafers with photoresist and to develop theexposed wafer, thereby achieving a highdegree of control and reproducibility in thechemical processing of photoresist.

Table I shows that although contact

III 1111

2µm, lµmLINES

4 p.m, 2 p.mSPACES

4 /AmPITCHLINES

5 p.m°ITCHLINES

3 #.4.m

CONTACTOPENINGS

5 µm, 3pmLINES

5µm, 3p.mSPACES

6µmPITCHLINES

10µmPITCHLINES

5 p.mCONTACTOPENINGS

HNR120 PATTERNS DIRECTLY ONA POLYSILICON SURFACE

HNRI20 PATTERNS DIRECTLY ONA POLYSILICON SURFACE

PE REFLECTIVE OPTICS PRI \ TER SUSS PROXIMITY PRINTER

Fig. 3. Performance of various proto-printers. The dimensions given are those on the maskwhich was used to print the pattern. Each set of patterns was made with the same exposure,i.e., each set comes from the same wafer.

Douglas: Advanced process technology at the Solid State Technology Center 9

printing is capable of replicating sub -micron feature sizes, contact printing isunsuitable for VLSI applications becauseof the defects which are caused on both thephotomask and the wafer by the contactprocess, and because of the runout which iscaused by wafer/ mask distortion whenthey are clamped together. For thesereasons, even older, less demanding in-tegrated circuit production is being shiftedto the contactless proximity and image -projection techniques.

Proximity printing

A simple method of achieving contactlessphotoprinting is to space the mask a smalldistance from the wafer (2.5 to 25µm) andproject a "shadow" of the mask onto thephotoresist-coated wafer. This proximity -printing technique costs much less thanimage -projection systems since no lens isinvolved. The technique also has the flex-ibility of allowing the use of a wider rangeof illumination wavelengths which, likecontact printing, is limited essentially onlyby mask transmissivity.

SSTC is experimenting with a SussModel 55 Proximity Printer's and hasfound that feature sizes in the 3 to 5umrange can be printed under optimum con-ditions (Fig. 3). Since a proximity printeruses the diffraction -dominated shadow of amask, the resulting exposed image (for thecase of negative resist) is a trade-offbetween complete exposure, minimumresist -loss during development, andminimum "orange peel" on the one hand,and line -width deterioration and resistbridging on the other hand. Proximity

MOTION OFMASK MASK

OBJECTPLANESLIT

IMAGE OFSLIT

printing also leaves noticeably roundedcorners, and the nature of the surfaceunderlying the photoresist can affect theexposed image. Polysilicon is the mostdifficult surface on which to pattern. Theuse of a broad -band, high-pressure,flashed -Xenon light source can minimizesome of these problems by allowing apolychromatic printing -characteristic.

Reflective image projection

Image -projection techniques can improvethe quality and control of contactlesswafer -exposure. Early attempts in thisdirection used large -field, refractive lensesbut were generally unsuccessful because ofproblems with lens aberrations, lightscattering, temperature stability, telecen-tricity, focal depth and field coverage.Simply stated, it is hard to grind glass lenselements that can produce 3- to 4 -inchdiameter images with -to-2µm resolution.An alternate approach is to use reflectiveoptics', and in addition to combinereflective optics with the scanning conceptwhich reduces the complexity of thereflecting surface needed to cover a largefield. The Perkin-Elmer 120 and 220 pro-jection aligners used in SSTC are based onthe scanning, reflective -optical principlewhich is diagrammed in Fig. 4.

Even though the accurately formedoptical surfaces in a scanning reflective

PRIMARY CONCAVEMIRROR

CHIEF RAY

, SECONDARYCONVEX

WAFER,

I

MIRROR

I

4 MOTION OFWAFER

Fig. 4. Diagram of basic 1:1 reflective optical system which imagesa ring field (circular object plane slit) using a primary concavemirror and a secondary convex mirror. As shown, the mask andwafer must be translated in opposite directions at the same rate. Ina real system, such as the Perkin Elmer (PE) 120 or 220, the opticalpath is bent with additional prisms so that both the mask and thewafer can be mounted on the same translating carriage.

CAMERAOBJECTPLANE

REFERENCETARGET ONRETICLE

RETICLEALIGNMENTTARGETS

system are fewer in number and smaller insize when compared with the refractivesystem counterpart, the physical fabrica-tion of a focusing mirror and its opticalcoating is still the limiting factor in 1:1reflective -projection system. Improvedmeasurement techniques, using a laser,allow the presently obtainable rmstolerances of finished optical surfaces toapproach A/100. This is sufficient to allowthe printing of feature sizes in the 2 -to -3µmrange (Fig. 3).

Direct -step -on -wafer techniques

Direct -step -on -wafer (DSW) machinesprovide the printing technique with theoptimum combination of minimum featuresize and overlay tolerance". This is

achieved by using a 10:1 refractive projec-tion system which employs a 10X reticle,projects and exposes an individual chip -size image on the wafer, and step -and -repeat -prints the number of chips neededto cover the wafer surface. Since the fieldsize of a 10:1 reduction lens is relativelysmall, "10mm (-400 mils) in diameter,stepper lenses can be fabricated to give-1mm resolution capability. Figure 5 il-lustrates the operation of the Electromask700SLR wafer stepper presently being usedat SSTC.

The difficulties associated with a DSWmachine are not in the lens. Positioning the

ROTATINGRETICLECARROUSEL

I I OPT CALI AXIS

10:1REDUCTIONLENS- -

WAFERMANIPULATIONSTAGE

RETICLEMANIPULATIONSTAGE

-WAFERALIGNMENTTARGET

Fig. 5. Diagram of basic operation of the Electromask 700SLRDirect Step -on -Water 10:1 projection aligner. The machine iscapable of automatic reticle changing, through the lens alignment,and ± 0.25 tirn alignment tolerance.


wafer accurately during the steppingprocedure, aligning the printing of eachstepped exposure, and obtaining fast

enough stepping operation in order toachieve a reasonable throughput are thedifficulties. Positioning accuracy is

achieved with a laser-interferometricallycontrolled air -bearing x -y table which iscomputer controlled and is capable ofpositioning accuracies within ±0.25µm.Alignment accuracy is achieved using aTV -based through -the -lens microscopesystem which aligns the 10X reticle directlyto the wafer (Fig. 5). With only twoalignments - one on each side of thewafer - the Electromask system is capableof overlay printing individual chips acrossthe surface of a 3 -inch wafer with ±0.25µmoverlay tolerance. Although the SSTCElectromask machine is not yet equippedwith automatic alignment at each chipposition, Electromask has developed sucha system that can be retrofitted to theSSTC machine. All this automatic perfor-mance, however, makes it difficult to

achieve high wafer throughput. Withoptimized printing of the largest availablefield and two automatic reticle changes perlevel of printing, the throughput of theElectromask machine will be between 30and 50 wafers per hour.

Low-pressure chemical -vapordeposition - the questfor fewer defectsMOS ICs are fabricated by the systematicformation and patterning of layer uponlayer of dielectric or interconnectmaterials. Figure 6 shows a diagram ofsuch a layered structure which forms acomplementary pair of bulk CMOStransistors (actual ICs may not use all ofthe layers shown). Of the eight layers usedto fabricate the structure, six of them aredeposited layers. For reliability and highyield, all eight layers should be perfectlyuniform, with no included defects, andshould contain no unwanted con-taminants. In addition, as is evident fromFig. 6, the layers should conformally coverthe various topological steps which resultin the structure because of the patterning.

Until recently, the techniques used todeposit these layers have involvedchemical -vapor deposition at atmosphericpressure which is in general plagued withproblems of uniformity control and

particulate formation'. The developmentof commercially available reactors forchemically depositing the required layers at

much -reduced pressures (-0.5 torr) hashelped to overcome these problems, andLPCVD reactors have already supplantedother techniques for forming silicon nitride(SiiN4) and undoped polysilicon layers.Work is presently underway at SSTC to

rAll,:ENFItTRIDE BARRIER

DEP POLYSILICON GATE ORDEP REFRACTORY SILICIDE

THERMAL GATE OXIDEI'l7/7/74

cs= ISOPLANARIZING THERMALOXIDE

establish LPCVD techniques fordepositing both doped and undoped silicondioxide (Si02) layers and for depositingdoped polysilicon.

Two variants of the basic tubularLPCVD reactor are available, as shown in

3 1 DEP 3-6% PSG OVERCOAT

E222a DEP ALUMINUM

4

Fig. 6. Diagram of a layered structure formingtransistors.

4

DEP 6% PHOSPHOSILICATEGLASS (PSG)

DEP UNDOPED Si02

a bulk CMOS complementary pair of

ACCESSDOOR

PRESSURESENSOR

>.<.6111.1Mlam

!LIG, OO

>< QUARTZ REACTORTUBE

>.<3 ZONE RESISTANCE FURNACE

GAS INLET

EXHAJSTPUMP

WAFERBOAT

Fig. 7a. End -feed LPCVD reactor.

GASDISTRIBUTIONTUBE

>< INTERIORWAFER ENCLOSURE.

GAS NLET

EXHAUSTPUMP

GAS OUTLET

Fig. 7b. Distributed -feed LPCVD reactor.


Table 11. Deposition processes available in commercial LPCVD reactors.

Layer Input gasesDeposition

Temperature(° C)

Deposition rate**(Al Min)

Reactor type

Undoped Si02 Si1-14,02,N2 400-430 100 Distributed

Doped Si02(PSG)

SiH4,PH 3,02,N2 400-430 90-110 Distributed

UndopedPolysilicon

SiH4,N2 610-640 100-125 End feed

Doped*Polysilicon

Si 1-14,1%12,PH 730 200 Distributed

Silicon Nitride(Si3N4)

SiH2C12NH3,N2

740-800 40-65 End feed

High temperatureUndoped Si02

SiH2Cl2,N2,N20 960 120 End feed

24 ohm/square layers, 3200A thick, post -annealed for 30 min at 1000°C.

The exhaust pump rate in all cases is 35-40 cfm.

Fig. 7. Either type of reactor can handletypically WO wafers per pump -down. The"end -feed" reactor shown in Fig. 7a wasdeveloped first and is used predominantlyat higher deposition temperatures.Chemical vapor deposition processes aresurface -catalyzed reactions, and if the reac-tion rate at the optimum deposition

CONTROLVALVE

LINEVOLTAGEREF

SCR

DRIVER

innSCR

DRIVER

MOTORPOWERMODULE

DRIVE MOTOR

GASSTORAGE

MASSF LOW

METER

TYPICALGAS LOOP

temperature is small compared to the masstransfer rate (the rate at which gas can bepumped through the tube), then the deposi-tion process will be uniform because thedensity of active gaseous species is un-iform, that is, the active species is notsignificantly depleted along the length ofthe tube. The optimum reaction conditions

CHANNELS1 THRU lfi

HEF

JUNCTION

OPENT C

DETECT

CONTROL PANEL

PRE

AMP

2 POLEINPUTFILTER

1 POLE

FILTER

LOWLEVELMUX

PRT AMPLIFIER

HIGHLEVELMUX

depend on temperature; Table II shows theconditions presently considered optimumfor forming uniform layers of polysilicon,Si02, and Si3N4 using the end -feed reactor.

At temperatures lower than 950°C forthe case of Si02 depositions (and attemperatures higher than 700°C in the caseof undoped polysilicon), the pump ratecannot conveniently be made high enoughto raise the mass -transfer rate above thereaction rate. Thus, in an end -feed reactor,non -uniform depositions occur both overthe surface of a given wafer and as afunction of the position of the wafer in thetube. This problem can be solved using thedistributed -gas system shown in Fig. 7band by using an enclosure inside the reactorwhich surrounds the wafers. Two paralleltubes run the length of the reactor, onecarrying silane (SiH4) and the other carry-ing oxygen (02) when Si02 is beingdeposited. These gases are injected into theinterior wafer -enclosure uniformly alongthe length of the tube. Using this tech-nique, the reacting species have a smallerdistance to diffuse in order to reach allareas of all the wafers in the tube, hencesignificant active -species depletion is

SYSTEMALARMS

Fig. 8. Diagram of the electronic feedback systems used in a direct digital control (DDC)oxidation/diffusion furnace (Courtesy Thermco).

12 BITADC

COMPUTERINTERFACE

COMPUTERINTERFACE

DIGITALMINICOMPUTER

<=1 RS 232INTERFACE


reduced over the region of a given waferand hence deposition uniformity is in-creased. Layers of doped and undopedoxide having a ±5 percent variation can beachieved in the 400-500°C temperaturerange using the distributed -feed tech-nique.

In those cases where depositions must bemade in the 300-400°C temperature range,plasma -enhanced LPCVD can be used'.The use of a plasma to achieve chemicalactivation of layer deposition has theadvantage of producing low -temperaturefilms having good conformal coverage. Adisadvantage of the technique is the oddstoichiometry that can result. Instead ofthe desired Si3N4, for example, one usuallyobtains SLAM: or SixIslyHz0..

Because of the large number of wafers -typically ^,1043 - which can be uniformlydeposited on in a single run, and because ofthe low-pressure operation, which usesmuch smaller amounts of reaction gas thanreactors which operate at atmosphericpressure, LPCVD-deposition techniquesare inherently more economical. Also, atthe low pressures used, gas -phase nuclea-tion is far less and hence particulate forma-tion from this source is negligible. Deposi-tion does occur on the reactor walls and onthe wafer boat, but if the tube and boat arecleaned every 20th run in the case ofundoped polysilicon when using a ^,0.6umdeposition thickness per run, flaking is nota problem:The deposits on the hot tubewalls are glassy and adherent, and anyparticles that may form have only a smallchance of falling on the vertically -orientedwafers. With good uniformity and lowlayer defect potential, as well as the goodconformal -coating properties, LPCVD is anatural for LSI applications9.

Direct digital control ofoxidation and diffusion

Although only two of the eight layersdiagrammed in Fig. 6 are formed bythermal oxidation, significant oxidation,diffusion and annealing steps are requiredin the LSI fabrication sequence. The latterprocessing steps require that the wafers beinserted into and removed from high -temperature furnaces generally ranging intemperature from 800 to 1200°C. Besidesthe desired effects of oxide growth ordopant diffusion, this large thermal cyclingof the wafers causes many undesirable sideeffects. These undesirable effects includethe introduction of wafer-slipl° due toinsertion and/or removal from the fur-naces at too rapid a rate, the introduction

of oxidation -induced stacking faults" ifimproper pre -oxidation or post -oxidationambients are used, or the precipitation ofbulk -oxygen cluster -defects if incorrectpost -processing anneals 12.13 are used.These undesirable effects lead to MOSyield loss due to high leakages and in-dividual transistor failure.

Greater control over the thermalprocessing of wafers can be obtained byusing direct digitally controlled furnaces. Adiagram of such a furnace system is shownin Fig. 8. The heart of the system is a micro-processor which organizes the overall fur-nace processing using feedback controlloops. These control loops are used toinsert and withdraw the wafer paddles at aspecified rate, to raise or lower the furnacetemperature at specified rates, to adjust thevarious gas flows as a function of time, andto monitor the actual temperature profileinside the furnace as a function of time. Themicroprocessor can, in addition,automatically clean the furnaces (usinghydrochloric acid (HCI) or trichloroethane(TCA), perform an automatic calibrationcycle and tailor the dynamic performanceof the furnace to a given process step byappropriately adjusting the proportionalband -control constants. Since these

various furnace operations are specified interms of a software instruction sequence,

A. CONFIGURATIONTO BE ETCHED

PHOTORESIST

DIELECTRIC ORINTERCONNECTMATERIAL

Si SUBSTRATE

DDC furnaces provide a high degree ofprocess reproducibility. All of these

features can, of course, be achievedwithout digital control. But with digitalcontrol they can all be easily achieved at thesame time. A disadvantage of digital con-trol is that all control is lost if the computersystem fails.

SSTC presently has 16 DDC 4 -inchdiameter tube furnaces and is activelydeveloping LSI processing using theircapabilities.

Plasma etching-transferringdimension accuratelyfrom mask to wafer

After fine -line photolithographic tech-niques have been used to define an etchmask (Fig. 9a), the next step is to etch theunderlying dielectric or interconnectmaterial with dimensional control. Plasmaetching, or alternatively dry plasma -

processing or dry etching, is a developingtechnology which promises to be criticallyimportant to the fabrication of high -density integrated circuits. Successfulfabrication of high -density LSI requiresetch control of fine lines. This etch controlbecomes difficult or impossible for wetchemical etching if the width of the line to

ANISOTROPY

RATIO A T/D

B FOR WET CHEMICALOR PLASMA ONLY(GROUNDED SUBSTRATE)ETCHING MODES,A -I

C. FOR REACTIVE IonETCH MODE -RIE -POWERED SUBSTRATE),A-00

A -co

Fig. 9. Diagram of the etching process showing the starting configuration (A), and resultswhen isotropic etching (A T/Da.''.) Is used (B) or when anisotropic (C) etching (A -,,x) isused.

Douglas: Advanced process technology at the Solid State Technology Center 1 3

GASINLET

RF ,GAS INLET

PLASMA

REACTIVESPECIES

FLOW

WAFERS

PLASMASHIELD

POWEREDELECTRODES

EXHAUST EXHAUST

100 BARREL (OR TUNNEL) ETCHER CONFIGURATION

(-GAS INLET

CATHODE

F

VC CATHODE ---POTENTIAL

,..--DARK SPACESI

I PLASMA GLOW

el

WAFERS ON POWEREDCATHODE IN RIE MODE

TO RF

INSULATOR

EXHAUST

to

o TO RF INSULATOR0rr

00

RF

ANODEVp PLASMA/ POTENTIAL

ANODE PLATEPOTENTIAL

VS WAFER SURFACEPOTENTIAL

WAFERS ON GROUNDED (OR FLOATING)ANODE IN PLASMA MODE

zrenimmRr

III

EXHAUST

10b RADIAL FLOW, PARALLEL PLATE ETCHER CONFIGURATIONS FORREACTIVE Ion ETCH MODE (LEFT) AND PLASMA MODE (RIGHT).

Fig. 10. Four different variations of plasma -etcher configurations.

be controlled approaches the thickness ofthe layer being etched. This difficulty iscaused by the isotropic nature (Fig. 9b) ofmost wet chemical reactions and by thesurface -tension effects associated withfluid flow which prevents the etchant andthe reaction products from freely exchang-ing in confined surface topologies.

Plasma etching at low pressures over-comes these problems. Plasma processesare used to excite a normally inert gas to achemically active species, and low-pressuresurface -adsorption -desorption reac-tions - coupled at times with sputter-ing processes - allow good control of fine -line etching. By properly selecting reactor

GAS IN

GASINLET

GAS IN-,

CONFINMENTSHIELD

INPUTCHAMBER

(*)

PLASMAEXCITATIONCHAMBER

69;41 69;91 199991 199991

1

EXCITEDETCHANTSPECIES

OUTPUTCHAMBER

(r))

EXHAUST

10t. EXTERNAL GENERATION, CONTINUOUS FLOWETCHER CONFIGURATION.

DISCHARGECHAMBER

TO PWRSUPPLY

EXTRACTIONGRID

BLEED GASINLET

WAFERHOLDINGPLATTEN

EXHAUST

10d. DIRECTED BEAM ETCHER CONFIGURATION.

geometry and source -gas mixtures, a spec-trum of controllable etching characteristicscan be achieved which ranges fromisotropic to highly anisotropic (Fig. 9c).This combination of features has causedthe present intense interest in the deelop-ment of dry -processing techniques forhigh -density LSI-circuit fabrication.

Four different varieties of plasma -etcherconfigurations (shown schematically inFig. 10) are presently available for process-ing IC wafers. The barrel or tunnel reactoris shown in Fig. 10a. For this configura-tion, the wafers are held in a quartz boatinserted in the central "tunnel" portion ofthe cylindrical reactor. The plasma is

Table lila. Plasma generated species interaction with a solidsurface.

Process A B

Etching species Ions

Driving force

Arrival on surface

Interaction withsurface

Species leavingsurface

Electric field

Highly directional

Momentum transfer

Atom clusters

Chemically activeneutrals (radicals)

Diffusion

Random direction

Adsorption -reaction -desorption

Gas molecules

excited, using an r.f. discharge, in a sheathregion which surrounds the tunnel. Thechemically active free radicals (i.e., excitedneutrals) in the plasma diffuse to the wafersthrough holes in the central cylindricalplasma shield and react with the wafersurface causing etching through a reduced -pressure adsorption -reaction -desorptionprocess. The etch products are pumpedaway by the exhaust system. Since noelectric field exists in the central tunnelregion, no ion bombardment takes placeand the surface etching reaction is anisotropic, chemically driven process.

A second configuration, the radial -flow,parallel -plate reactor, is shown in Fig. 10b.

Table illb. Processes occurring in various plasma -etchreactors.

Reactor Process combination

Barrel

Parallel -plate RSEor RIE mode

Parallel -plate plasma

Continuous plasma flow

Directed beam

B

A+B, A>B

A+B, B>A

B

A+B+species activation onsurface after adsorption


For this reactor configuration, the wafersto be etched are placed directly on thesystem circular -plate electrodes. Since anelectric field exists in the vicinity of eitherelectrode (see potential diagram in Fig.10b), the wafers are not only exposed to theplasma -generated active chemical species,but also are exposed to bombardmentsputtering by ions from the plasma. Themagnitude of the electric field in front ofeach plate depends on: the appliedvoltages; the gas pressure; the plate separa-tion; the secondary emission ratios of thewafers and the electrodes; and thegeometric configuration of the reactor, forexample the ratio of anode to cathodearea". The magnitude of the electric fieldin the vicinity of the cathode is generallythe largest, and when the wafers are placedon the powered electrode (cathode) and thereactor is operated at low pressures (0.01 -0.05 Corr), the bombardment assistedplasma etching is called Reactive Sputter( Ion) Etching (RSE or RIE mode) whichyields highly anisotropic etch results''' 16. 17.Verticle-walled structures (A-00) havebeen obtained in Si02 which have an aspectratio (height/ width) of -8'°.

When the wafers are placed on theanode, where the electric field is smaller,and the reactor is operated at somewhathigher pressure (0.1 - 0.5 Corr), chemicalprocesses dominate the etching and theetch results are closer to isotropic etching.By varying the wafer placement, the reac-tor pressure, or even powering both elec-trodes, a spectrum of etch characteristicfrom nearly isotropic (A-1) to nearlyanisotropic (A -00) can be obtained.Tables Illa and Illb summarize the variousetch processes. Although exposing thewafer directly to the plasma adds the extradimension of physical sputtering andenhances the flexibility of parallel -plateetchers, it also introduces the disadvantageof increased radiation damage from thevacuum UV generated in the plasma. Thiscan preclude the use of parallel -plateetchers for the fabrication of rad-hardproducts.

Two variations of the etcher con-figurations already discussed are shown inFigs. 10c and 10d. In the external genera-tion, continuous -flow configuration, thechemically active species are generated inan external excitation chamber excited bya microwave discharge and then aresprayed onto the wafer surface using amanifold distribution arrangement. Theetching properties here are the same as forthe barrel reactor (Table 111b). Thedirected beam etcher configuration shownin Fig. 10d forms a large -diameter ion Fig. 11.

Table IV. Resistivity of various Interconnect materials.

.MaterialResistivity 77

(Mu -em)

Sheet resistance*(0.5pm layer)(ohms/square)

Pure Al (alloy heated) 3.1-3 3 .062-.066

Al -I% Si (alloy heated) 3.5-3 6 .070-.072

AI -2% Si (alloy heated) 3.6-3.9 .072-.078

TiSi2 15-20 0.3-0.4

TaSi2. WS12 50-100 1-2

MoSi2 100-150 2-3

n+ poly (POC13) 800-1000 15-20

(after laser annealing) (500-800) (10-15)

p+ poly (boron doped oxide) 1750-2250 35-45

n+ poly (150eV p", 1.6x1OIS, cm',15 min. 1050°C)

p+ poly (60KeV B". 1.6x101 c

800-1000

1250-1500

16-20

25-30

15 min. 1050°C)

n+ poly ( in situ doping, AMT, 1200reactor, 90 min. 850°C)

1000-1500 20-30

Sheet resistance p, = %i where t = layer thickness.

Resistance R1$.

resistor structure.

p, where L and W are the length and width of the

IG=22ZMIFURNACE AREA

16 THERMCO DOC TUBES(EXPANDABLE TO 48)

(MAIN ROOM CLASS 100)

AIR SHOWERENTRANCE

V A

FLUOROWARE SPRAY ETCHERSMEGASONIC WAFER CLEANERS

MAIN ROOMAIR DUCTS

V A7 A

GOWNINGROOM

V APLASMA ETCHERS

PLASMA THERM1RIE (2)

IPC PLANAR

I IPC BARREL----IMETALLIZATION

VARIAN S-GUNIN -SOURCE

AIR

!SHOWERENTRANCE

CVD AREA

AMS 2001

(LPCVD AREA

AIRSHOWERII CLASS 1000)

ENTRANCE

GOWNINGROOM

WET CHEMICAL AREA

PHOTOLITHOGRAPHICAREA (CLASS 10)

COATER DEVELOPERS:KASPER/III, OCA

ALIGNERS:COBILT CONTACT ( 3)

ELECTROMASK700 SLR (10:1)P E 120,220(1:1)SUSS MJB55 (1:1 PROX)

IV A 111=11111111

PHOTOROOM AIR DUCTS

Diagram of the white room fabrication facility in SSTC,

LPCVD

TEMPRESS(4 TUBESHIGH TEMP)

ASM(4 TUBESLOW TEMP)

GASSTORAGEAREA

Somerville, N.J.


beam using a discharge chamber and anextraction grid. This technique is similar tothe RIE etch mode with the advantage thatthe ion bombardment energy is easier tocontrol and can be adjusted to any desiredvalue. This extra dimension of controlcombined with the single -wafer -at -a -timereactor design, can be used, for example, toactivate (by bombardment) a species thathas been introduced to the wafer surfacethrough a bleed gas inlet and adsorbedonto the surface.

Routine plasma etching of polysilicon inbarrel -type etchers using the CF4-basedchemistry is presently being used at SSTCto fabricate 5µm circuits. Active programs,both within SSTC and in cooperation withthe Princeton Labs and the Zurich Labs,are underway to develop production -oriented, parallel -plate etchers foranisotropic etching of polysilicon,aluminum, and SiO2 films.

Silicide metallizationAs the density of integrated circuits in-creases, the device lateral dimensions andthe layer thickness used must be scaled tosmaller values. This includes the con-ductive interconnect layers of dopedpolysilicon and aluminum. If the layerconductivities (a) or resistivities (0= 1/ a)are not also appropriately scaled, increasedinterconnect resistance will result whichwill lead to poor circuit performance. Insome chips where circuit speed-low RCvalues - is critical, such as micro-processor or short -access -time memorychips, overall interconnect resistivity mustbe reduced even after scaling. As an exam-ple, in present memory chips usingpolysilicon access lines, RC delay accountsfor --5ns of the access time.

Table IV shows the resistivity of variousinterconnect materials. Polysilicon layersare presently widely used for both self -aligned structures and for structures re-quiring multilevel interconnects. Theresistivities, however, are higher thandesired. The low resistivity of aluminumcannot easily be exploited because processtemperatures cannot exceed -450°C afterits use. A third class of materials, therefractory metal silicides, have resistivitiesbetween aluminum and doped polysilicon.These layers can be formed by alloyingsputtered layers of polysilicon and refrac-tory metal, titanium (Ti), tantalum (Ta),tungsten (W) or molybdenum (Mo); by co -sputtering the layers, for example, sputter-ing from a target made of tantalum silicide(TaSi2); or by using chemical vapor deposi-

tion. RCA is exploring all three tech-niques at SSTC or at the PrincetonLaboratories. Refractory-metal-silicide in-terconnect layers are targeted for use in thenext generation of high -density LSI cir-cuits.

The upgraded SSTCWhite Room facility

The successful fabrication of high -densityintegrated circuits requires, in addition tonew processing techniques, a more careful-ly controlled fabrication environment. TheSSTC White Room in Somerville has beenrenovated extensively to satisfy thisenvironmental requirement. Figure IIshows a layout of the SSTC White Roomalong with a listing of the major new piecesof equipment purchased to support theadvanced process technology presently be-ing developed.

The room is divided into three areaswhich are distinguished by the flow rate ofthe recirculated, filtered air. In all cases, theair is passed through high -efficiencyparticulate -air (HEPA) filters whichremove all particulates over 0.2µm in size.Most of the particles larger than this arecarried in by personnel, hence the need fordust -confining jumpsuits and air showersat the room entrances. The air -flow rate inthe main room is adjusted to 65 linear-feet/ min. The main room is Class 100, thatis, an environment with a maximum of 100particles per cubic foot with a size largerthan 0.5µm and a maximum of 10 particlesper cubic foot with a size larger than5.0µm19. In a Class -100 room -1particle/ cm2-hour strikes a given wafersurface20. The LPCVD area has a lowerflow -rate - 25 linear feet/ min - and israted Class 1000. The photolithographicarea, which is rated as Class 10, has its owntemperature (70°±2°F) and humidity37.5±2.5%RH ) control and has an air -flowrate of 100 linear feet/ min. This flow rateexceeds the --BS linear -feet/ min flow ratethreshold for laminar flow, i.e., air flowmoving with uniform velocity followingessentially parallel flow lines with anabsence of eddies. With this type ofprocessing environment, wafer defectscaused by dust should be negligible evenfor large area circuits with feature sizes assmall as 1µm.

Conclusions

A number of the new technology areas thatare presently being explored at SSTC for

.14Ed Douglas is Manager, LSI TechnologyDevelopment in the Solid State TechnologyCenter. He became a Member of TechnicalStaff at RCA's David Sarnoff ResearchCenter in Princeton, New Jersey, in 1969. Hehas worked in the area of lensless, high -resolution projection techniques. He hasworked on the application of ion -implantation techniques to integrated -circuit devices, including the fabrication ofhigh-performance bipolar transistors, thedevelopment of implanted P -wells forCMOS structures, and the development ofimplanted surface guard layers for optimumpacking density of CMOS structures. He hasworked on the development of low -temperature, all -implant processes for fabri-cation of large -array CCD imagers.

Contact him at:Solid State Technology CenterRCA LaboratoriesSomerville, N.J.TACNET: 325-7292

use in fabricating the next generation ofhigh density CMOS integrated circuitshave been described. The challenge ofVLSI CMOS ICs is a formidable one, butformable tools and a continuous series ofprocess innovations are available to meetthis challenge.

Acknowledgment

Many helpful discussions were held withW. Bosenberg(Somerville); J. Vossen, N.Goldsmith and W. Kern (Princeton); andH. Lehmann (Zurich). Their help is

gratefully acknowledged.

References

I. Kalish. I.H., "VLSI -Tools. Technology, andTrends," RCA Engineer, Vol. 24, No. 1, pp. 59-61(June July 1978).

2. Queyssac, D., "Projecting VLSI's Impact onMicroprocessors," IEEE Specirum, Vol. lb. No. 5.pp. 38-41 (May 1979).


3. Resor, G.L. and Tobey, A.C., "The Role of DirectStep -On -The -Wafer in MicrolithographyStrategyfor the 80s," Solid State Technology, Vol. 22. No. 8,pp. 101-108 (Aug. 1979).

4. Snyder, J.R. and Van DeVen, J., "A BetterMousetrap," SPIE, Vol. 174, Developments inSemiconductor Microlithography IV, pp. 75-82(1979).

5. Offner, A., ''The Influence of Partial Coherence inthe Microprojection of Images," Proceedings of theOSA (Jan. 1971).

6. Tobey, A.C.. "Wafer Stepper Steps Up Yield andResolution in IC Lithography," Electronics, Vol.52, No. 17, pp. 109-112 (Aug. 16, 1979).

7. Kern. W. and R.S. Rosier, "Advances in Deposi-tion Processes for Passivation Films,"J. Vac. Sc:.Technol.. Vol. 14, No. 5, pp. 1082-1099 (Sept./Oct.1977).

8. Purggraaf, P.S., "Plasma Deposition Trends,"Semiconductor International, Vol. 3. No. 3. pp. 23-24 (March 1980).

9. Kern, W. and Schnable, G.. "Low PressureChemical Vapor Deposition for Very Large ScaleIntegration Processing -A Review," IEEE Trans.Elec. Devices, Vol. ED -26, No. 4, pp. 647-657(Apr. 1979)

10. Fisher, A.W. and Schnable, G.L., "MinimizingProcess -Induced Slip in Silicon Wafers by SlowHeating and Cooling," J. Electrochem Soc. Vol.123, No. 3, pp. 434-435 (March 1976).

I I. Murarka, S. P., Levenstein, 1-1.1, Marcus, R.B. andWagner, RS., "Oxidation of Silicon Without theFormation of Stacking Faults," J. App!. Phys..Vol. 48, No. 9, pp. 4001-4003 (Sept. 1977).

12. Helminch. D. and Sirtl, E., "Oxygen in Silicon: AModern View," Semiconductor Silicon 1977, Huff,H.R. and Sirth, E., Editors. Proceedings. Vol. 77-2.pp. 626-636, The Electrochemical Society, Inc.Princeton, N.J. (1977).

13. Sugita, Y., Shimizu. H., Yoshinaka, A. andAoshima, T., "Shrinkage and Annihilation ofStacking Faults in Silicon:V. Vac. Sri. Technol..Vol. 13, No. I. pp. 44-46 (Jan./ Feb. 1977).Shimizu, H.. Yoshinaka. A. and Sugita. Y., "For-mation of Stacking Fault -Free Region in Thermal-ly Oxidized Silicon." Japan. J. Appl. Phys., Vol.17, No. 5, pp. 767-771 (May 1978).

14. Vossen, J., "Plasma Deposition and Etching Reac-tors for Semiconductor Applications."Proceedings. 4th Intl. Symposium on PlasmaChemistry. Vepruk and Hertz, J.. Editors,

International Union of Pure and AppliedChemistry, Vol. 3, p. 344-345 (1979).

IS. Lehmann. H.W. and Widmer. R.. "Fabrication 01Deep Square Wave Structures with MicronDimensions by Reactive Sputter Etching." App.Phis. Lett.. Vol. 32. No. 3. pp. 163-165 (Feb.1978).

16. Lehmann, H.W. and Widmer, R., "Profile Controlby Reactive Sputter Etching," J. Vac. Sci.Technol., Vol. 15, No. 2, pp. 319-326( March/ Apr.1978)-

17. Knopp, K., Lehmann, H.W. and Widmer, R.,"Microfabrication and Evaluation of DiffractiveOptical Filters Prepared by Reactive SputterEtching," J. App!. Phys.. Vol. 50, No. 6. pp. 3841-3848 (June 1979).

18. Table Obtained from H. Lehmann, RCA ZurichLaboratories.

19. U.S. Federal Standard 207B, GSA Business ServiceCenter, New York, N.Y.

20. Lounsbury, J.B. and Klein, K.L., "Limitations inPhotolithographic Semiconductor Processing,"Electronic Packaging and Production (March1974)

New Publication fromthe RCA Engineer

According to the RCA EngineeringInformation Survey conducted in1977, RCA Engineering is the secondmost important source of technicalinformation about RCA, (the mostimportant information source beingthe engineer's associates). The backissues of the Engineer -150 ofthem - provide a record of RCA'sprogress in invention, development,and manufacturing. To make thiswealth of technical informationaccessible to the engineers, a 25 -YearIndex to RCA Engineer has beenpublished.

The Index can help you find specificinformation that is needed in yourwork. Or the Index might provide avital contact in another RCA businesswho has related experience and whowould be willing to consult with you.The Index gives you the opportunityto profit from RCA's technicalheritage-to reuse knowledge, tobuild on past accomplishments.

The 25 -Year Index to RCA Engineer isavailable in all RCA Libraries.Recipients of the RCA Engineer canobtain their personal copies bywriting to:

RCA EngineerBuilding 204-2Cherry Hill, NJ 08358


R.A. Geshner

As chip size gets larger and more complex and line -size gets smaller andmore sensitive to lithographic defects, the design engineers andmanufacturing process engineers need to know

What electron -beams can do for LSI

Abstract: The manufacturing electron-beam exposure system is amicrolithography photomask-makingsystem that can delineate, for today's LSImasks, extremely fine lines in complexgeometrical configurations on electron -sensitive resist polymer. The author alsoreviews a constellation of relatedtechnologies.

LSI designer problems

In 1950, a digital gate cost $10, was madewith vacuum tubes and covered 2500mm2.Today, a digital gate costs 1 cent and iscontained within only .001mm2. Today'sdesign engineer must cope with ever-increasing design complexity on semicon-ductor chips that are becoming larger.

Devices (basic functional cells) and theirline sizes are becoming smaller. Designdensity will continue increasing at the rateof 60 percent each year. With just thisincrease in complexity, the design engineerwould be "pulling out his hair" if he didn'thave a complete computer -aided design(CAD) system that allows computerizedpreparation of his design information withalmost immediate translation to hard masktools.

As an example, with smaller line sizes,the tolerance on transistor source -to -drainspacing gets smaller. This means line -sizetolerances must get smaller to allow thesedevices to realize required performancegain and to stay within oper-ating parameter specifications. Addition-ally, as the chip size gets larger there are

Reprint RE -26-2-3Final manuscript received May 29, 1980

fewer chips on the wafer, which meansregistration of each process mask step ismore critical. These factors and defectdensity factors introduced during waferprocessing take their toll in yield, raisingthe price of the semiconductor device. Weneed a lithography system that will keepthe yield high, and also economically willmake larger, more densely packaged cir-cuits.

Typically, the design engineers must alsoprove out their design through an actualsample design -verification production run.They must produce a complete mask setand make wafers. In today's dynamicsemiconductor industry, these design -

verification runs have to be completed inrecord time. The design must be provenquickly to get the product into large-scaleproduction and on the market if we are torealize an effective return on investment. Itmust be possible to modify the design andget masks quickly. The refined design mustbe documented and cast in concrete forproduction runs. Correct designs must beimmediately reproducible from day to dayto maintain production. The computer -aided -design, 1 X mask production systemdeveloped around the manufacturingelectron -beam exposure system (MEBES)helps the designer to accomplish thesefunctions. Conventional masks are thinpieces of clear glass with an even thinnercoating of opaque chromium in which thedesired circuit configuration is delineatedfor a particular step in the semiconductormanufacturing process. The resolution ofthe delineated device structures can be nobetter than the quality of the mask used. Inthe past, masks were made only by opticalmicrophotographic techniques. Some fun-

damental limitations in optics can limit ouroptically making masks for the larger,more complex IC designs. That is why weare in the electron -beam (E -beam) processbusiness today.

New tools inmicrolithography

Electron -beam technology for photomaskgeneration has become a viable state-of-the-art in the last ten years. Several othertechnologies made this possible includingCAD and other electro-mechanical-optical-chemical techniques such as laserinterferometry, cryogenic -ion -pumpvacuum systems, scanning electron -beammicroscopes (SEMs), air bearings, servo -pneumatic vibration -isolation mounting,servo -motor control, microprocessors andcomputers, new polymer resist systems anda lot of ingenuity. We can use this equip-ment now to shoot a finely focused beam ofenergized electrons onto an electron -sensitive resist polymer. This beam willdelineate extremely fine lines in complexgeometrical configurations for makinghigh -density, high -complexity large scaleintegration (LSI) semiconductor devices.RCA has been using a system approach toLSI mask fabrication for about two years.

Electron -beam technology is a completesystem approach because it involves: thedesign engineer who specifies the designdata; the CAD procedures and the designcaptured as a computer -readable represen-tation; the actual lithographic techniquesusing the E -beam; and the process engineerwho uses these new techniques to increaseyield.


The main advantages of RCA's E -beamtechnology are that it can make: masks upto 5 -inch x 5 -inch over a 4.I -inch drawnfield; line sizes down to 0.5µm ± 0.1 pm;masks with defect densities of < 1defect /i nch2; complete mask sets fromCAD tape to first contact prints in less thanthree days in more than 50 percent of thecases; and the most complex masks on anychip size up to 4 -inch x 4 -inch. An outlineof some of the pertinent E -beam machinespecifications is shown in Table I. A pictureof SSTC's MEBES equipment is shown inFig. I. The specific advantages and disad-vantages of E -beam lithography have beenreviewed previously in an RCA Engineerarticle (Vol. 24, No. 3, Oct./ Nov. 1978).

Manufacturing problemsAs designs become more complex andmore dense, design rules (the size of thelines and spaces allowed in the design) willbecome smaller. RCA is actively workingwith 5µm design rules now and is activelymoving toward 3µm rules. A I pm factorydesign is technically possible in the future.The use of 1pm design rules in the 1980swill have a greater impact on semiconduc-tor technology than any other single factorin the last 20 years. Although MEBES caneffectively draw 1 pm lines from a systemstandpoint, other problems should be con-sidered.

Let's look at some of the problems that1 pm lines and spaces in LSIs could causein the immediate future. Defects occur in I X masks and on the

wafer. Masks are manufactured andqualified by automatic 100 -percent in-spection with a 2µm lower -limit defect -detection system (Fig. 2). If we get to I pmlines, on IX masks, then in all probabilityat least 0.5 pm defects must be detected.This may be possible but is probablyimpractical because 0.5µm detectionwould be very time-consuming.

Accuracy in masks, registration, andprinting on the wafer must be held to<±0.25µm. Today the tolerances on"runout" or variation across the mask are>±0.5µm. The wafers vary more than±0.25µm during fabrication due tostresses in the wafer caused by uneventopography and high -temperatureprocess steps.

Metrology problems. If dimensionaltolerances must be held to ±0.25 pm, thenthe measurement techniques must berepeatable to at least ±0.025µm (±1µinch).

Mask defect repair could be a problem.

Table I. Typical E -beam machine specifications.

Drawing area

Table speed

lnterferometel correctionresolution

Raster scan

Maximum chip sin

Pattern input type

Raster butting error

Writing address modes

Pattern resolution in 6000-Apositive resist

Line -size control

Line definition

4.1 in. x 4.1 in. (5 -in. x 5 -in. plates)

4 cm/s (.44 in./min)

1/32 gm

256 gm (10 mils)16 mm ("'0.63 in.) x 32mm (1.3 irj

without special partitioning

Trapezoids

±1/8 gm (.6 gin.)2 (0.5-µm and 0.25 -gm address)

I pm consistently, 0.25 gm with thinnerresist using smallest address

±0.10 gm

±1/8 gm (0.5-µm address)

Fig. 1. MEBES mask and reticle drawing facility in a specially controlled clean roomenvironment. The actual drawing equipment is shown on right and the computer consolecontrol is shown on left.

Fig. 2. KLA-10C automatic 100 percent mask inspection machine. This machine has a defectdetection capability down to 2 gm and produces a hard copy map of all defects detected. It istied directly to a laser chrome defect removal machine (see Fig. 3) and common software anddata is shared between equipment.

Geshner: What electron -beams can do for LSI 19

I Ns

Fig. 3. A Quantronix laser repair machine used to remove extraneous chrome spot defectson a completed mask. This allows preparation of masks with, in some cases, zerodefects/inch2.

Today's practice is to use a laser toremove excessive chrome spots andthereby salvage masks with too high adefect density (Fig. 3). The I gm lines willrequire removal of 0.251.1m defects. Thesedefects will be difficult to detect and maybe even more difficult to remove when inclose proximity to a critical device in aI Aim space.

The problem of testing a chip as complexas a complete computer seemsoverwhelming.

Yield (the number of good die per wafer)is the bottom line. We have listed a very fewobvious manufacturing problems thatcould affect yield. We need the best systemsapproach possible to obtain the best yieldpossible.

PLOTS

00

F

CA

0N

DPS

Electron beamsystems approach

RCA has a complete systems approach forsolving the mask lithography dilemma.The systems approach can handle thedesign complexity problem for today's 3-to -5 µm design rules and can be used for theI Aim design rules in the future. We solvetoday's problems with this systems ap-proach by using 1 X contact and 1 X projec-tion masks. The MEBES 10X reticlegeneration and direct -step -on -wafer(DSW) projection equipment can handlefuture requirements. The keystone of thesystem is the electron -beam equipment.This system encompasses computer design,magnetic tape transfer, archival storage,

CREATION

APPLICON CALMA APAR ROM

V

C

E

0T

Fig. 4. A schematic of RCA's CAD software system used for developing LSI artwork,analyzing artwork design rule variation, checking artwork and preparing magnetic tapeinputs to various pattern drawing equipment including MEBES.

electron -beam mask writing, 100 percentautomatic mask inspection and verifica-tion. We can adapt the system to all waferlithography including contact printing,soft or proximity printing, projectionprinting and direct -step -on -wafer printing.The designer can use CAD to relieve hisdesign complexity problem. The electron -beam gives him the line resolution and thequick turnaround (QTA) he requires, andgives the process engineer the tool -dimensional and defect -density toleranceshe requires. This should allow RCA to getthe best yield possible.

Computer -aideddesign (CAD)

figure 4 shows RCA's mask artworksystem developed and assembled by adedicated design automation (DA) groupin Somerville, New Jersey. The heart of thesystem is a common artwork -specificationdesign -file language (DFL). Designs can becreated, modified and verified through anumber of software programs. The initialdesign can be created by manual, in-teractive graphics, or by automated layouttechniques as outlined on the top line of theschematic (Fig. 4). Similarly,modifications and verification of graphicdesigns can be accomplished by programsshown on either side of the diagram. Forexample, a design may be verified byCRITIC, the design -rule checking pro-gram. It is "batched" by the mask artworkprogram (MAP) for preparation of amagnetic tape that can drive various typesof mask -generation equipment. One ofthese pieces of equipment is MEBES.

In the past, the designer would come tothe "little -old -mask -maker" with a drawingof his design. The mask -maker wouldprepare artwork, make first -stage camerareductions for 10X reticles and makemultiple -image masks on a step -and -repeatreduction camera. In "designing" the mask,the mask -maker had to determine thingssuch as tone, orientation, geometry, grid orscribe -line size, test inserts, alignmentmarks, step -and -repeat size, and so on. Allof these problems are now handledautomatically by the MASK and SAN-DRA programs shown in Fig. 4.

All the mask criteria in these programsare called out or specified by the designengineer. The design engineer not onlydesigns his circuit but he also completelydesigns the 1 X mask. Technology files forstandard technologies, such as LOVAG,closed-circuit logic (CL), linear and


bipolar, aid the design engineer. Thetechnology file permanently delineates thearray format for the particular technologyand standardizes the mask design to reducethe large number of parameters the designengineer must specify. This file reduces thepossibilities for error. A CAD -developedtape given to MEBES has all the arrayinformation and pattern informationnecessary to directly produce, throughMEBES, a complete IX master mask.

Magnetic tape proofing

The tape used to delineate patterns onMEBES can be inserted into "Deformat"(Fig. 4). "Deformat" allows us to checkplotcircuit information on a 72 -inch Versatec'"plotter (Fig. 5) at almost any scale factor in8 minutes. We can check the design visuallywith this drawing (almost equivalent to a"blow-up" of an optical 10X reticle) orcompare the checkplot on the drawing withthe 1 X mask using a microscope. Thissystem will effectively troubleshootdesigns, but will it make useful parts? Onlya design verification part -fabrication runwill assure this and prove the design.

MEBES

We have already reviewed MEBESmachine specifications (Table I). These

specifications are realistic, and reproduci-ble from mask to mask with reasonablemask yield. In addition, we run a vigorousquality control verification procedure onevery MEBES master and carefully main-tain precise control over all maskprocesses.

Quick turnaround (QTA)One MEBES 1X master can be writtenevery hour. Actual run time on equipmentfor a fairly complete 1 X design is onlyabout 30 minutes. A special "Hi -SpeedCorfil" programming method has im-proved MEBES writing time for morecomplex designs. Tests show that, with thistechnique for very dense complicateddesigns, the relative write time can beimproved five times. Here is another exam-ple. Engineers made a mask set for anexperimental RCA -designed 16K staticRAM. This circuit had -100K transistors.Using conventional, optical, pattern -generator 10X -reticle generation techni-ques for a 10X reticle for older, optical 1Xmask -generation it was estimated thatreticles could take up to 76 hours per layer.Optically generating these reticles was im-practical since production time just to getto the 10X reticles was exorbitant. MEBESdrew the 1 X masters much more quickly,averaging 38 minutes a level.

Direct step -on -wafer (SSW)

RCA recently invested heavily in 10Xprojection aligners where 10X reticles areused directly in a wafer aligner rather thanI X masks. These new projection systemscan resolve 1pm lines and spaces.

Therefore, l At m design rules are still possi-ble.

MEBES can write 2X -to -10X reticlessince it will write at any scale. Designautomation has provided special reticlesoftware. The reticles can be written in thesame short intervals it takes to write a 1 Xmultiple pattern. This makes it an extreme -

Fig. 5. A 72 -inch Versatec Plotter that allows preparation of paper drawings of informationon magnetic tape at almost any scale factor in about 8 minutes. This machine is used tocheckplot a MEBES tape input before a MEBES is drawn.

Fig. 6 An ultra precision ITP, digital,microdensitometer line edge sensingmachine used to measure criticaldimensions down to 1'zµ m tc an accuracyof ±2 µinches.

iy efficient reticle pattern -generator. Onthe new direct -step -on -wafer (DSW) pro-jection systems just becoming available, wecan "step" a full field of chips or as many ascan be drawn in the 4 -inch x 4 -inch drawingfield of MEBES -a 2 -inch x 2 -inch arrayof .200 -inch chips (Fig. 9). For this applica-tion, MEBES is the only practical way tomake reticles.

The " I OX reticle system" approachalleviates some problems brought up in ourdiscussion of I pm design rules. That is, thereticle defect size can now be 5 pm andcurrent 2µm detection limits are effective.The DSW machine is now responsible forand holds tight tolerances between masksets. In addition, defects on 10X reticles arerepaired more easily because a I pm line ona 10X reticle is now 10µm.

Other innovations

Metrclogy

As line sizes get smaller, measurementaccuracy and resolution become morecritical. We have already explained whycritical dimensions less than I pm on amask or wafer are difficult to measure. Thenew lithography system approach alsoaccounts for this problem. RCA hasseveral of the most up-to-date cross -correlated scanning electronic -microscopesystems available (ITPT" -Fig. 6). Eachmachine in this system costs upwards of$75K. The system is heat -sensitive andmust constantly undergo a rigorouscalibration procedure.

Geshner What electron -beams can do for LSI 21

Fig. 7. RCA's diffraction grating laser line measurement equipment developed by RCA'sZurich Research Facility capable of measuring line width down to .6 Am to an accuracy of<±5 percent.

We have succeeded with new measure-ment techniques using diffraction gratings.The new diffraction -grating line -widthtester (Fig. 7) is a highly precise and stableelectro-optical apparatus developed byRCA's Laboratories in Zurich,Switzerland. This system will measure atarget grating in an LSI design (line sizes assmall as 0.6 µ m) to an accuracy of <±fivepercent in only 17 seconds. This technique

can be used on the mask and on the waferfor process optimization. The new tech-nique depends on a He-Ne laser andautomatic microprocessors to measureline -width accurately.

Glass inspection

We use various glass substrates for variousmask applications, depending on the

20 40 60

CHIP AREA IN K - MIL 2

80

2X2 3X3 4X4MATRIX OF 60 X 60 MIL CHIPS

5X5

Fig. 8. This is a chart showing the relative yield of MEBES masks vs. conventional opticalmasks. A statistical matrix approach was used to establish this data. The chart shows yielddifferential vs. chip size. Chip size was varied by determining yield based on varying matrixsizes of .060 -inch chips. The entire position of the pair of curves (i.e., relative yield of goodchips) could change dependent on the quality of the process used to make the chips,however, the relationship of MEBES masks vs. optical masks would stay the same.

Fig. 9. A 5 -inch by 5 -inch -10X reticle madeon MEBES in ^O'40 minutes. Preparation of asimilar multi -image 10X reticle for newdirect step -on -wafer machines is notpractical to fabricate by any other availabletechnique other than MEBES

process to be used in wafer fabrication. Theproper glass must be used for eachprocess - the glasses have differentcoefficients of thermal expansion and passdifferent wavelengths of light. In the past,quality control people used an oil immer-sion objective lens to measure the refractiveindex of the glass before shipping it to thefactory, to be sure it was right. Oil madethis time-consuming and dirty. The RCAZurich Laboratories came up with anotherway to sort the glass. A 254-nm light sourcewill make various glass materials fluorescewith colors that depend on the type ofglass. We can, therefore, sort the glassbefore we use it in MEBES and save timeand defective runs because of "wrongglass." RCA has shared this technique withthe glass industry.

Yield improvement studies

J.J. Fabula's group compared statisticalyield on wafers using the same maskpatterns made by both optical methods andE -beam methods. All masks were 100 -percent inspected to assure they hadequivalent defect densities. In fact, theoptical masks really tested a little betterthan the MEBES masks. The groupfollowed rigorous control procedures inprocessing wafers. They used a mix ofoptical and E -beam mask sets within eachbatch of wafers run so that processingcould be eliminated from mask -yield data.In addition, they explored the effects ofcomplexity and size of the chip design bybreaking the experiment into various chipsizes.


The chip design had fairly loose designrules (1976 RCA design rules). The resultsof this extensive test show:

I. The MEBES mask sets gave a higheryield on wafers.

2. High yield with MEBES was even moreevident on the larger chip sizes, with a50 -percent to 80 -percent increase in chipyield on MEBES masks (Fig. 8).

Since KLA'" automatic inspectionshowed the defect density on optical masksto be marginally better than MEBESmasks, this increase in yield on wafers canonly be attributable to the improved chip -location and line -size accuracies in theMEBES mask set.

Other potentialsI. MEBES also can draw a number of

different chip designs on the samemaster, thus allowing a design engineerto check out a number of designs on thesame experimental design run.

2. MEBES has universal scaling and linebiasing so that the engineerautomatically designs at different scalefactors on a separate mask set. He cantest how his design could work withtighter design rules, withoutregenerating new DFL computer runs.

Bob Geshner is Manager of the AdvancedMask Techrology activity in the PhotomaskTechnology and Operations department atSSTC. He has been working in

microlithography for most of the 20 years hehas been with RCA. During his first years inCamden, he worked on microelectricpackag ng and printed -wiring standardiza-tion. Later, he developed the first automatedlarge-scale artwork system using a Gerbernumerically controlled printed -wiringartwork plotter. When his MicroimageTechnology group was moved to Somervillein 1973, he became the Engineering Leaderof the Solid State Technology Centersquick -turnaround photomask facility. Hewas responsible for the development of thenew MEBES facility. In 1978 he was ap-pointed to his present position.

Contact him at:Solid State Technology CenterRCA LaboratoriesSomerville, N.J.TACNET: 325-6514

Ultimately, the designer can put morechips on the wafer to increase yieldprovided his design can be adapted tothe tighter design rules.

ConclusionsThe design engineer and the processengineer now have a useful system,MEBES, for coping with the complexitiesof current and future LSI designs. We can

hope for even more advantages. We mustbe alert to new technology in lithographyto stay cost -competitive. In the future, newwafer technology in I X projection printingand 10X direct step -on -wafer printing willrequire us to use a completely integratedlithographic system with higher resolution,quicker turnaround, lower defect densitiesand greater precision. Electron -beamlithography fits into this future, and givesRCA the necessary competitive tools.

Geshner: What electron -beams can do for LSI 23

W.A. Bosenberg

The Road to LSI:A Photographic Journey

The long road from discrete components to LSIfunctions started with the invention of the transistorin 1948, passed through the development of thesilicon planar technology in the late 1950s and brokeinto the open with the integrated circuit technologyof the late 1970s. Since then, it has been an openroad to the present sophisticated LSI technology.

Technological innovations achieved along the pathto LSI have cleared a firm roadway now used toarrive at today's complex LSI product. Thephotographs and captions on these pages trace theessential steps in the current process as it is carriedout at RCA's Solid State Technology Center.

2. Mask generation depends on electron -beam precisionexposure. The location of the beam is monitored by aninterferometer to 1 /32 of a micrometer. For better accuracy,chromium on glass masks is preferred to emulsion on glassmasks.

1. As integrated circuits becomedenser and more complex, so do theblown -up checkplots run on the com-puters. The various mask levels aresuperimposed and have various cross-

__ hatchings. Layout errors are markedon the plot and corrected in the artworkfile.


3. Patterning precision is achieved by photoengrav-ing. The silicon wafer is coated with an ultraviolet-s9nsitive phctoresist. This process is highlyautomated.

11 am

41111.

%

5. Alignment must bedone under a microscope.The Suss aligner fromWest Germany allowswafers to be fed from onecartridge into another.The alignment and ex-posure can be done eitherin contact with the waferor at a distance of about20 µ m.

4. The wafers are moved one at a time throughovens, then spin -coated. Next, the wafer is exposedunder a precision aligner and developed, all in thesame piece of equipment.

6. Mask defects will print on wafers. If aperfect mask never touches the wafers, betteryields can be expected This Perkin-Elmeraligner uses scanning -projection mirror opticsthat allow deep -ultraviolet exposures forbetter resolution.

7. Even finer lines can be printed on thisElectromask step -and -repeat aligner. A fieldof 3/8 inches by 3/8 inches contains four -to -nine LSI chips. Forty to a hundred fields areused per wafer. The positional accuracy isachieved by an air -bearing table and an in-terferometer. Linewidths down to 1.25 om canbe printed.

Bosenberg: The Road to LSI: A Photographic Journey 25

8. Diffusion is a 1100° C heat treatment that distributessemiconductor donors and acceptors for making p -njunctions. Since it is more economical to use large -diametersilicon wafers, diffusion furnaces have become very large.This computer -controlled four -stack furnace not onlyallows exact gas -flow control and precise insertion andwithdrawal of wafers, it also uses a computer to controltemperature.

10. This FSI spray -etch station looks like awashing machine. It allows 150 four -inch wafersto be cleaned, etched, rinsed and dried in oneoperation. Again, a computer terminal controlsthe operation and prevents incompatiblechemicals from being sprayed together.

9. Chemical hoods are made of corrosion -resistantplastics. They have laminar flow bonnets over theperforated work surface. Wet chemicals requireclose temoerature control for consistent etch rates.

\-717 ...

0 p....... ou

lei me Ti"":"...

11. Ion implantation precisely controls dopinglevels. Arsenic, boron and phosphorus are the mostcommonly implanted species. The depth of theimplant depends on the acceleration voltage. Theconcentration can be measured as accurately as anelectrical current.


12. Chemical -vapor deposition is used to depositpolysilicon, silicon dioxide, silicon nitride andphosphorsilicate glasses. By reducing the pressure,100 or more wafers can be treated in one cycle. Theuniformity of such low-pressure chemical -vapordeposition (LPCVD) systems is much better thanthat of atmospheric systems. Again, micro-processors control the process.

14. Most integrated circuits are limited in theirdensity by how fine a metal line can be defined. Thisline must be continuous even over steps. No twolines can be shorted by a defect. This Varian S -Gunsystem allows the precise deposition of silicon -aluminum alloys for integrated -circuit fabrication.

13. Dry (plasma) etching has become more and morepopular. It eliminates some of the wet chemical disposalproblems. Fine geometries require the vertical wallsachievable in reactive -ion etching (RIE) systems.

15. DC -parameter testing is the first important testafter the fabrication procedure is finished. NMOS andPMOS transistor parameters are measured. They mustbe closely controlled if an integrated circuit is tofunction.

Bosenberg: The Road to LSI: A Photographic Journey 27

16. The wafers are tested functionallyon this Datatron tester. The test se-quence must include all possible com-binations. For VLSI circuits, such asmemories, the total testing time wouldbe prohibitive. To solve this problem,intelligent test sequences have beendeveloped in computer software.

18. Then the integrated circuits are encapsulated-usually in plastic. Random samples are pulled for lifetesting.

Wolf Bosenberg is Leader, Technical Staff at the Solid StateTechnology Center (SSTC). He has worked in the field of solid statephysics and technology since 1949. From 1952 to 1957 he workedfor IT&T in Germany. Dr. Bosenberg joined RCA in 1957. He hasbeen in engineering, an engineering leader, in engineeringmanagerial positions both at Somerville and at Princeton observingthe long road from the germanium point -contact transistor to thepresent sophisticated LSI technologies.Contact him atSolid State Technology CenterRCA LaboratoriesSomerville. N.J.TACNET: 325-7027

Reprint RE -26-2-4Final manuscript received August 26, 1980

17. Dicinc: Me wafer and mounting the pellets onto headersis done nee. Then wires are bonded between the integratedcircuit chin and the oackage leads. This is by far the mostlabor-senti'ive area of integrated circuit fabrication. ForSSTC intewated circuits, visual inspection procedures arerigorous.


R. McFarlane

Computer -aided wafer processing

Complex solid-state products will require ultra -precise,closed -loop manufacturing facilities guided by computersreacting to direct -measuring product sensors.

Abstract: The process -hardware portionof an SSD program focusing computertechnology on wafer manufacturing isdiscussed relative to its development andcurrent status.

During the early seventies the Solid StateDivision (SSD) initiated an energeticprogram to apply computer technology towafer manufacturing. This consistentlyfollowed SSD objectives to competitively

Table I. Computer benefits summary.

manufacture devices by current wafertechnologies and to reduce costs and im-prove profitability. The ongoing programencompasses product management, maskmaking, the broad spectrum of waferprocessing and in -process as well as finaltesting. Command, supervisory and, even-tually, closed -loop computer -aidedhardware are being developed and applied.At the time, the program called forrecognizable short-term improvements,minimized manufacturing disruption and

maximized long-term benefits. Asanticipated by the more computer -orientedsupporters of the program, initial benefitsfar surpassed expectations (Table I).

Quantification of the results, althoughextremely difficult because of the dynamicsof wafer manufacturing, is currentlyprogressing.

Our comments concentrate on theprocess -hardware portion of the com-puterization program. The highly criticalcomputer hardware and software portions

Cost re-duction

Labor (Eng.-DL-IDL) X

Operator skill (reduced) X

Operator error (lockout) X

I )1 i ect material efficiency

Diagnostic capability X

I )ecisior making

Process change capability X

I ighter nttrameter control

Reduced quality checks X

\ccurate process history

Lot control X

Instant ,iisentor

Best route scheduling X

I quipment mill/mum

Floor space X

Inrres conserNation

Preventive maintenance X

Improvedyield

X

Quality &reliability

X

Consistentproduct

X

X

X

Improvedcustomerresponse

Increasedthruput

X

Flexibility

s

X

DL = Direct LaborIDL = Indirect Labor (Technician, Maintenance)

Reprint RE -26-2-5

Final manuscript received Aug 18,1980

RCA Engineer 26-2 Sept./Oct. 1980 29

Table II. Control concepts.

RAW MATERIALSFunctions

Concept Instruct Alarm Adjust

Command X-110 PROCESSING FACILITY-01 FINISHED PRODUCTSupervisory X X

Closed loop X X XRECIPE

RAWMATERIALS

RECIPE

RAWMATERIALS

RECIPE

(a)

PROCESSINGFACILITY

SENSE

ALARM

(b)

FINISHEDPRODUCT

PROCESSING FACILITYFINISHED

PRODUCT

£ £ PROCESSADJUSTMENT

SENSE

FEEDBACKSENSE

PROCESSPARAMETER

PRODUCT BEINGPROCESSED

(c)

Fig. 1. Functional flow of the elements of the various hardware systems: (a) command,(b) supervisory, (c) closed loop.

SENSORFOCUSADJUSTMENT

TABLE

Fig. 2. Mask -pattern generator - command system

LIGHTSOURCE

SHUTTERX,Y,

WORK PIECE( PHOTO /CHROM E

PLATE)

COMPUTER

continue to be studied by the Solid StateTechnology Center (SSTC) computergroups.'

Table II summarizes the elements ofcommand, supervisory and closed -loophardware systems, and the block diagramsof Fig. I illustrate the functional flow ineach of these systems. A close examinationof manufacturing conditions, the state-of-the-art and practical constraints led to theconclusion that a combination of the threesystems would be essential. Looking to thefuture, however, SSD concluded thatclosed -loop systems deserved emphasis.

An initial survey of existing technologiesrevealed two excellent examples of com-mand and closed -loop systems (Figs. 2 and3). Each had worked in a manufacturingenvironment for several years and each wasself-contained. The mask pattern generatorin Fig. 2, a command system, is turned onand commanded by a computer tape thatuses an X, Y and 0 system for table motionsand an X, Y and 0 system for shuttergeometry adjustments. The systemproduces a reticle that, upon inspection, isaccepted or rejected. If the reticle is re-jected, operators appropriately alter thetape and run it again to produce a reticlefor re -inspection. They repeat the processuntil the system produces an acceptablereticle. Then they file the final tape forfuture use. Recently, the tape generationsystem has improved to the point wherererun is rarely necessary.

The crystal puller (Fig. 3), a closed -loopsystem, is also started by signals from acomputer tape, but sensors closelysupervise it and continuously feed informa-tion back to a computer that consistentlyalters process parameters to satisfyidentified needs. If we have reliablehistorical data in the computer memory wecan accurately compare product perfor-mance to the product specifications.

SSD found several quasi -supervisorysystem examples but none that had thealarm mechanism built into the computercircuitry. Therefore, we could not tell theeffects that real-time logging of processinterruptions and computer -guidedparameter adjustment prior to restart hadon wafer yield. We soon had an opportuni-ty to make such a study - the high-speed


bipolar (HSBP) diffusion system (Fig. 4)installed at Somerville during 1975 as thefirst step in the overall computer -aidedmanufacturing (CAM) program.

The HSBP diffusion complex, a

supervisory system, follows a

programmed, machine-readable processcard containing basic step-by-step in-structions. Audio and visual alarm systemsalert the operator to malfunctions and,based on conditions at the time, the equip-ment continues processing, holds or shutsdown. The system logs real-time. Thishelps the operator diagnose the malfunc-tion and prepare corrective -action in-structions needed to save the product.

After months of investigatory effort,detailed planning (including software,hardware, and process -parameterspecification), design and layout, ourCAM education really began the day westarted -up the initial hardware comple-ment. Grounding difficulties and noiseproblems occurred. Software, hardwareand interface malfunctions hampered per-formance and had to be systematicallyidentified and corrected. Experience withthe HSBP diffusion system prompted im-provements in the Palm Beach Gardensdiffusion system, and both experiencesinfluenced the architecture of the highlyeffective, low -defect direct digitally con-trolled (DDC) line at Findlay, Ohio. TheFindlay system currently incorporatesproduct management, data logging,process monitoring and control, lockout,equipment loading, equipment diagnosticsand total supervision features. Engineersbrought -up the unit there over a two-yearperiod and added the supervisory elementswhen needed.

Results have far exceeded initial expec-tations. But we've drawn two basic con-clusions concerning the hardware: (I)additional progress toward closed -loopoperation depends on breakthroughs in thesensors, and ( 2) some operations may neverbe totally closed -loop systems becausethere may never be a practical way tomeasure certain product characteristics.Table III lists process parameters andproduct characteristics that require con-tinual control. Some characteristics, suchas degree of photoresist polymerization,elude measurement and, consequently,machine -guided process parameter ad-justments must be based on residenthistory. In most cases, we cannot evendirectly measure temperatures. We mustapproximate temperatures based on thereaction of pre -calibrated instruments,such as the thermocouple shown in Fig. 5.Film -thickness control is even more

POWER ALARM

COMPUTER

ARGO

PWR1412%

MOTION CONTROL

WATER

INGOT

MOLTEN SI LI CON

// / J_/7

/////

Fig. 3. Crystal puller - closed -loop system.

POSITIONSENSOR

OUT

BOATPUL LERCONTROL

WAFERS

HEATERS

L'VVVI ..FURNACE

POSITIONSENSOR IN

TEMPERATURECONTROLLER

MA.

RAMPINGSEQUENCER 4

--I AMPLIFIER

COMPUTER

ALARMI/O CRT

DEP. TELETYPECARD TAPE

4FLOW

REACTOR

4FLOW N2

FLOW

VALVESEQUENCER

02

Fig. 4. Diffusion complex-supervisory system.

McFarlane: Computer -aided wafer processing 31

Table III. Major process parameters andcharacteristics.

Temperature PressureTime Flow rate Viscosity Composition Particle content Transparency Velocity Acceleration Distance Liquid level Resistivity Thickness Contamination Change in any of the above

precarious since it depends upon in-struments that measure indirectly andprovide, at best, only rough ap-proximations of what is taking place on thesurface of the product.

Clearly, the manufacture of more com-plex solid-state products will require ultra -precise, closed -loop facilities guided bycomputers reacting to direct -measuringproduct sensors. Current plans to addressthe process -control challenge of the 1980sand 1990s include in-house concentrationon the sensor, software' and computer -hardware areas, as well as careful selectionof computer -compatible process hardwarefor product manufacture.

Acknowledgments

The following activities and individualshave had, and continue to have, a majorrole in the development of the Solid StateDivision CAM facility:

RCA Corporate Staff-Cherry Hill, N.J.J. Thorne, L. Dillon, J. Millerand associates

Solid State Technology Center -Somerville, N.J.

J. Gaylord, R. Sunshine, J. Goodman,V. Grobe (Mountaintop), J. Rudolph(Findlay) and associates

Ray McFarlane was Manager, EquipmentTechnology, for solid-state signal ICs andspecial products before leaving RCA inAugust, 1980. During his 24 years with RCA.he was intimately involved in product andprocess design, as well as manufacturingfacility development as related towaveguides, computer components, elec-tron tubes, solid-state energy converters,integrated circuits and power transistors.His solid state experience includes allphases of product and facility development,including photomask generation and silicongrowing through assembly, packaging andtesting.For more information:Joe Koskulitz. Manager,Equipment TechnologySolid State DivisionSomerville. N.J.TACNET: 325-6422

TEMPCONTROL

A

JLi A

TEMPERATUREMON ITOR

Fig. 5. Internal, protected thermocouple.The internal temperature of the tube isapproximated from the temperature of thewall of the tube.

Equipment Technology - Somerville,N.J.

R. Shambelan, W. VanWoeart, J. Kau

High Speed Bipolar Operations -Somerville, N.J.

H. Uhl, P. !dell, R. Lamont

SSD Materials and ProcurementJ. Watkins, S. Townsend, C. Edwards

SECTION "A A"

ReferenceI. For a greater insight into, and specific detail

concerning, the computer software and hardwareareas of CAM, the reader is referred to the ProcessMonitoring and Control (PMC) organizationlocated in the Solid State Technology Center inSomerville, New Jersey, Mr. John Gaylord,Manager. Also see "Process Monitoring andControl -- A Computer -Based System for Manufac-turing," J. Gaylord, RCA Engineer. Vol. 24, No. 6(April May 1979); and "ERIC: A Process Monitor-ing and Control System," J. Gaylord, RCAEngineer, Vol. 25, No. 4 (Dec. 1979/Jan. 1980).


L.M. Rosenberg

The evolution of design automationtoward VLSI

The incremental historical growth of design automaton atRCA w.:11 continue as VLSI design becomes imminent. Wewill see improved approaches to logical and physical designto reduce front-end costs, cost-effective design -for -testability approaches, and more.

Abstract: This paper presents the author'sopinion ojthe major problems confrontingdesign automation (DA) for VLSI andhow DA may evolve to meet thesechallenges. The paper first takes ahistorical look at the drivingforces for DAdevelopment by analyzing the evolution ofDA at RCA . It looks at some successfuland unsuccessful developmentefforts and attempts to isolate some of thecriteria necessary for success. It reviewsRCA's current LSI DA abilities andcompares them to the challenge of VLSI.The major challenges - layout, designverification and testing - are discussedalong with possible achievable solutions.

Introduction1 he challenging question posed by VLSI is:how can we cope with the continuingexplosion in complexity of ICs? Althoughthe challenges facing technology develop-ment are substantial - lithography, bothimaging and registration, etching fine lines,

Reprint RE -26-2-6Final manuscript received June 12. 1980,

An overview of this paper was presented as the opening,invited paper of the 17th Design Automation Conferenceand a similar version was published in the Proceedings ofthat Conference, pp. 3-11. June. 1980. Permission torepublish is granted by the Association for ComputingMachinery

implantation, multilevel fine -line inter-connect, and so on - we have no evidencethat any fundamental physical barrier willprevent IC complexity from continuing togrow exponentially in time. Device -countper chip may double every two years or sofor the next decade or more until designrules of one -quarter to one-half micron areachieved.'

Many observers, including myself,believe that the rate -limiting factor con-straining the growth of IC product com-plexity may well be the design automation(DA) tools required for design (system,logic, circuit and process) and its verifica-tion, for physical implementation (layout)and its verification, for test generation andits verification (fault coverage) and for testdata analysis. These substantiallychallenge the design automation tool -builders and their users because of the largeand growing amount of data involved. Forthe purposes of this paper, allow me tooperationally define VLSI as the IC com-plexity of the near future, that is, one -to -two orders of magnitude mon complexthan our design automation systems cancomfortably handle today.

Some history

I start in 1970 - the year of the SeventhAnnual Design Automation Conference(DAC) (then called a workshop) - clearly

not at the beginning. Extensive work hadgone on in areas such as interactivegraphics, automatic layout, and circuit andlogic simulation. At this time, however,most of the enthusiasm for DA came fromthe DA tool -builders at large corporateresearch centers, not from the design com-munity.

I suspect circuit designers themselvesbuilt the most useful DA tools at customfacilities such as system houses. This isbecause the low volume and quick turn-around required of custom designs forceddesigners to find computerized solutionsthat gave them design leverage. The newlydeveloped techniques such as standard -cellautomated layout substantially increasedchip size (and hence incremental cost), butwere not an issue because low productionvolumes were required. This penaltyjustifiably discouraged commercialsemiconductor houses - the main focus ofthis paper-from pursuing automatedlayout. IC complexity was modest enough(perhaps 100-150 devices) so that layoutaids, logic simulation and circuit simula-tion were not viewed as crucial or evennecessary. These tools were considered tooinaccurate and expensive to be cost-effective.

The commercial semiconductor housecould do - quickly, simply andinexpensively - rubylith cutting forphotomask generation. Although workwas going on in interactive graphics, what


could one do with the resulting digitizedmask -artwork polygons except use com-puterized ruby -cutters?*

Digitizing these polygonal shapes wastedious and time consuming. Worse,editing these computer representations waseither tedious if done on a source -languageformat, or expensive because interactivegraphics systems were extremely costly andonly CAD researchers could afford them.The advent of and necessity for the patterngenerator really made DA viable for thecommercial semiconductor manufacturer.It was the first true DA necessity -because manufacturers needed to copewith MSI complexity from a manufac-turing point of view. Let me explain.

What is the limiting practical complexityfor the rubylith? If the largest practicalruby sheet is approximately ten feet on aside, if the smallest practical ruby grid -stepis close to 0.1 inch, and if the requiredsilicon grid step is 0.1 mil (2.5 micron tosupport 7-10 micron design rules), then weneed a ruby scale factor of 1000X and amaximum chip size of about 100 mil on aside. As MOS complexity pushed pastthese limits, pattern generation of a 10Xreticle became necessary.

But, how were we going to feed thepattern -generator "beast"? How were we toget the artwork into a computer? At RCALabs an English -like language calledPLOTS2 was developed. Examples of thislanguage are shown in Figs. I and 2.

Photoplotters. making up to BOX foils. were used atcarious government installations such as RCA'sGovernment Systems Division as far back as 1967 or so.-I hese photoplotters were fed by the DA system whichautomatically laid out standard cell chips. But I know01 no semiconductor house using them at that time.

Although easy to learn and use, especiallyfor regular structures such as memories, itsoon outgrew its ability to convenientlysupport random logic designs when com-plexity reached the MSI level. DA system -builders had to come up with a low-costsystem to capture hand -drawn designs inthe computer. We therefore developed asimple, inexpensive interactive graphicssystem (based on a PDP-8 with 4Kmemory, a Calcomp digitizer plotter-hence, the name, digitizer plotter system(DPS) - and a hand-held joystick' (seeFig. 3). By today's standards, its"interactive" editing abilities were asprimitive as its hardware configuration.But mask artwork could now be quicklyand accurately captured by a computer.One element of human error waseliminated.

The state-of-the-art DA problem nowwas to develop pattern -generationsoftware which could translate a general,all -angle polygonal shape into a minimalcovering -set of rectangles with the furtherconstraint of minimal overlap at the edgesof the polygon. This problem requiredthree generations of production software atRCA before we finally achieved an optimalsolution. We did not limit ourselves toorthogonal or 45 -degree geometries(nonacute) because certain technologies,such as bipolar with lateral complementarytransistors, require all -angle polygons.

This latter constraint - support of manytechnologies - has had other effects onour DA strategy at RCA. DA at RCA dealswith metal and silicon -gate MOS,CMOS/ SOS, "Linear" Bipolar, I2L, High -Speed Bipolar and various powertransistor technologies. Because of this

PLOTS POLYGON EXAMPLEM5

P X20Y20 TO X100Y20 TO X100Y100 TO X 80Y100 TO -OR P X20Y20 TO X100 TO YIOO TO X80 TO OR P X20Y20 R80 U80 L20

100 -

80-

60

40-

20-

i

20 40 60 80 100 1(

Fig. 1. Because of the power of PLOTS, the three differentstatements shown can be used to specify this polygon on mask -

level 5. The first explicitly gives all vertices: the second eliminatesthe specification of duplicate coordinates and the third givesrelative movements.

diversity, we have endeavored to keep oursoftware as technology -independent aspossible.

Concurrently with this work, thefeasibility of a computerized design rulechecking (DRC) facility was investigated.Initially, it was too difficult in the generalcase; there were too many special cases.Additional data from the designers wasessential. But as complexity continued toincrease, the number of digitized design-rule violations became a major problem.Furthermore, continuing growth wasrapidly moving us past that awesome levelof integration now called MSI. DRC hadto be developed-even if it only solved asubset of the problem -and it was.'

DRC was the first truly new capabilitythat storing the artwork in a computerbrought us-the pattern generatorresulted in the same functional reticle wecould get from rubylith. Now the computercould do something truly new: automateddesign -rule verification. We also dis-covered we could do more verification withthe data at hand than we originallyguessed.

At this point, it was dramatically clearthat DA possibilities were unlimited.Researchers quickly conceived techniquessuch as connectivity verification, deviceextraction from the artwork layout,automated artwork geometry modificationand a common data base linking all these tocircuit and logic simulation. Allow me tofocus on this.

Common data base

Many of us at this point clearly saw thatcomputer -aided design and verification

PLOTS CENTERUNE EXAMPLEM7W 10

L X20Y20 R40(R20U60) R20

100-

eo

-20-

-

AND R100

I VII 4111120 40 60 80 100 120 140 t60 180 200

Fig. 2. The polygon with constant width (left) can be represented,using PLOTS, simply by giving the coordinates of its "centerline"and its width. The polygon 100 units to the right was specifiedsimply by appending the phrase "AND 100."


4fr

Fig. 3. Using the RCA -designed digitizer -plotter system (DPS), the operator can quicklycapture artwork into the computer.

systems had an important role to play inthe future of IC design. First, automatedDRC proved that it was possible andachievable. Second, we began to inter-nalize the fact that IC progress wasrelentless, and that the next year wouldbring even more complexity. We all feltthat our DA tools were barely adequate forour needs that year, let alone the next.Hence, the DA systems we then envisionedhad to cope with chips far more complexthan those existing at the time. A newsystems -approach had to be taken. We hadto confront increased circuit complexityand we had to unify the worlds of circuit,logic and physical design. In addition, wehad to cope with the problem of dataintegrity.

We decided that we needed a centralized,"strongly -coupled" design data base,

hierarchical in structure, to solve all theseproblems. We called this the computer -aided design data base (CADDB).5 Asystem diagram is shown in Fig. 4. Thisstrategy "solved" many problems. Theexistence of only one copy of the design(centralization) ensured data integrity;"strong coupling" between the physical andlogical design representations guaranteedthey would remain in sync. The "common"data base also guaranteed that only oneconversion program had to be written foreach existing or new CAD tool, for exam-ple, logic simulation, circuit simulation,system simulation, automated layout andso on -the tool's input data structureneeded only to communicate with the data

base, not with N other programs, whichimplies N2 conversion programs in theworst case. The hierarchical structurewould solve the complexity issue. Finally,we could characterize the overall designprocess and postulate a new unified, dis-ciplined methodology. This would requirea substantial effort and would lead to aquantum leap in capability. The CAD

CAD

r -DATA BASE

CONSISTENCY

EDIT/INQUIRY

LOGIC

SIMULATION

project team set their sights on success inthree -to -five years. In contrast, most of theremaining CAD effort continued to focuson incremental progress, based on specificneeds, with these new tools going intoproduction in one -to -three years.

The CA DDB system was developed inthe expected time frame. Hopes were highfor its successful introduction into theproduction system. It was successful to theextent that it worked on all our test cases.However, it was not accepted by our designcommunity, although many of its conceptsand some of its software components havebeen adopted. What went wrong?

I am not really sure, but I suspect thefollowing problems contributed. It is acomplex system unifying many differentapplications -programs - which supportboth logical and physical designs-andhence presents a steep learning curve todesigners. In addition, it requires a signifi-cant amount of preliminary work, such aslabeling functional blocks and identifyingand naming their electrical pins. This one-time cost is particularly significant for atest case. In addition, although the data-base management system we chose is high-ly efficient for commercial applications, itis not efficient for certain CADapplications -programs. It requires toomany I/ 0 events and too much memory.

As it was a totally new system, ex-perimental cases encountered a significantnumber of bugs. Unfortunately, it is a

CAD DATA BASE SYSTEM

TEST

GENERATION

EMI AUTOMATIC

MASK LAYOUT

AUTOMATIC

MASK LAYOUT

NETWORK

COMPARISON

Fig. 4. The common "data base" is at the center of the CAD system and is designed to tietogether all the capabilities shown.

Rosenberg: The evolution of design automation toward LVSI 35

highly integrated design system: one couldnot select the single benefit of the systemthat was desired, such as connectivityverification, and ignore the rest. It is an all -or -nothing system. Finally, although it wasa system designed to unify the worlds oflogical and physical design, designers werenot using logical simulation extensively atthat time and hence much of this benefitwas not immediately evident. For these andother reasons, this quantum leap incapabilities was simply too high for ourdesign community to achieve.

Meanwhile, the CAD developmenteffort - which defined needed, incremen-tal capabilities - continued to expand ourset of design tools into the highly successfulsystem it is today. Data from our software -usage monitoring system show that in1979, over 30 of these CAD programs wereaccessed over 100,000 times by over threedozen engineering organizationsthroughout the RCA Corporation.

Based on these and many other ex-periences in DA software development -some quite successful, some not-can wediscover any general principles to help us tosucceed in the future? This is not an easychallenge. Here are a few of my ownobservations.

Criteria for success

First of all, I define a successful DA tool tobe one which is used actively by manydifferent design teams on a variety ofdesigns, not simply one which has beentested successfully on a single, benchmarktest vehicle. I believe that several criteriamust be met before a DA tool can besuccessful.

I. The design community must perceivethat the DA tool will cost-effectivelyresult in a tangible benefit.

2. The approach must be technology -independent.

3. There must be close communicationbetween the DA tool -builders and thedesigners.

4. Ninety percent of a DA tool's "paper"capabilities can be developed with ap-proximately fifty percent of the totaleffort. This implies that it takes"forever" to finally get the last few bugsout and to add the last few "bells andwhistles" required for user acceptance.It also implies that the creative DAdevelopers who got it to the 90 -percentpoint are probably bored with the wholeproject and are eager to move on to the

next challenge, and to let the "secondteam" finish the project.I believe that the last 10 percent is

"make -or -break" for many DA tools andthat the second team may not have theperspective or experience to make thecompromises required for success. In fact,often some of the most challengingproblems - involving designeracceptance - occur during the introduc-tory phase of the development - the "lastten percent."

Current capabilities

At this point, I Huuld like to describe LSIDA at RCA, equate this system to thecomplex designs and point out where I feelour greatest challenges will be on the roadto VLSI and beyond. I will then use someof our historical perspectives to project thefuture evolution of DA.

Artwork

At the heart of RCA's artwork system,shown in Fig. 5, is an artwork representa-tion called Design File Language (DFL).'It is an efficient, compact, program -readable language. Its primitive com-ponents include general -shaped (all -angle)polygons, orthogonal polygons, centerlines with width, general purpose"comments" (to permit new extensions towork with old versions of software), and ageneral "definition" (building-block) func-tion with an instance -specification (with

M0

F

C

D

T

N

Fig. 5. RCA's mask artwork system.

nesting up to 12 levels deep). All this isforward -looking for a language developedover ten years ago. This language hasremained upward- and downward -compatible over the years, although newfeatures have been added (using the "com-ment" extension capability). Recentlydeveloped DA programs can read a ten-year -old file while a ten -year -old programcan read a recently created file. We believelong range compatibility of both softwareand data is an essential issue in a realproduction environment.

Although DFL is "friendly" to DAsoftware, it is not really friendly to humans.Therefore, the PLOTS language2, alreadyreferred to, was created as a free -format,textual language for designers, which has aone-to-one function equivalence to DFL.One may view PLOTS as a source language(for example, assembly language) and viewDFL as its machine -language counterpart.

This language is useful for designingsimple structures or ones that are highlyrepetitive (such as memories). The arrowsbetween DFL and PLOTS in bothdirections in Fig. 5 indicate that both aPLOTS compiler and decompiler weredeveloped.

In order to design more complex struc-tures we developed, during the late 1960s,the digitizer -plotter system (DPS) thatdirectly works with DFL. By the mid -1970s, growing IC complexity made theDPS systems obsolete. We consideredupgrading them and we also evaluatedturnkey systems. Our analysis clearlyshowed that purchasing would be more

CREATION

ELECTROMASK GERBER

TRANSLATION

V

R

F

C

E

T

N


economical than upgrading, so we

purchased our first vendor -suppliedinteractive -graphics system. One suchsystem (Applicon) is shown in Fig. 6. InFig. 5 the arrows in both directionsbetween the interactive graphics systemsand the DFL boxes indicate that wedeveloped conversion software to translatefrom their internal artwork representationsto DFL and vice -versa. Hence, thesesystems became an integral part of ouroverall DA system. A design generated onthese systems could use any CAD routinesuch as PG and DRC and designsgenerated using DPS or any other routinecould be edited on these systems.

Another method to create DFL is via anautomatic layout program. RCA hasdeveloped a family of these programsgenerically called automatic placement androuting (A PAR )7. APAR refers to theautomatic placement of predefined stan-dard cells into regular rows of cells that arethen automatically routed (inter-connected). The first generation of thissoftware was called placement routing andfolding (PR F), while the second was place-ment and routing in 2 -dimensions (PR2D).The third generation called multi -port 2 -dimensional ( M P2D) now is being used.The MP2D program has been highlysuccessful in automatically laying out wellover one -hundred chips. In fact, over thelast ten years RCA's APAR programs havegenerated over 1000 custom-LSI devices.

Typically, a layout can be performed inweeks (from logic diagrams to PG tape). Ifthe logic is simulated by our MIMIC logicsimulation program, its connectivitydescription can be automatically translatedto MP2D format. Automated layout ishighly useful for making prototype chips(to quickly develop a custom IC for inser-tion into a system breadboard) and low -volume custom designs. It trades -off in-creased chip size to gain shorter design timeand lower front-end cost.

After creating the computerizedartwork, the next step is to verify it. Thiscan be done in a variety of ways. The mostbasic is to generate a checkplot of all thefeatures for visual inspection. Softwareexists to communicate to a variety ofpenplotters, to graphic terminals or tohigh-speed electrostatic plotters. Figure 7shows one such system, our 72 -inch -wideVersatec' electrostatic checkplotter.

More powerful than the visual inspec-tion provided by a checkplot is the CRITIC(Computer Recognition of IllegalTechnology in Integrated Circuits) design -rule checking program' alreadymentioned. The designer may describe the

Fig. 6. Usi-g the Applicon interactive graphics system, the operator can easily and quicklymake numerous changes to the IC artwork.

geometrical rules of his technology in anEnglish -like language to CRITIC. Thedesigner usually does this once for a newtechnology and this description, containedin a user -named "CRITIC control file," issimply invoked when CRITIC is executed.An example of such a file is shown in Fig. 8.User -named CRITIC control file holds thegeometrical rules of the designer'stechnology. CRITIC generates a listingthat, for each violation, describes: whattopological condition (for example, dis-joint, contain, inside, overlap, abuts) ortolerance (width, notch, clearance orenclosure tolerance value) was violated; a

PLOTS listing of the offending featuresand what definition they came from; and aDFL "error" file containing these

offending features and tolerance "ticmarks" for generating an error-checkplot.

The artwork -to -connectivity extractionprogram (ARTCON)6 extracts logical con-nectivity directly from the physical artworkfor a subset of design styles. These includeones using predefined standard cells orother more general artwork buildingblocks. This program is used for all RCA'sgate -universal -array (GUA) designs(including metal -gate, silicon -on -sapphire(SOS) and closed -cell logic (C2L)

Fig. 7. This electrostatic checkplotter can create a six -foot -square checkplotof a complex ICin less than 10 minutes.

Rosenberg: The evolution of design automation toward LVSI

technologies) to automatically extract theconnectivity for a variety of logicsimulators. The circuit is again simulatedto verify functionality and look for possiblelogic hazards. The truth -table output isthen automatically translated by theAFTER (Automatic Functional Test En-coding Routine) program to a variety ofautomatic tester languages to provide afunctional test program. This is highlyuseful, especially for quick turnarounddesigns such as GUA and APAR.

Another important function of theartwork system is automated modificationof the artwork. The SMART (SelectiveModification of Artwork Regions andTopologies) programs, based on the Bairdalgorithms% provides many essentialabilities. On a primitive level, it can do theArtwork Boolean Operators (AND, OR,NOT), oversizing and undersizing offeatures, and translation.

SMART can dimensionally "bias"(undersize) features to compensate forvariations that occur during the mask -making and semiconductor processingoperations.

It automatically can notch down thechannel region of polysilicon gates,without narrowing the interconnect por-tion, to increase performance of critical

can generate newmask levels from existing mask levelsunder a number of conditions and do otherautomatic modification tasks.

At the working end, the MAP (MaskArtwork Program) translates the generalpolygonal shapes described in the DFLlanguage into a format that drives a mask -making machine such as a D.W. Mann orElectromask pattern generator (to make a5 -or- I OX reticle), a Gerber photoplotter (tomake an 80X foil) or a manufacturing

electron -beam exposure system (MEBES)(to make a fully step -and -repeated mask).The step -and -repeat array (SANDRA)program generates the required chip -location information, including dropoutsand test inserts, and also labeling informa-tion.

Over the years we have found theDEFOR MAT program to be highly useful.This decompiler-like program translatesthe data contained on a mask -makingcontrol tape back into DFL. This permitsus to generate a shaded electrostatic check -plot of this data before the mask is made(for designer sign -off). This invaluableverification procedure tends to detect grosserrors and otherwise obvious ones (im-properly generated borders, improperlypositioned or chosen library elements,missing alignment keys, an opaque "hole,"and so on) before expensive masks aremade.

The MASK system is another valuablefacility at RCA. This software greatlysimplifies the task of specifying MEBES oroptical masters. It interactively requests allthe information required to make a master.It gets chip information such as step -and -repeat distance and chip corners togenerate borders automatically and it re-quests wafer size, chip dropout locations(or a standard code) and test -insertpatterns to create the chip array. Sincemuch of this information is common to atechnology, we may specify it in a datasetcalled the Technology File which may beinvoked for future circuit types of the sametechnology family.

After assimilating all this information,and performing syntax and semanticschecks, MASK generates an "exec" file torun the following programs automaticallyand independently. First MAP translates a

CRITIC CONTROL LANGUAGE

N+ IS LEVEL 4 WIDTH

METAL IS LEVEL 6 WIDTH 5

CONTACTS ARE LEVEL 13 WIDTH 2 AREA 9XYZ IS LEVEL 28 WIDTH 5 NOTCH 3

METAL CLEARS XYZ BY 2

METAL CLEARS METAL BY 5 IGNORE BUTT

CONTACTS INSIDE METAL BY 1

N+ OVERLAPS XYZ BY 2 ALLOW BUTT

N+DEV IS DEFINED N+ INSIDE PWELL

P+DEV IS DEFINED P+ NOT INSIDE PWELL

ABC IS DEFINED XYZ OVERLAPS IMPLANT

POLYCONTACT IS DEFINED CONTACT INSIDE POLY

Fig. 8. A typical user -named CRITIC control tile.

DFL file to a PG tape. Then SANDRA isrun to make the step -and -repeat array.Then DEFOR MAT converts the PG tapeback to DFL. Finally, the checkplotsoftware is run, which produces magneticcontrol tapes to generate the electrostaticcheck p lots.

We have found this type of system to beextremely valuable for automating stan-dard procedures because it reduces effort,time and, most importantly, the chance ofprocedural errors.

A similar system to MASK isAUTOROM. It automatically generates aPG control tape and an automated testertape from an input file consisting of the"Is" and "Os" desired for a custom mask-

programmable read-only memory (ROM).All permanent data required fora specifiedROM type, (for example, step -and -repeatdistance) is stored in a permanent file, andso we need not respecify it to generate anew custom variant of that type. In addi-tion, AUTOROM does over a dozenobvious validity checks on the customersupplied bit -pattern -and -option file beforegenerating the PG and tester tapes.AUTOROM automatically invokes over ahalf -dozen CAD programs.

Simulation

We also have sophisticated circuit andlogic simulation software tools. These toolsverify the performance of an IC beforemanufacture.

Our recently developed MIMIC logicsimulator12 is state-of-the-art. We can use itin either interactive or batch mode. It is afour -level simulator ( I, 0, X, Z). It permitsa hierarchical building-block specification.It uses the CA DL language developed forthe CA DDB system but not the data baseitself. It has built-in models for primitiveelements such as NANDs, NORs, ANDs,ORs, and a variety of flip-flops (bothclocked and not). It properly modelsbilateral transmission gates including anarbitrary network of these. It supportsinertial delay models for all gates: separaterise -and -fall delays may be automaticallyderived from tables of delay vs. eitherfanout or capacitive loading. A flexiblehazard -detection facility exists. A largevariety of interactive facilities are sup-ported: different time intervals may besimulated, breakpoints may be inserted,desired outputs may be respecified, NETstates may be displayed or reset. Thenetwork may start in the unknown ( X) oran initialized state. The designer mayrequest detailed timing information (show -


ing all the intermediate activity in responseto an input change) or just stable -stateresults (the final state resulting from a newinput state).

Our TESTGEN Logic simulator9 cansimulate up to 512 "faulty" networks inparallel and can help determine the "stuck -at" fault coverage of a set of test vectors.Another significant capability allows thedesigner to automatically translate fromMIMIC input description format toAPAR format (and the other way). This isnot only fast and convenient, buteliminates translation errors. To furtheraid this process, a library of MIMIC sub-networks is being developed to functional-ly model each of the standard cells inA PAR's library. Furthermore, MIMICoutput format is directly compatible withthe AFTER program which allowsautomatic translation of test vectors(network inputs and simulated outputs) toautomatic tester format. This greatlysimplifies functional test generation.

Our R -CAP circuit simulationprogram is similar to well-knownprograms such as SPICE in its capabilities.It employs a highly efficient direct -currentalgorithm, has standard transient responseand small -signal -alternating -currentcapabilities and has sensitivity to passivecomponents and has noise -modelingcapabilities.

The program's short -channel MOStransistor model is accurate to him and isbeing extended further. It employs anextended Ebers-Moll bipolar -transistormodel and also, optionally, a Gummel-Poon model which truly models basecharge (unlike many other implemen-tations). The user may choose aneconomical background batch mode or ahighly interactive foreground mode. Wecan plot all state variables, such as node -or -branch voltages, component current in-cluding device -pin current and componentpower. Significantly, R -CAP has a

correlated -component capability whichallows the designer to specify anyparameter (such as a resistance,capacitance or any model parameter suchas threshold voltage or beta) in terms of ageneral algebraic expression. This supportsdesign for manufacturability, (that is,

meeting electrical specifications in the faceof processing variations).

We have developed the verysophisticated, cost-effective and easy -to -use TDAS (Test Data Analysis System)".The system's basic primitive abilities -histograms, wafer maps, trend diagramsand so on - may be custom -assembled fora specific application. This system is used

on a daily basis to support six differentprocessing lines at three different RCAmanufacturing locations. Process, typeand design engineers automatically get thereports.

Under active development is a generalparameter correlation capability. This willprovide graphical tools such as scatterdiagrams, and analytic tools such as regres-sion analysis. This will further aid the goalof design for manufacturability.

The challenges of VLSIMajor questions before us are: What arethe compelling challenges to DA as wemove toward VLSI? Where must we ex-pend most of our future efforts to enableVLSI to become a reality? I see vastchallenges ahead, especially in layout,design verification and testing. I can envi-sion solutions to these problems just asmany of my co-workers in this field can.

As I think back to my early days in DA, Ihave this strong feeling of deja vu. In theearly 1970s, we clearly saw some of theproblems of complexity and outlinedelegant and achievable solutions. But manyof the more elegant and far-reachingsolutions never took hold in our designcommunities. However, whenever weadded a new (but incremental) capabilitythat solved a real problem, and that cleanlyfit into the existing structure, it was

accepted. Our DA system evolved to whereit is today through the addition of in-cremental capabilities. Therefore, as I tryto project the evolution of DA to serve theneeds of VLSI, my optimism is for growthmodes that I have seen work first-handalready.

Without a doubt, I believe the majorproblems to be solved on the way to VLSIare in layout, testing and design verifica-tion, in that order. Moore" predicted thatthe design problem - product definition,design and layout -will be the rate -

limiting process constraining VLSI use.First, he thinks that this cost ("front -end -cost") is growing exponentially with time(and thereby tracking complexity growth)such that the front-end cost -per -function isremaining roughly constant. Second, hethinks that as we move toward the systemlevel of complexity on a chip, productuniqueness increases, thereby decreasingpotential volume. This increases the front-end cost of a function per unit IC.Meanwhile, technology advances are

decreasing dramatically the per -unit -

manufacturing -cost of each function.Clearly, front-end cost will soon dominatethe total cost of a VLSI IC.

Physical design

Clearly, design and layout techniques thatdramatically improve productivity in thefront-end areas are a major challenge toDA developers. I do not believe this is animpossible problem. In fact, I am confidentthat we are evolving, slowly, to a solutionof the productivity and cost -per -functionissues.

The fundamental reason why front-endcost per function is not declining is becausewe are still designing mostly at or near thedevice or gate level. I believe that the way toreduce front-end cost in IC design is todesign and layout VLSI chips using higher -level functional building blocks that maybe of SSI, MSI or even LSI complexity.For each product group, these blocks willinclude universal functions (such as

clocked flip-flops, shift registers, ALU,RAMS, ROMs, encoders, decoders, ex-pandable PLAs, comparators, A/ Ds,Di As) and specialized proprietaryapplication -oriented (yet often reusable)elements.

In addition, we must develop higherlevel, more productive techniques, such assymbolic layout15, to create these

functional blocks. Furthermore, these

blocks must be assembled within a struc-tured, hierarchical design environment toallow design verification to remain trac-table.

However, is this "apple-pie" techniqueachievable both technically and by thecrucial criterion of designer acceptance?

1 am particularly encouraged in thepracticality of this approach by our largesuccess in using the APAR techniques(already described) in our semiconductorcommercial product areas. As indicated, ithas been highly successful in the systemsarea for over 15 years. At this time, theacceptance of this technique for a subset ofcommercial designs is growing rapidly,precisely because of the necessity to reducefront-end cost and design time for system -type components for which hand -packedlayout techniques are uneconomical.

No automatic -layout approach willresult in minimal area. For standard cellapproaches, I believe the major cause of thearea penalty is the use of fixed -heightstandard cells and their algorithmic place-ment. Fixed -height cells are rarely optimalin size - simple cells tend to be too narrowand complex ones too wide. Also, rigidpinout requirements tend to reduce celldensity. And algorithmic placement is

never optimal because computers lackglobal perspective - local optimums areusually found. This leads to larger -than -

Rosenberg: The evolution of design automation toward VLSI 39

required routing surfaces and affectsoverall chip size and sometimes even per-formance (long interconnects with toomany tunnels add excess series resistanceand capacitance to ground). Fortunately,CMOS technology is quite tolerant of theseproblems.

I believe the advantages of APAR can beextended to dense VLSI while minimizingits limitations by adopting a semiautomatictechnique which cleverly elicits designerguidance. We are developing one suchapproach called FLOSS (Finished LayOutStarting from Sketch)'. This approachallows us to use arbitrary -sized cells thatcan be SSI, MSI or LSI in complexity. Thekey insight of FLOSS is that it uses theglobal perspective of the human to get arough, initial layout (the sketch withinwhich the designer optimizes placementand wireability) and then uses the com-puter to do the tedious compaction. Therough layout is equivalent to the chip planrequired before handcrafted layout begins.

This process can be optimized by allow-ing extensive but rapid iterations. Theloose initial sketch is modified by insightsgained from subsequent compaction.Another benefit of this approach is that thedesigner can do future modifications(which occur more often than we wouldlike to admit) on the loosely packed sketch,not on the densely packed, final layout. Weplan to further optimize the iteration partof this approach by developing a dis-tributive computer system tying togetheran interactive graphics system with a fastprocessor.

The logic and layout designers can vastlyimprove productivity by using this buildingblock technique to design at a much higherlevel of complexity. The challenge is todevelop a set of "macrocells" that havereasonably high complexity (which is thesource of productivity gain), but that arenot too functionally unique (which wouldrequire designing a large library ofmacrocells, and each, of course, must beaccomplished at the device level). Otherchallenges are to develop a design style thatflexibly addresses aspect ratio, pinout-location and power -bussing issues.

A highly promising technique for thedesign of macrocells - but not VLSIchips - is symbolic layout such as a

STICKS approach's The challenge here isthat the "compiling" of a STICKS diagraminto silicon -mask features is highlytechnology -dependent. As technologyevolves, we may have difficulty enhancingthe compiler for optimal density. Ofcourse, design -rule parameterization maybe hugely advantageous in the face of rapid

process evolution. One hope is that most ofthe parametrized designs will be readilyscalable to tighter design rules - this, ofcourse, assumes that design rules will onlychange quantitatively not qualitatively,that is, topologically. Or, if there are a fewqualitative changes, we must be able toreadily modify the software compiler.

The FLOSS approach is advantageousbecause it is not vulnerable to the aboverisks but can readily capitalize on whateverbenefits symbolic layout can offer. When itis judicious, a macrocell can be designed atthe device level.

Design verification

Other crucial issues are both logic andcircuit verification and the crucial issue ofphysical design verification. As described,we and other companies have excellentcircuit and logic simulation tools. OurMIMIC logic simulator is hierarchical innature. We can thereby develop a library oflogical models for the predefined physicalbuilding blocks (macrocells) described inthe previous section. This lets the logicdesigner achieve the same type ofproductivity leverage as the layoutdesigner, that is, working with high-levelprimitives.

This approach, however, will be in-efficient as complexity increases. Althoughit will be simple for the designer to specifyand analyze rather complex systems bydesigning them in a top -down, hierarchicalstructure, the simulator itself must performa complete macro -expansion of the system,as it simulates on the gate level.

Clearly, a general, transparent high-level, macromodel ability must bedeveloped to improve simulatorefficiency - this is crucial for fast,economical interaction with the designer.This will be relatively straightforward forsimple functional blocks such as ROMs,RA Ms, PLAs, counters and shift registers.However, many subtle problems do existwith, for example, detailed timing ac-curacy, hazard detection and intelligent(minimal) propagation of the unknown( X) logic state. It will be even morechallenging for more general functionalblocks such as A LUs and decoders.

On the positive side, it is obvious that wecan incrementally solve this problem, byadding additional functional models(macromodels), one at a time, focusing onthose that most heavily affect simulatorcost.

In general, to simulate VLSI circuits, orsubsystems, we will need even higher levels

of analysis, such as register transfer level( RTL) and behavioral -level simulation.Although these types of simulators exist, Ibelieve the challenge will be to structure ahierarchical simulation capability in-volving multilevels of simulation that com-municate efficiently with one another. Thiswill permit system -level simulation toverify lower -level block design as top -downdesign proceeds. Impressive work" hasoccurred in this area, but I believe theefficiency challenge remains to be solved.

There are many challenges in physicaldesign verification. Many of these can bemet if we develop structured design tech-niques. These techniques extensively usehierarchical layout implementation -nested building blocks with clearly defineddesign rules governing their proximity andinterconnection. Clear definition is crucialif currently available design rule and con-nectivity verification techniques are to beextended to VLSI. I believe this challengefacing physical design verification willrequire strong coordination between CADtool developers and the design community.

Testability

Another huge challenge to the successfuluse of VLSI is the ability to test the deviceswe design. This is already a significantproblem for many designs of LSI complex-ity. A number of techniques for design fortestability (DFT) have been proposed in-cluding scan techniques'', on -board testcircuitry including use of signatureanalysis, behavioral -level testdevelopment'9 and designs using highvisibility of all internal sequential logic toeither probeable pins or the bus structures.In addition, I believe CAD testability aidssuch as controllability/ observabilitymeasures20 will help the designer who isincorporating DFT.

There is the obvious trade-off, however,between testability and unit cost. Thewhole industry has traditionallyemphasized silicon real estate above DFTfor unit -cost reasons. Our studies haveshown that DFT, using currently un-derstood techniques, can be quiteexpensive - more so than theirproponents acknowledge. In addition, con-ventional testability measures, such as"stuck -at" fault -coverage monitors (usedby all known parallel and concurrent faultsimulation programs) do not address theissue of pattern -sensitive faults. Nor do thescan techniques test for them. These maybecome more significant as design rulesshrink and inter -electrode couplings


become more significant. This may also becrucial in the reliability area where migra-tion of metal interconnections, after stresstesting, may accentuate pattern -sensitivity(or lead to failure). As this will be afunction of process evolution, built-inDFT techniques may be essential for evenmature VLSI devices.

I believe the development of cost-effective design -for -testability approachesand their supporting DA tools remain alarge challenge.

AcknowledgmentsI wish to thank Henry Baird, Larry Frenchand Hank Miller who thoughtfullyreviewed an early version of this paperthereby contributing valuable insights andencouragement. I would also like to thankmy staff, Rich Auerbach, Chris Davis, andHans Schnitzler for their many and signifi-cant contributions to our DA efforts overthe years. I am grateful to Larry Frenchwho guided the direction and developmentof DA for many years. I am totallyindebted to my many co-workers at RCAwho created the capabilities discussed inthis paper.

ReferencesI. Mead, C. and Conway, L. Introduction to VLSI

Systems. Addison-Wesley, pp. 137-143 (1980).

2. Korenjak, B.J., "PLOTS: A User -orientedLanguage for CAD Artwork," RCA Engineer. Vol.20, No. 4. p. 20 (Dec., 1973).

3. Ressler, D.G., "Simple Computer -aided ArtworkSystem That Works," II th Design AutomationWorkshop, Proceedings. Denver. Col. (June,1974).

4. (a) Rosenberg, L. and Benbassat, C.. "CRITIC:An Integrated Circuit Design Rule CheckingProgram." I 1th Design Automation Workshop.Proceedings. pp. 14-18. Denver. Col. (June. 1974).

(b) Auerbach. R.A. and Deutsch, S.. are responsi-ble for the significantly enhanced current version ofCRITIC.

5. Korenjak, A.J. and Teger, A.H., "An IntegratedCAD Data Base System," 12th Design AutomationWorkshop, Proceedings, Boston, Mass. (June.1975).

6. Baird, H.S. and Cho, Y.E.. "An Artwork DesignVerification System," 12th Design AutomationWorkshop, Proceedings. pp. 414-420, Boston.Mass. (June, 1975).

7. Feller. A. and Noto. R.. "A Speed -oriented. Fully -automatic Layout Program for Random LogicVLSI Devices," National Computer Conference.Proceedings. pp. 303-311 (1978).

8. Baird. H., "Fast Algorithms for LSI ArtworkAnalysis," 14th Design Automation Conference,Proceedings. pp. 303-311. New Orleans. La. (June,1977).

9. Hellman, 11.1. "TESTGEN: An Interactive TestGeneration and Logic Simulation Program." RCAEngineer. Vol. 21, No. I (June/July. 1975).

10. (a) Davis, C.B., Miller. J.C. and Rosenberg. L. M.,"Digital Simulation as a Design Tool,- RCAEngineer, Vol. 17, No. 4, pp. 34-39 (Dec., 1971).

(b) Davis, C.B. and Payne. MI_ "R -CAP: AnIntegrated Circuit Simulator," RCA Engineer. Vol.21. No. 1 (June/July, 1975).

11. Bergman, R., Aguilera, M. and Skorup, G.E.,"MOS Array Design: Universal Array. APAR orCustom." Ibid.

12. Ashkina/y. A. and Hellman. HI, are responsiblefor developing the MIMIC simulation program.

13. Gianfagna, M.. "A Unified Approach to Test DataAnalysis," 15th Design Automation Conference.Proceedings, Las Vega, Nev. (June, 1978).

14. Moore, G.. "VLSI: Some FundamentalChallenges." IEEE Spectrum, pp. 30-37 (April,1979).

15. (a) Williams, J.D.,"STICKS -A Graphical Com-piler for High -Level LSI Design," National Com-puter Conference, pp. 289-295 (1978).

(b) Hsueh, M.. "Symbolic Layout and Compac-tion of Integrated Circuits." MemorandumNumber UCB/ ERL M79/80, Electronics ResearchLab. University of California, Berkeley (Dec..1979).

16. Cho, Y.E., Korenjak, A. and Stockton, D.E.,"FLOSS: An Approach to Automated Layout forHigh -Volume Designs," 14th Design AutomationConference. Proceedings. pp. 138-141, NewOrleans, La. (June. 1977).

17. Hill, D. and vanClemmpat. W., "SABLE: A Toolfor Generating Structured, Multi -levelSimulations," 16th Design Automation Con-ference, Proceedings. pp. 272-279, San Diego.Calif. (June. 1979).

18. (a) Eichelberger, E.B. and Williams, T.W., "ALogic Design Structure for LSI Testability," 14thDesign Automation Conference. Proceedings, pp.462-468 (June, 1977).

(b) Funatsu, S.. Wakatsuki. N. and Yamada. A..

"DESIGN". "Designing Digital Circuits With Easi-ly Testable Consideration," 1978 SemiconductorTest Conference. pp. 98-102.

(c) Mulder, C., Niessen, C. and Wijnhoven.R.M.G., "Layout and Test Design of SynchronousLSI Circuits," 1979 International Solid -State Cir-cuits, pp. 248-249.

19. Johnson. W.A.. "Behavioral -Level Test Develop-ment." 16th Design Automation Conference.Proceedings, pp. 171-179. San Diego, Calif. (June.1979).

20. Goldstein. L.H., "Controllability ObservabilityAnalysis of Digital Circuits." IEEE Trans. Circ.and Sys.. Vol. CAS -25, No. 9, pp. 685-693 (Sept..1979).

-

Larry Rosenberg is Manager of the DesignAutomation Department of the Solid StateTechnology Center (SSTC). He joined RCALaboratories' SSTC in 1970 in the DesignAutomation Department as a Member of theTechnical Staff, and was involved with theR -CAP Circuit Simulation Program, bipolartransistor modeling and the CRITIC DesignRule Checking Program. In 1976, he becameEngineering Leader of the Artwork SystemsGroup and in 1978 he was appointed to hiscurrent position.Contact him at:Solic State Technology CenterRCA LaboratoriesSomerville. N.J.TACK ET: 325-6316

Rosenberg: The evolution of design automation toward VLSI 41

A.E. Heath R.P. Lydick

A system for the automated designof complex integrated circuits

The automated layout of an LSI circuit is only part of thestory - circuit simulation programs at RCA give thecustomer assurance that the circuit meets expectation 3.

Abstract: The authors describe the designflow leading to successful, rapid auto-mated circuit layout using automatedplacement and routing (A PAR) and,moreover, they cover computer simulationprograms and the assortment of checkingand conversion programs needed to assurecorrect circuit performance - beforefabrication .

Introduction

Amazing advances have occurred in thefield of semiconductors during the lastfifteen years. Things that were complex in1965 are almost mundane today. Thedifficult tasks of that year arecommonplace - the impossible hasbecome ordinary. Circuits that werebeyond the comprehension of most peoplein 1965 are being manufactured in largenumbers today.

The most complex circuit types availableat that time included single bit storageelements, monostable multivibrators, andquad, two -input gates. One need only lookaround one's own home or office to seeexamples of today's complex circuits. Thequartz wristwatch, pocket calculator, elec-tronic automotive controls, advancedpacemakers, electronic toys and personalcomputers would all have been impossiblewithout the development of Large ScaleIntegrated (LSI) and Very Large ScaleIntegrated (VLSI) circuits.

The development of, and demand for,these circuits has created a new problem.The complexity of the circuits requiresteams of skilled individuals working over

Reprint RE -26-2-7

Final manuscript received July 28. 1980

extended periods of time to produce thefirst working circuit. One recently designedmicroprocessor required a team of fromtwo to sixteen people working together forthree years before the design wassuccessfully completed. This span of time isclearly not responsive to the needs ofcustomers who are trying to impact themarketplace.

One solution to this problem is the use ofthe Automated Placement And Routing(APAR) of standardized circuitry to formstructures tailored to the requirements of acustomer. When a circuit is designed withAPAR techniques the time required for thesimulation, design, fabrication and test of anew circuit can be as short as seventeenweeks. This time will, of course, vary withthe complexity of the particular task.

The basic APAR approach utilizes acomputer program to place standardizedcells of circuitry and the associated inter-connections on a relative surface. The useof standardized cells eliminates the need todesign new circuitry and allows the perfor-mance of the finished circuit to be moreaccurately predicted. Once the cells havebeen placed on the surface, the samecomputer program can calculate the inter-connections required for those cells. Thecomputer, by means of its excellentbookkeeping ability, can operate with anerror rate that is orders of magnitude betterthan even the most experienced circuitdesigners'. This virtue vastly increases theprobability that a new circuit will becompleted correctly and in a timelymanner.

The automated layout of an LSI or VLSIcircuit is only part of the story. To be trulysuccessful, the customer must be assuredthat the finished circuit will meet hisexpectations before he commits large sums

of money to the layout and fabrication ofthat circuit. This assurance is providedthrough the use of the circuit simulationprograms available at RCA. Detailedanalog simulations of circuit cells accurate-ly predict the performance of those cellsbefore they are manufactured. This infor-mation can then be utilized with a digitalsimulation of the entire circuit to providethe customer with an accurate prediction ofhow well his circuit will (or will not)perform. If the simulation reveals designdeficiencies, they can be corrected prior tothe manufacture of any circuits. Thisfeature alone can save six months to a yearin the development of a new circuit type.

Simulation of the overall circuit servesan additional function - the results of thesimulation can provide the truth tablesnecessary for the testing of completedcircuits.

To make these design tools truly useful,it is absolutely necessary that manualintervention be minimized. Every time aperson has to retype or reformat data, thepossibility for error is present. For thisreason software programs have beendeveloped to provide the interface amongeach of the design tools. Once a simulationhas been successfully completed utilizingstandardized cells and data, that data basecan be converted to the format required bythe APAR programs. This same conver-sion program can be utilized to convert theoutput of the APAR program to theformat required by the circuit simulationsoftware, and thereby to provide a checkon the accuracy of the APAR program.Another conversion program is capable ofreformatting the output of the APARprogram into a form that is compatiblewith various means of displaying the com-pleted design. The displayed data can be in

42 RCA Engineer 26-1 July/Aug. 198C

C A

ateBO

POLYSILI CON

METAL

SILICON

Fig. 1. Two input NAND gate.

the form of video signals at a graphicsdisplay or hard copy on any one of severalstyles of plotters. Finally, the data can beconverted into the format required by thephotomask generation equipment.

Standardized cell libraries-the first step

Virtually all modern integrated circuitdesigns make use of a cellular approach tocircuit layout. Groups of transistors aredesigned as units that can be placed on asurface. Interconnections are then definedamong the various groups. The design andredesign of these groups for every newcircuit can provide extremely dense results,but the probability of error is ever presentand the design cycle is often lengthy.

A much more practical approach makesuse of a library of standardized cells ofcircuitry. The libraries for bulk CMOS andCMOS/ SOS technologies provide the cir-cuit designer with the wide range offunctions (NAND, NOR, Exclusive -OR,storage elements, etc.) required to com-plete his assigned design task. Because newcells are the exception, rather than the rule,they can be added to the appropriatelibrary without placing an undue strain onthe scarcest resource in the integratedcircuit industry - manpower.

In order to be compatible with theAPAR software, each of the cells has beendesigned on a coherent grid. In addition, allof the cells in a particular library are of aconsistent height and have accessibility toeach input and output on both the top andbottom of the cell. Figures I and 2 areillustrations of the topology for a two -input NAND gate and a D -type Flip -Flop,respectively.

Fig. 2. D -type flip-flop.

Simulation-a necessityfor success

All circuit designers are familiar with thefeeling of depression that occurs if theircircuit does not work when it is finallybuilt. In the case of a circuit built on aprinted circuit board, the problems canoften be corrected with some jumpers and afew days of effort. Integrated circuits,because of the inaccessibility of signals,may require weeks of effort just to locate aproblem. Corrections must be made at thephotomask level, and a new run of wafersfabricated. Often, secondary problems arethen discovered, requiring one more itera-tion of the design. Complete debugging of acomplex design can consume six months ofengineering time.

The solution to this problem is computersimulation of the circuit before it is

fabricated. Analog simulation of criticalportions of the proposed circuit can revealseveral types of design deficiencies orprovide characterization data prior tofabrication. RCA's circuit analysisprogram (R -CAP) is used to perform thesefunctions for the individual cells and largergroups of circuitry.

R -CAP does have some finite limitsbeyond which detailed simulation is nolonger practical. Complex integrated cir-cuits would be extremely expensive tosimulate with a component -basedsimulator, because of the vast amounts ofcomputer memory and the large number ofcomputations required to perform thistask. Complex circuits can be simulatedwith a new logic simulator developed at theSolid State Technology Center (SSTC) inSomerville, New Jersey. The MIMICprogram utilizes logical descriptions of the

functions of each of the standardized cells,along with the propagation delaycharacteristics predicted by R -CAP (ormeasured on previously fabricated devices)to model circuits with complexities up to3000 equivalent gates.

When a circuit is simulated usingMIMIC and the standard descriptions ofcharacterized logic elements, the probabili-ty of success, from a logic design viewpoint, is limited only by the thoroughnessof the truth table utilized for that simula-tion. A secondary advantage of completesimulation is the generation of a logicalpattern that can be utilized to test thefinished circuit.

APAR-the key totopological successThe simulation routines, when exercisedfully, ensure that the logic used in a newdesign is correct but they do nothing toenhance the topological layout of thatdesign. The computer program that canensure the success of a new layout is theMulti -Ported, Two -Dimensional (MP2D)program developed at the AdvancedTechnology Laboratories in Camden, NewJersey.

MP2D utilizes physical descriptions ofstandardized circuit cells and nodal con-nection lists to design the finished circuit.The program places the cells with respect toone another in a manner that minimizes theinterconnect requirements among the cells.It then determines the paths that must bedefined to interconnect the circuitry. Final-ly, it compresses the interconnections andthe placement of the cells to minimize thecircuit size consistent with the appropriatedesign rules. MP2D, when properly used,

Heath/Lydick: A system for the automated design of complex integrated circuits 43

CREATEMIMIC

INPUT FILES VERIFY

MIMIC

SIMULATION

YES

NO

NO

CONVERTTO

APARCELLS

ANNOTATEFOR

MAIIC

REVISENO INPUT

°I FILE 8SCHEMATIC

CADLM

TEST PATTERNF LE

DEVELOPWMIC

INFO

DEVELOPPDFINFO

MERGE WITHSTD. IP/PDF

AND NEWPDF IN FO

-

DESIGNDESIGN

NEWOUT-

LINES

NEWCELLS

\B)

Fig. 3. Design flow chart.

can generate circuit designs withreasonable densities in less than onemonth, rather than in the one -to -two yearsrequired for custom circuits.

Conversion programs-the "glue" that holdsthe system togetherLogic simulation and automated layout areeach valuable tools, but they cannot betruly effective if they operate with in-dependently generated inputs. One of theconversion programs developed at SSTCutilizes the MIMIC logical descriptionsand nodal net list to generate an M P2D-compatible description of the circuit. Inthis way, human intervention (with theassociated probability of error) is almostcompletely eliminated, and the circuitdesigner is assured that the circuit beingdesigned is identical to the one that wassimulated. This same program can be usedto convert an M P2D design into a MIMICdata base and allow a simulation of thecompleted design, thereby adding onemore level of confidence.

Once the MP2D design is complete,another conversion program provides theinterface between MP2D and the variousmeans of displaying the design. These

ARTSIFT WITH

OUTLINES)

OUTLINECHECKPLOT

means include, but are not limited to, theApplicon graphics system, pen plotter,Versatec electrostatic plotter andTektronics video display. Once the descrip-tion is formatted in the Design FileLanguage (DFL), the design can proceed inthe same manner as any other integratedcircuit. The remaining steps include check-ing (the human eye is still a highly valuabletool in integrated circuit design), maskfabrication, wafer fabrication, testing andpackaging.

A recently developed conversionprogram (PROBE) can provide advanceddata relating to the placement of probingpads on the circuit. The PROBE programdecodes the position of each of the inputand output cells on a design and generatesall of the information necessary tofabricate a probe card that can be used totest the finished wafer.

The design flow-an overview

Now let's follow the flow of a typical jobthrough the design procedure. The pathinvolving no new cell designs will be

considered. Reference to the Design FlowChart (Fig. 3) will be helpful.

The first task is to annotate the logic

drawing with APAR cell type membersand MIMIC part names. Cell typenumbers correspond in general, to singlelogic functions such as inverters and two -input NOR gates, although some cells maycontain multiple logic functions andshould be so indicated. Part names may benumeric, alphabetic or alphanumeric, butmust be unique to each part (cell) in thelogic. Cell pin numbers should also beindicated on the drawing to facilitate laterchecking.

When the logic diagram has been com-pletely annotated, the MIMIC input filemay be created. A printout of the fileshould then be obtained and checked backagainst the logic drawing to ensure ac-curacy. The design engineer then in-teractively exercises the logic using theMIMIC program until satisfactory resultsare obtained. All changes incurred duringthe above interactive exercise must benoted on the logic drawing. The resultingMIMIC files then become the basis fordeveloping an APAR input file and a testpattern file for later testing of the chip.

The next step in the design procedure isto create an APAR input file. Invoking theCADLM program with the MIMIC inputnet file and an APAR standard Pin DataFile (PDF) as inputs will result in thecreation of a file containing all the elements

44 RCA Engineer 26-1 July/Aug. 1980

ARTSIFT W

CELLS)CRITIC

CRITIC )

ART(SIFT WITH

CELLS)

NO APPLICONMOD

i

FINALCHECK PLOT

& APPROVALS

( MASK

(MEBES TAPC\a DATA }

unique to the subject task, namely anMP2D element -to -pattern assignmenttable and net list. For the typical job, theabove file is then merged into a filecontaining standardized run data ( M P2D5program switches, PDF data, etc.). After afew simple edits to enter the chip name,number of cell rows and number of pads oneach side of the chip, the file is ready forMP2D.

To ensure that the input file is acceptable

to the APAR program, a foregroundsyntax checking program, MP2D5T (est)should first be run. This procedure willvery often uncover syntax errors and willgreatly enhance the feasibility of obtaininga successful first run throughM P2D5B(atch). A background job may beentered for MP2D5B, once MP2D5T hasbeen successfully run.

The output of M P2D5B is a Design FileLanguage (DFL) file containing all theinterconnect metal and tunnels as well asreference calls to cells and tunnel -ends.With the aid of the ART program, this fileis combined with a file containing outlinesof all cells. The resulting file may be plottedeither in black -and -white shading on aVersatec plotter on in color on a penplotter. This check -plot should be verycarefully checked back to the logicdiagram. Modifications to the DFL designfile are accomplished through use of theApplicon interactive design system.Modifications should of course, be check -plotted and checked until correct.

If no modifications are required, orwhen the required modifications will nolonger affect pad locations, the DFL designfile is run through the PROBE program.The output of the PROBE program is a listof pad -center coordinate points and anedge sensor location suitable for obtaininga probe card for wafer probe testing.

Once a satisfactory check -plot has beenobtained, the design file is then exercisedby the design rule checking program,CRITIC. Design rule violations indicatedby CRITIC are located and corrected byuse of the Applicon. When CRITIC hasindicated that the design file is free ofdesign rule errors, a final check -plot isobtained, reviewed and approved.

The design file, now ready for masking,is combined with the APAR cells usingART. It is then entered into the MASKprogram which outputs a magnetic tapecontaining the design file in ETEClanguage and input command data for theMEBES mask plotter. Thus, havingstarted with an unverified logic diagram,we find ourselves some four -to -six weekslater ready to obtain masks for a

simulation -verified integrated circuit thathas excellent possibility of first -shotsuccess.

The final step of the design flow nowremains-the generation of a test se-

quence. In order to ensure that the truthtable utilized in the test sequence cor-responds to the desired implementation ofthe logic, the MIMIC simulation resultsare reformatted through the use of theAFTER program. This method eliminatesthe need for debugging the truth table whenfinished wafers are first tested, but it alsorequires that the circuit designers do athorough simulation of the logic. Thus, theMIMIC simulator will help to ensure thatthe logic is correct and will provide asequence that can be used to test thefinished circuit.

Summary

A design system has been described thatprovides a logic designer with an assurancethat his design is correct. The system canthen be used to convert the simulation database into an integrated circuit design, withmaximum probability of success on thefirst iteration. This system is fullyoperational and is being used at the SSTCin Somerville, New Jersey.

Fred Heath joined RCA in 1953 at Government Systems, Camdenwhere he was involved with printed wiring design and fabricationfor 18 years. In 1971 he transferred to SSTC. He is principallyinvolved in the design of large-scale integrated circuits forAdvanced Applications using APAR and Custom Techniques. He isalso responsible for the design and maintainance of the standardAPAR cell files.Contact him at:Solid State Technology CenterSomerville, N.J.TACNET: 325-6389

Richard Lydick started with RCA in 1965 at Aerospace SystemsDivision in Burlington, where he worked on the system and detaileddesign of military electronics and was responsible for the design ofPMOS arrays. After an absence of seven years, he joined SSTC in1979 where he has been involved in the design and application ofLSI circuits using APAR and Custom Techniques.Contact him at:Solid State Technology CenterSomerville, N.J.TACNET: 325-6906 Authors Fred Heath (left) and Richard Lydick (right).

Heath/Lydick: A system for the automated iesign of complex integrated circuits 45

B.S. Wagner

A multi -technology checking programfor large-scale integrated circuitsbased on standard cells*

In some cases an experienced, senior -level engineer musttake approximately seven hours to do the LSI checking that the topologyand connectivity checking (TACC) program can do in 15 minutes.

Abstract: Designers who use the multi-port two-dimensional ( MP2D) computer -aided design program for large-scale in-tegrated( LS/) circuits need an inexpensivewar to check the correctness of thesedesigns. The checking program describedin this paper is inexpensive, handles manytechnologies and is east' to use.

Background

Since its introduction in 1972, the multi-port two-dimensional (MP2D) computerprogram has been distributed to ap-proximately 30 companies. A fullyautomatic placement and routing programbased upon the standard cell technique,MP2D quickly and inexpensively helps thedesigner to make LSI arrays for variousapplications. Many users of custom LSIarrays need MP2D because artwork,masks and initial design are major equip-ment development costs.

Reprint RE -26-2-8Final manuscript received June 25. 1980.

This program received major support from theU.S. Army Electronics Research and DevelopmentCommand, Adelphi, Maryland, under contractDAAB07-76-C-1398. The work on this programwas performed under the technical direction of Mr.Randy Reitmeyer, at the Electronics Technologyand Devices Laboratory, Ft. Monmouth, NewJersey.

The standard cell technique for produc-ing very large scale integrated (VLSI)arrays depends on a library of customcircuits or standard cells. Each of thesestandard cells has a unique identificationor pattern number. An engineer im-plements a logic design by specifying thestandard cells he needs and the way inwhich the cells will interconnect.

The designer must give the MP2Dprogram specifications for the standardcells to be used, the way in which the cellswill interconnect and a box -outlinerepresentation library of standard cells.The MP2D program automatically placesand interconnects these standard cells.

MP2D generates a completely finishedarray design, but sometimes the designermust manually edit it. Typically, manualediting is done when unusual power dis-tribution requirements exist in certainareas of the chip. Although the designerusually edits on an interactive graphicssystem that has some very powerful com-mands for rapidly manipulating graphicalelements, the manually -directed editingoften corrupts areas or layers of the array.

Even if the output of the M P2D programis not modified, an error could exist ineither the connectivity or topology of theoutput because designers naturally tend toselect designs that tax the abilities of theprogram. Thus, chip designs must be

checked before being released for fabrica-tion. Customarily, engineers havescrutinized magnified (100X), multi -color"check plots" - approximately 20 incheson a side - of the MP2D-generated chipdesigns. This is a slow, error -prone, ex-pensive and difficult method for checkingchip designs. Over the last few years, boththe device densities of chips and the sizes ofthe chips have increased. Consequently,manual checking has become more ex-pensive and undetected errors have becomemore probable.

Automatic checking of MP2D-implemented arrays began in 1975, when aprogram was written to check chip designsimplemented by a predecessor to theMP2D program. This predecessorprogram was called two-dimensionalplacement and routing (PR2D) and thechecking program was called automaticplacement and routing artwork integritysurvey (A PRA IS). Tony Scialdone, whoworked for the Palm Beach Division ofRCA, wrote APRAIS. The program wassuccessful both at the Palm Beach, Floridaand Camden, New Jersey locations ofRCA.

When the new MP2D program wasintroduced in 1972, the APRAIS programcould not be used to check the new M P2D-implemented chip designs. The APRAISprogram needed major changes. In 1977,an upgraded APRAIS program became


the topology and connectivity checking(TACC) program.

TACC program functions

The TACC program can:

Check the topology and connectivity ofM P2D-implemented chip designs;

Check chips designed using any one offour different standard -cell families;

Provide diagnostic messages and a

minimum of false -error messages;

Provide graphic representation of errorconditions on an Applicon interactivegraphics system; and

Require a few user -inputs for programexecution.

Basic assumptions of the program

MP2D-implemented chip designs use a setof previously designed custom circuits orstandard cells. The basis of TACC is thatthese standard cells, while being designed,are carefully checked. Any errors are cor-rected before the standard cells are put intothe library. Therefore, the TACC programchecks for topology and connectivityerrors up to and including the input-outputpins of these standard cells.

Topology and connectivitychecking

The TACC program checks for: short-circuited signals; open -circuited signals;unconnected pins; and spacing violations.One input to the TACC program specifiesall of the signals on the chip and theirdestinations. As data about each signal isread in, the program assigns a sequentialnumber to the signal and prints out boththe signal and its sequential number. Anytime the program detects (from a com-parison with the artwork tape) that, in fact,two supposedly distinct electrical signalsare connected inadvertently, it prints anerror message containing the sequentialnumbers of the two signals that are short-circuited. Similarly, whenever the programdetects an electrical open circuit in anysignal, it prints an error message con-taining the sequential number of the signal.If the signal is electrically open in morethan one location, the program prints anerror message for each location.

The program also checks to ensure thatall of the pins connected to the varioussignals are actually connected. If theprogram finds that a pin is not connected,

then it prints an error message giving the Xand Y coordinates of the pin and the signalthat the pin should be connected to.

The program checks for various edge -to -edge spacing violations. On these chips,connections are made via conducting pathsthat exist on either a metallization level, apolysilicon level or a combination of theselevels. The program checks for minimummetal -to -metal spacing, and minimumpolysilicon-to-polysilicon spacing. Itchecks, not only between the various pathsthat interconnect the pins, but also betweenthe paths and the standard cells. When theprogram finds a spacing violation, it writesan error message that states the level wherethe violation occurred, the types of com-ponents involved in the violation, and thelocations of the two components involvedin the violation.

Multi -technology flexibility

The program can check chip designs in anyof the following four cell families: 4.2 -milsilicon -gate silicon -on -sapphire (SOS);6.3 -mil radiation -hardened silicon -gateSOS; 11.4 -mil closed -cell logic (CI) and12.6 -mil CI. The TACC program holdslists of internal control parameters. Theselists correspond to the cell technologiesthat the program can accommodate. Oncethe relevant technology is specified, theprogram can find the proper parameter listto be used. While the program currentlyhandles only these four technologies, ex-pansion of the program to othertechnologies is readily accomplished.

Diagnostic and other messages

The program prints three classes ofmessages.

The first class of messages is infor-mational. These messages either repeatsome of the required or optional inputinformation or denote that the programwill use a default parameter. Thesemessages give a comprehensive set ofinformation in one printout for documen-tation purposes. Samples of these messagesare listed in Table I.

The second class of messages tells theuser when the input data is incorrect,incomplete or unrecognizable. Undermany of these circumstances, an attempt tocomplete the checking of the design wouldbe wasteful. These messages prevent suchan action. Samples of these messages aregiven in Table II.

The third class of messages consists ofthe actual diagnostic messages. The first

Table I. Sample informationalmessages generatedby TACC

1. "The Process Technology Key Is X"

. This is the process technology keythat was specified on one of theinput parameter cards.

2. "The Specified Metal -To -MetalSpacing (In Centimils) = XX"

. This is the metal -to -metal spacing(edge -to -edge) that was specifiedon one of the input parameter cards.

3. "The Default Metal -To -Metal Spac-ing Will Be Used"

. No metal -to -metal spacing wasspecified on the input parametercards and the following spacing willbe used by the program:SOS = 0.25 mil (edge -to -edge)C2L = 0.30 mil (edge -to -edge)

4. "The Specified Poly -To -Poly Spac-ing (In Centimils) = XX"

. This is the poly -to -poly spacing(edge -to -edge) that was specifiedon one of the input parameter cards.

5. "The Default Poly -To -Poly SpacingWill Be Used"

. No poly -to -poly spacing wasspecified on the input parametercards and the following spacing willbe used by the program:

SOS = 0.30 mil (edge -to -edge)CzL = 0.20 mil (edge -to -edge)

possible group of diagnostic messages tooccur are the connectivity -error messages.Topology checking is performed after con-nectivity checking, therefore spacing errormessages are the last possible messages tobe printed. Some possible diagnosticmessages are shown in Table III.

One of the greater challenges in writingartwork checking programs is to eliminatefalse error messages. A potential user willtolerate only a very small number of falsealarms before he stops using the program.This program has given false alarms veryinfrequently , and the program has beenchanged as these messages have appeared.

Graphic epresentation oferror conditions

For each topology or connectivity errorthat occurs a graphic representation of the

Wagner: A multi -technology checking program for large-scale integrated circuits based on standard cells 47

Table II. Sample TACC messages caused by Incorrect, incomplete or unrecognizable input data.

1. "Illegal Process Technology Key"

An illegal process technology key was specified onthe input parameter card.

2. "Unrecognizable NOT055 Record: XXX...XXX"

XXX...XXX is the 80 character record (on the artworkinstruction input tape) which the program does notrecognize. The record is skipped and processingcontinues. This error generally indicates that theuser made a mistake in manual modification of thechip.

3. "Illegal Diagonal Line Set Pair. See NOT055 RecordWith Subject Sequence Number NNNNN."

The TACC program has found a non -orthogonal lineset pair. The TACC program can handle onlyorthogonal line sets.

4. "XXXX Pattern Undefined In Pin Data File"

Information on this particular pattern number ismissing from the pin data file.

error is also generated. This is donethrough the generation of a magnetic tapein the design file language (DFL) format.The magnetic tape information then isconverted into a format compatible with anApplicon interactive graphics system, andloaded onto the graphics system. Then theuser may view and correct the errors on thegraphics system.

When the graphic representations of theerrors are generated, they are placed intoone of several possible display levels,depending on the class of error. Thisgrouping of errors into various display

also facilitates the analysis of theprogram's output.

User inputs to the program

Inputs to the TACC program can bedivided into two classes - required and

optional. The inputs to the program are:

I. A pin data file. This file describes theexternal characteristics of each circuitor cell in the standard cell library - pinlocations, cell width, etc.

2. A node list. This list describes thedestinations of the signals.

3. An element -to -pattern assignment list.This list identifies, by a unique elementnumber, each occurrence of a pattern inthe design.

4. The output tape from the MP2Dprogram. This tape eventually is used togenerate the artwork masks for the chip.

5. Various control cards.

Input items 2 and 3 (node list andelement -to -pattern assignment list) areoptional outputs from the MP2Dprogram. Input item 1 (pin data file) is arequired input to the MP2D program. A

node list and an element -to -pattern assign-ment list also are part of the MP2Dprogram's required input. But, these twolists are not identical with input items 2 and3 for the TACC program because MP2D,in the course of its execution, may makemodifications to the two lists. For exam-ple, MP2D may interchange logicallyequivalent pins on a cell. In order to checkcorrectly, TACC must use only updatedlists from the MP2D program.

Examples of program output

The TACC program is written in the IBMSystem / 360 Basic Assembly Language.Versions of the program currently exist ona Univac Series 70/55, an IBM 370/ 158and an IBM 360/65 computer. On theUnivac computer, the executable coderequires approximately 210,000 bytes of

Table III. Sample diagnostic messages generated by TACC.

1. "Nodes MMM And NNN Are Shorted"

The node numbers show the relative positions of thenodes in the input node list.

Exception: Ground and VDD show as GND and VDD .

2. "Node NNN Is Open"

Not all of the pins in the node are tied together.

3. "Pin at SXXX.XX, SYYY.YY in Node NNN Is Un-connected"

. The pin is not touched by a metal or tunnel polygon.

4. "Spacing Violation Between (A) MMMMMMMM And(B) NNNNNNNN On Level X"

The two rectangles (A) and (B) are too close. Therectangle coordinates are given in two followingmessages. "MMMMMMMM" and "NNNNNNNN"identify the types of rectangles involved as follows:

UNUSED PIN, PIN, CELL OUTLINE,TUNNEL END, SHAPE SET, POLY RECTANGLE

or METAL RECTANGLE

. Level X defines the mask level involved.

5. "The LLLLLLL Rectangle's Diagonal Is: SXXX.XX,SYY.YY-SXXX.XX,SYYY.YY"

The message always appears in conjunction with,and immediately following, another message.LLLLLLL identifies the type of rectangle in question.The coordinates identify the corner of the rectangleclosest to the chip origin and the corner furthestfrom the origin.

6. "Pin At SXXX.XX, SYYY.YY In Node MMM is ShortedTo Pin At SXXX.XX, SYYY.YY In Node NNN"

Two pins are located too closely together, probablydue to misplacement of a component (pattern, cell).


memory. The amount of memory requiredto run the program varies according to thecomplexity and density of the chip. Todate, all of the chips run through theprogram have required less than 500,000bytes of memory.

Representative program execution timesare given below for the Univac Series 70/ 55computer. The 70/ 55 is a relatively slowcomputer having a register -to -memoryfixed-point add -time of 2.5 microseconds.In Table IV, the column labeled Number ofartwork records denotes the number ofrecords on the output tape from the MP2D

program. It indicates the density and com-plexity of the chip.

If a cost for computer time on a 70/55computer is estimated at $200 an hourthen, from the preceding table, the cost ofrunning the TACC program on a chip A is$50. An experienced, senior -level engineermust take approximately seven hours toperform the identical amount of checking.Compared with the present cost ofengineering labor, the cost of the TACCprogram is significantly low.

The execution time in the table is actualelapsed time from the initiation to the

Fig. 1. Checkplot of chip containing topology and connectivity errors.

termination of program execution. Actualprocessing time (as opposed to I/O time)constitutes most of the running time.

Figure I is a checkplot of a chip that wasrun through the TACC program. This chipuses the SOS cell family and was producedby the MP2D program. The checkplotcontains one connectivity error and twotopology errors.

Figure 2 shows the printout that wasgenerated by the TACC program. The firstgroup of lines indicates the parameters thatwere specified to the program, and thesecond group of lines represents the actual

Wagner: A multi -technology checking program for large-scale integrated circuits based on standard ceils 49

TALCD1T,,,I6OGy AN, CJY,IECTIVITy LAcCR

DATE: 0s/16/78

THE r.lEEss TEC HOLAGY KEY IS 5

THE S"EEIFIED IETAL TU AETAL CENT1110). 25THE s,EcIFtin Rao To RAT sPhLIN6 ( to cE01,.(Ls). 30THE sPEciFtEc CELL HEIGHT( III OECIIILSI. 042THE LJWEST HUMBER EJR Em -CELL RUN CELLS IS 8101

NOCE 132 is (IRE I.

SPAEI 5 VI7LATIIN 8EidEE.4 (4) METAL 0.W/0:OLEI4E .A" RECTAHGLL.S UIAGUIAL IS: 0/4.92,THE "8" RECTAAGLE.S OIAGOAAL IS: 010,08,

PAC! V191.ATIIA BLI.,EEN (A) lETAL RECTAqGLEIff "A" REMIT:L(1S JIAuL4AL IS: 015.52.

.8" REC)4`:GLE1S tiAGLAAL IS: 01,,.0e,

END C SURVEY FAR: APAR REMbAS5 TEL132 CHIP

Fig. 2. Program printout.

101 CELL DUILI4E GA LEVEL 6042.62 --> 015.08. 043.18042.43 --> 025.92. 040.17

181 (ELL OA LEVEL o .u42.02 --> 011,u0. 043.18J42.03 --> Q4c../7

Er-

INTE HORE EA MER SELECTED 0.4 0, 0 1 .0 1 . orr 0 .0CP(I LEVELS 4 FEF LEVELS NONE

B

A

ROUTING I

O

CELL

ROUTING 2

MODE I4Z3 E.LAIBER SELECTED. 0r)KIDO1 01. OFF 0 .0EDIT LEVELS 5 , FEE LEvEL.s NODE

Fig. 4. Topology errors. The width of space A is less than the minimmetal -to -metal spacing.

error messages. In this example, node 132was open -circuited. The program detectedthis error and generated a picture on theApplicon of all of the segments of node 132(Fig. 3).

In this chip design, two segments ofrouting on mask level 6 are too close to oneof the cells. The minimum metal -to -metalspacing was specified as 0.25 mil (25centimils). The program detected and

um allowable 0.25 mil

printed out these errors. Figure 4 shows thegraphic representation of these errors.

Program algorithm

Overall program organization

The TACC program has four majorprogram routines (Fig. 5):

Input parameter processing routine; Main topology and connectivity process-

ing routine; SOS connectivity determination routine;

and

C2L connectivity determination routine.

The input parameter processing routineis the program routine in which executionof the TACC program begins. In thisroutine, various required and optionalparameter cards are read in. Based uponthe parameter values read in, variouscontrol parameters are initialized for ul-timate use by the three other majorprogram routines. Following this in-itialization, control is passed along to themain topology and connectivity processingroutine.

The main functions of the main topologyand connectivity processing routine are:

Read in and process the various requiredcard decks.

Read in and process the artwork instruc-tion tape.

Determine the connectivity of the chipand report any errors.

Determine the topology of the chip andreport any spacing errors.

Control the execution of the SOS andC2L connectivity determination routines.The SOS connectivity determination

and C2L connectivity determinationroutines are similar in function butdifferent in detail. Their function is to assistthe main topology and connectivityprocessing routine in determining the elec-trical connectivity of the chip design. Theiralgorithms are based upon the separate setsof rules for establishing connectivity in theSOS and the C2L technologies.

The main topology and connectivityprocessing routine prints out all errormessages related to the actual chip design,and normal program termination occurswithin this module.

Detailed program description

Input Parameter Processing Routine -Execution of the TACC program begins inthis routine, which sets up internal controlparameters for the entire TACC program.The routine initially reads in a value (fromcards) for the process technology key and,based on this value, initializes variousinternal control parameters.

Some internal control parameters can bespecified by the user. The routine alsoprints out messages that denote theparameters that have been specified by the


INPUT PARAMETERPROCESSING

ROUTINE

SOS CONNECTIVITY MAIN TOPOLOGY C2L CONNECTIVITYDETERMINATION .111-11. AND CONNECTIVITY -0-0- DETERMINATION

ROUTINE PROCESSING ROUTINE ROUTINE

Fig. 5 Major program modules of the TACC programcontrol).

user and the specified values. Next, controlis passed to the main topology and con-nectivity processing routine.

Main Topology and ConnectivityProcessing Routine - This routine beginsby reading the remaining cards in the inputcard file: the pin data file cards, theelement -to -pattern assignment cards andthe net list cards. From the pin data filecards, the routine builds a pin data file listin memory, with one entry for each pindata file card. From the element -to -patternassignment cards, the program builds anelement -pattern list in memory, with oneentry for each assignment on the cards.From the net list cards, the program buildsa node list in memory, with one entry foreach pin in the net list.

Upon reading the end -of -file on the cardreader file, the program sorts the variouslists for later processing. It then reads thecomponent records (which specify in-stances of standard cells in the chip design)from the artwork instruction tape, andbuilds an entry in the core pattern list foreach record. Next, the program reads therest of the tape records and builds a recordin the core rectangle list for each rec-tangular shape, and for each orthogonalline. The rectangular shapes andorthogonal lines are used to specify theinterconnection paths between the stan-dard cells.

Upon reaching the end of the artworkinstruction tape, the program builds one ortwo rectangle list entries for each pin in thenode list. If the pin exists on both sides of acell, then the program builds two rectanglelist entries. Otherwise, it builds only onerectangle list entry. If two rectangle listentries are built, these two entries are called

Table IV. TACC program

(arrows indicate flow of program

"sister pins," and whatever processing isperformed on one of the sister pins mustalso be performed on the other sister pin.Each sister -pin pair is assigned a uniquenumber that is part of the rectangle listentry.

Since I/O pad pins are not defined(physically) as rigorously as pins in othercells, the preceding process is not perfectlyaccurate for I/O pad pins. Therefore,through the use of a table built into theprogram, an attempt is made to find thepattern's actual pin descriptions for anyI/O pad. If the pattern is not represented inthe table, then the program builds the pin'srectangle record in the same way used forother patterns. Note also that unused pins(since they do not appear in the node list)are not processed at this point. The rec-tangle list is now sorted on lower -left-handX-coordinate, lower -left-hand Y-coordi-nate, and upper -right-hand Y-coordinate.

At this point, the rectangle list is siftedthrough for intersecting rectangles. Even-tually, a group of disjoint trees evolves,each consisting of at least one rectangle. Asa matter fact, N rectangle trees are initiallyused, where N is the number of rectanglesin the rectangle list. Each of these trees isnumbered J, where J is the index (position)of the rectangle in the rectangle list. Therelationships between rectangle index andtree number are recorded in the tree list.Each time the program finds a pair ofintersecting rectangles, it picks their treenumbers out of the tree list. If the treenumbers are unequal, it searches the treelist for each occurrence of the higher treenumber of the two. Each such occurrence isreplaced with the lower tree number. At theend of rectangle intersection processing,

execution times.

Chip Number of Execution Computeridentification artwork records time (mi9.) charge ($)

A 6037 15 50

B 14435 64 204

the tree number of any given string (tree) ofrectangles will be the index of the rectanglethat appears closest to the front end of therectangle list.

An intersection of two rectangles is

considered significant if, on the actual chip,such an intersection would provide a paththat a signal could traverse. Not all rec-tangle intersections are important-itdepends on the technology involved.Whenever the main topology and con-nectivity processing routine finds a pair ofintersecting rectangles, it transfers controlto either the SOS connectivity determina-tion routine or the C2L connectivitydetermination routine. The SOS con-nectivity determination routine or the C2Lconnectivity determination routinedetermines the important intersections.

SOS Connectivity DeterminationRoutine - Table V lists some of the rec-tangle intersections that are significant forthe SOS technology and that are the basisof the algorithm for this routine. Each timethis routine receives control, it determineswhether the two intersecting rectanglesmatch any of the significant rectangleintersections listed in Table V. If theintersection is found to be significant, thenthe tree list is updated. Pin -to -pin in-tersections are errors and cause an errormessage. Any time a pin rectangle is part ofa significant intersection, the routine flagsboth that pin rectangle record and its sisterpin rectangle record (if one exists) asconnected.

C2L Connectivity DeterminationRoutine - Table VI lists some of the rec-tangle intersections that are significant forthe C2L technology and that are the basis ofthe algorithm for this routine. Each timethis routine receives control, it determineswhether the two intersecting rectanglesmatch any of the significant rectangleintersections listed in Table VI. If theintersection is determined to be significant,then the tree list is updated. Pin -to -pinintersections are errors and cause an errormessage. Any time a pin rectangle is part ofa significant intersection, the routine flagsboth that pin rectangle record and its sisterpin rectangle record (if one exists) asconnected.

Main Topology and ConnectivityDetermination Routine - After theroutine checks all possible rectangle in-tersections, it attempts to assign one ormore node numbers to each tree. Thecomputer looks at each rectangle record ina tree and picks node numbers out of thosethat are pin rectangles. The results of thisprocess appear in the tree -node list. If nopin rectangle is found in a given tree, then

Wagner A multi -technology checking program for large-scale integrated circuits based on standard cells 51

Table V. Sample significant rectangle intersections for SOS.

No. Type of intersection

1 Poly routing with pin on a cell2 Poly part of tunnel end with pin on a cell3 Pin on a cell with pin on a cell4 Pin on an I/O pad with pin on a cell5 Metal routing with metal routing6 Metal part of tunnel end with metal routing7 Pin on an I/O pad with metal routing

Table VI. Sample significant rectangle intersections for C2L.

No. Type of intersection

1 Metal routing with pin on a cell or I/O pad2 Metal part of tunnel end with pin on a cell or I/O pad3 Pin on a cell or I/O pad with pin on a cell or I/O pad4 Metal routing with metal routing5 Metal part of tunnel end with metal routing

the program builds an entry in the tree -node list with the tree number and a nodenumber of 0. If more than one nodenumber is found for a tree, then theprogram builds multiple tree -node list en-tries for that tree.

Next, the program sorts the tree -nodelist by tree number, then node number. Itcompresses the list to get rid of anyredundant entries. It finds short-circuitednodes by identifying adjacent tree -node listentries whose tree numbers are equal andwhose node numbers are different. Theprogram puts all rectangles in the shortednodes on level I of the DFL output tape.

After re -sorting the tree -node list onnode number, the routine looks at adjacententries again, reporting those whose nodenumbers are equal but whose tree numbersare different as open nodes. It puts theserectangles on level 4 of the DFL outputtape.

The connectivity processing portion ofthe routine is now done. In preparation forthe topology processing '(spacing check)portion of the routine, both the tree list andthe tree -node list are used to propagatenode numbers through trees by markingthe rectangle list records. Then the rec-tangle list is written to a work file.

The topology processing begins with therectangle records being read in from thework file and new rectangle list recordsbeing generated from them. Each new

rectangle list record is slightly larger (halfof the appropriate spacing parameterminus 1/ 100 mil) than the original rec-tangle list record. In this way, the routinecan tell if spacing rules have been violatedby looking for intersections of rectangleswhose node numbers are different. Itchecks only polysilicon-to-polysilicon andmetal -to -metal intersections.

For each entry in the pattern list (i.e., foreach cell on the chip), two things happen.First, for each unused pin in a cell (checkedagainst the node list), the programproduces a polysilicon-level rectangle(SOS) or a metal -level rectangle (C2L).Second, it generates outline rectangles onboth the polysilicon and metal levels for thebody of the cell. Special handling is againrequired in generating outlines of I/Opads. This is accomplished by using a tablebuilt into the program.

Finally, the rectangle list is again sorted(on lower -left-hand X, lower -left-hand Y,and upper -right-hand Y, and the programmakes a pass through it, looking atpolysilicon-polysilicon and metal -metal in-tersections. If it finds an intersection andthe node numbers of the two rectangles aredifferent, then the computer prints a spac-ing violation message, and puts the tworectangles on level 5 of the DFL outputtape. The program terminates by printingthe contents of an optional title card fromthe input card file.

Conclusions

The TACC program has been verysuccessful since its inclusion into RCA'sgroup of design automation programs.TACC has reduced the costs of checking achip by reducing the number of personswho manually check the design, and byenabling less -experienced persons to checka design.

Acknowledgment

The author wishes to express his thanks toMr. Albert Feller and Mr. RandyReitmeyer for their assistance with thispaper.

References

I. Feller, A. "Automatic Layout of Low -Cost. Quick -Turnaround. Random -Logic Custom LSI Devices."13th Design Automation Conference. Proceedings.San Francisco. California (19761.

2. "Computer -Aided Design for Complex Circuits."RCA ERADCOM contract DAAB117-76-C-1398.Final Report (Feb. 1979).

Barry Wagner is a Senior Member of theTechnical Staff in the Digital SystemsLaboratory of the Advanced TechnologyLaboratories. Mr. Wagner has been withRCA since 1967. Since 1974, he has workedmainly in the area of computer -aided designwhere he has been responsible for thedevelopment and maintenance of logicsimulation programs, artwork checkingprograms, database systems, and an in-teractive graphics system. Before 1974, hewas involved in the development of supportsoftware and applications programs forvarious minicomputers.Contact him at:Advanced Technology LaboratoriesGovernment Systems DivisionCamden, N.J.TACNET: 222-3803


R.H. Bergman T.R. Mayhew

LSI testing methods and equipment

Design automation has dramatically shortened designdevelopment time, so now the focus mist be on effectivelyand rapidly testing the complex LSIs with innovative methodsand equipment.

Abstract: The authors examine methodsand equipment needed to test complex LSIdevices, and delve into the functional testvectors portion of the electrical testspecification, the design -for -testabilityissue, the SSTC test facility's effort tomaintain compatibility with its customersand a review of SSTC's test equipmentacquisition plans.

Introduction

The Solid State Technology Center givesthe major operating units of RCA theopportunity to develop and incorporatecustom digital LSI devices into theirequipments for certain competitive ad-vantages - size, weight, power, cost andreliability. The systems -activity designertypically specifies and designs the LSIdevice and generates the test specificationfor the device.

The electrical test specification consistsof two basic parts. The first part, theelectrical test limits, includes power -supplyvoltage, load conditions, input/outputsignal swing, delay and repetition -ratetests. The second part is the functionaltruth table (test vectors) to be applied to theinputs of device for testing and theequivalent expected output -response truthtable. This article addresses the truth -tablepart of the electrical test specification -the functional test vectors, and how com-patibility with the SSTC test facility can bemaintained in an environment of rapidlyincreasing test complexity.

Test program generationThe LSI-array designer is responsible forgenerating a test program so that his

fabricated devices can be tested. Obvious-ly, he wants to define a test program thatcompletely tests every function and deviceon the array. When semiconductor deviceswere simple (a few gates or flip-flops) thistask was trivial and did not materiallyaffect schedule, array design, cost and soon. But as device complexity increases(logic arrays of 300 - 2000 gates andmemory arrays of 1000 - 64,000 bits arecurrently being designed or used), theefforts required to design test programsincrease dramatically. Also, the length ofthe resultant test vector sequence hasgrown. Some devices require 100,000 to 1 -million test vectors. The far-reaching con-sequences of such developments are thatschedule and cost goals for array develop-ment may be missed because of generationcomplexity, possible difficulties in install-ing the complex test program on existingSSTC test equipment, or prohibitively longdevice testing time at wafer probe and finaltest.

For example, the chart below shows thetrade-off between device test time andthroughput of the tester for a range ofdevice test times.

Test time vs. volume.

Test Time Device Devices' Month' Shift

2 sec. 77,500

20 sec. 7,750

5 min. 516

1 hr. 43

Assumptions: 10% probe yield0.25 time -factor for yield70% F.T. yield

If the test time exceeds 10-20 seconds there

Reprint RE -28-2-9Final manuscript received Aug. 28. 1980.

will be a major impact on testerthroughput.

RCA's fine complement of designautomation (DA) tools has dramaticallyreduced complex array development time.This time -reduction means that the test-vector-seq uence design efforts, if ap-proached improperly, can be the limitingstep in a custom design cycle. Let us look atthe test sequence generation procedure insome more detail.

Classification -combinatorial or sequentialCombinatorial logic has no internalstorage elements (flip-flops, shift registers,counters, or more complex internal logicloops) and the state of the logic is complete-ly and uniquely defined by the state of itsinputs. Look -ahead adder -logic, decodersand multiplexers are good examples. Com-binatorial logic is simple to test. A com-plete test of the logic can be done with (2")test vectors, where N is the number of logicinputs to the array. This test is completeand may be used to verify that the logic isexactly as specified on the logic diagram,but it contains many tests that are notrequired for production-LSI testing ofverified parts.

As a minimum, the test pattern shouldinclude functional verification of eachnode of the logic, including tests for all gateinputs and outputs stuck at "I" (SA1) andstuck at "0" (SAO). For example, to test athree input AND gate we must test for theoutput stuck at "0" (SAO), the output SA1,and the inputs SAO and SA1. To test for theoutput SAO requires, in this case, all inputsin the "I" state. This test also detects anyinput SAO. To test for the output SA I , wecan use one of many tests where at least one


c)

B) 5

4

INPUTS

3 2 1

OUTPUTS

5 6 7 GATE INPUTS TEST VECTOR

1 0 0 0 0 0 0 0 A 11 SAO 142 0 0 0 0 0 0 A 01 SA1 103 0 0 0 0 0 A 10 SA1 34 0 0 0

B 00 SA1 105

6

0

0

0

0

0 0

0

0

0

0

0B 01 SAO 14

7

8

0

0

0 0 0

0

B 10 SAO a

C 11 SAO 14

0 0 0 0 0 0C 01 SA1 10

10 0 0 0 0 0 C 10 SA1 8

11 0 0 0 0

12 0 0

13 0 0 0 Fig. 1. The simple logic structure is shown14 0 (above), together with a 16 -states truth table15 0 0 (bottom left) as well as tests for SA1 and SAO16 faults (bottom right).

input is in the "0" state. A test for inputsSA 1 requires that the tested input be in the"0" state, and all other inputs be in the "I"state. In this case, then, three tests arerequired to detect inputs SAl and outputSA1: 011, 101, 110, and the state 111completes the stuck -at test sequence.Therefore we need to use N+ I inputs totest an N -input gate. Observability is anadditional requirement. For each of thetests described, we must have a way tomonitor the output state of the device. Ifthe gate is buried inside a complex logicnetwork, paths must be sensitized so thatthe gate's response can be monitored at theoutput pins of the device.

Consider the simple logic structureshown in Fig. I. The circuit has four inputs,three logic gates and two outputs. Thefigure shows a complete exercising of allcombinations of inputs ( I 6 -states truthtable) as well as the set of four states thattests all gates for SA I and SAO faults, withall tests observable at the outputs (testvectors 3, 8, 10, 14).

Software programs can automaticallygenerate test programs for combinatoriallogic. TESTGEN can examine logic todetermine percent of SAl and SAOcoverage in a supplied test program.

Sequential logic contains storageelements internal to the array (flip-flops,

counters, shift registers) and the exact stateof the logic depends on the current state ofthe inputs to the array, and on the pasthistory of those inputs (the number oftimes a clock line has been activated, and soon). In theory, we can exhaustively test asequential logic device by applying 2 N+ mtest vectors, where N equals the number ofinputs and M equals the number of internalstorage states. Obviously, for arrayscurrently being developed with, for exam-ple, 30 inputs and 70 internal storage states,2 "I" = 230.70 1032, and the number oftest vectors becomes prohibitively large.

We need a way to generate an adequatebut minimum set of test vectors. Thiscompromise involves a complex set oftrade-offs. In the past, designers haveapproached this problem from one ofseveral ways. First, they have used simplefunctional verification. The concept is onewhereby the designer, being intimatelyfamiliar with his design and the intendeduse in the system, generates a sequence ofinput patterns that puts the logic throughits intended paces and generates outputsrequired for systems -use. These testpatterns may come from logic simulationthat is done to verify that the logic has beenproperly designed. Such patterns may usetester memory space inefficiently and theyoften do not check for undesirable modes

of operation or possible logic failuremechanisms.

A more rigorous method of generatingtest patterns is to configure them from afault -coverage point of view. As mentionedpreviously, we can use TESTGEN to ana-lyze test programs for coverage of nodaltesting. Once a test program with adequatecoverage has been generated, minimizationtechniques may be used to reduce thenumber of test vectors to fit into practicaltest equipment requirements and keepproduction -test costs low. One powerfulway to minimize test -pattern requirementsfor a given logic function is to designtestability features into the logic. Often, atthe expense of a pin or two plus a few gates,we can substantially reduce the test patternlength.

It is imperative that the designer con-sider test requirements early in the designphase. Test requirements may well affectthe partitioning of the logic and definitelyhave to be resolved before the logic isfirmed. Initialization must be considered.The logic should be able to be initializedwith a small set of test vectors. Schemes foraccomplishing this requirement includedesigning master resets for all counters andregisters, partitioning long counters intosections for test purposes and addingcontrol elements to break up large se-quential r. etworks during initialization.Also, it is sometimes possible to isolatesections of the logic so that the sections canbe tested simultaneously. This technique isspecially useful for highly sequential logicstructures.

The chart' shown in Fig. 2 puts intoperspective the economic implications ofthe investment in testability. This invest-ment includes development efforts andusually requires additional gates and pinsthat affect manufacturing costs. This totalinvestment is shown to increase linearlyand is the investment in testability. Thereward for this investment is a substantialreduction in initial testing cost followed bydecreasing gain. The total cost thereforehas a minimum and any further investmentin testability will not result inproportionate testing savings.

What is the future of design fortestability? Clearly, a larger investment willbe made in this area. Some micro-processor -based chip designs already in-clude a self -test capability' and this featurewill show up with increasing frequency.Another self -test technique calledsignature analysis' is appearing in some ofthe more complex logic devices. In thisapproach the addition of a test register andsmall amount of logic allows the chip to


sequence through a complex test sequenceusing a pseudo -random -like test sequence.At the conclusion of the test, results areautomatically compared with the correctresult for a 100 -percent functional device.

A third approach is the serial -scan tech-nique.4 Here, all master -slave registerelements, counters and shift registers areconnected in serial fashion via special testconnections on the array. Means areprovided for loading all of these elementsvia external data and clock inputs. Thisapproach requires from 5 -to -20 -percentadditional logic, and several pins. Thisserial -scan technique, however, reduces thetest pattern generation problem to the taskof serially loading and unloading theregister string and running combinatorialtests on the balance of the logic in-between.Therefore, all logic structures can bereduced to the equivalent of testing com-binatorial logic, a straightforward problemthat can be solved with computeralgorithms.

Which of these techniques is going tosucceed? Which will fade away with time?The answers are not clear. Perhaps all threetechniques will be used to some degree.What is clear, however, is that some formof design for testability is required forfuture LSI devices.

Interfacing with SSTCWith the testability problem being sointeractively related to the array design,how does a design activity interface withSSTC to provide an efficient transfer oftest requirements that will allow quickturnaround sampling of design verificationparts?

Logic simulation is the key to solvingthis problem. The MIMIC logic simulatorshould be used as a design tool to verifybasic logic function. For more informationon SSTC's new logic simulator, MIMIC,contact Aaron Ashkinazy or HenryHellman at SSTC in Somerville, NewJersey. SSTC will supply delay versus fan -out tables for logic cells used in bothuniversal array and automatic placementand routing (APAR) design approaches.These tables will allow the designer toanalyze and optimize his design from adelay and timing point of view. This effortwill lead to a verified logic design that willoperate over required environmentalranges and process variations and willprovide adequate margins.

The simulator effort will also provide aset of test vectors (inputs and expectedoutputs) in standard format (TESTGEN)that can be used to test the device.

I-N0

INVESTMENT IN TESTABILITYFig. 2. Eccnomic implications of investment in testability.

The design review-a critical step inarray design

An essential part of the design review priorto release to SSTC is the review of the testpackage for adequacy of test and forcompatibility with existing test facilities.

Where the application has been definedas a universal array, SSTC will digitize thelayout and extract the logic connectivity ofthe layout with software techniques. SSTCwill then resimulate the logic with MIMICto verify capture of the correct functionthrough the layout and digitizing cycle.Work is in progress to enhance thisprogram to include interconnect loadcapacity as a part of the simulation effortafter digitizing. This will allow layoutdependent delays to be included in thesimulation effort. For APAR designs, thelogic is not resimulated at SSTC since thereis no manual layout and digitizing cycle.Once proper operation has been verified,SSTC will generate the dedicated test tape(Datatron) from the standard simulationformat.

This method of interfacing has been usedfor over two years and, when followed, hasresulted in a smooth transfer of designinformation and a high probability of first-time success with design verificationsamples. During this period fifteen univer-sal array designs were handled with sevencustomers. In almost every case there wassome adjustment to the logic or layoutmade to improve performance marginswhen resimulated at SSTC. In many casesthe customer used a different logicsimulator and this caused some difficulty intranslating between simulators. Of thesefifteen designs, fourteen worked the firsttime into device fabrication, giving ex-cellent proof of the value of simulation inverifying the design and test program.

TOTAL COST

DEV, 3 MFG,COST

TESTING COST

Test equipment

The Solid State Technology Center's pre-sent test equipment consists of two mediumspeed (50 -kHz) systems, the Datatron 44and 4400 functional and parametric testersused for design verification and productiontesting of LSI arrays, a high-speed (10 -MHz) Datatron 45 functional tester usedfor device characterization, and a low -speed Keithley LPT-2 parametric testerused for wafer acceptance testing. Table Isummarizes the characteristics of thesetesters.

The medium speed Datatrons areparallel parametric and functional testersthat measure all input and output terminalparameters simultaneously while applyingthe functional test vectors. These testerscan either force a voltage and measure acurrent or force a current and measure avoltage. The terminals of the device undertest are sampled at the 80 -percent point ofthe data -bit period and the values arecompared with the programmed minimumand maximum acceptable limits. Out -of -limit values are detected as bit errors,which are indicated on a display panel orwhich can be data -logged. The current orvoltage value of any device terminal can bemonitored on the display panel. Duringproduction testing, devices are rejectedwhen the first error is detected.

The high-speed Datatron 45 is afunctional tester that can supply bursts offunctional test vectors, up to one kilobit inlength, at a 10 -MHz data rate. The outputscan be sampled at any point in the bitperiod with a 10 -nanosecond strobe width.The tester can measure rise and fall times,pulse widths and propagation delay.

The Keithley LP -2 is a sequentialparametric tester that measures the deviceterminals one at a time. It can applyvoltages up to 172 volts and currents up to

Bergman/Mayhew: LSI testing methods and equipment 55

Table I. SSTC test systems.

DATATRON 45 DATATRON 44 DATATRON 4400 KEITHLEY LPT-2

Tester type High speed Medium speed Medium speed Parametricfunctional functional and

parametricfunctional andparametric

Maximumrepetition rate 10 MHz 50 KHz 50 KHz 100 Hz

1/0 pins 96 pins 100 pins 50 pins 58 pins(includes 8 lowlevel pins)

Test stations 1 package I package test 1 package test 2 wafer probetest wafer probe 2 wafer probe

Maximum voltage 30 volts 30 volts 30 volts 172 volts

Slew rate I v/ns 20 v/kisec 20 v/µsec 2 v/µsec

Current measurementaccuracy ±1 nA ±200 nA ±1 pA

Voltage measurementaccuracy ±50 my ±50 my ±50 my ±1 uv

Rise and fall timemeasurement accuracy ±3 ns

Propagation delaymeasurement accuracy ±5 ns

Pulse widthmeasurement accuracy ±5 ns

100 ma. It has measurement accuracies of±1 pA and ±IµV.

The present SSTC test equipment forfunctional testing is limited to a maximumof 100 test terminals for the Datatron 44and 50 test terminals for the Datatron4400. Both systems are limited to a max-imum data rate of 50 KHz. The maximumfunctional truth -table length for this equip-ment is limited by the tester in incrementsof 16 pins. Table II shows this limitation.Longer test patterns can be generated byusing groups of truth tables with clockingand jumps between truth tables.

Test programs are generated on theDatatron equipment using the followingsteps.

I. Generate a Value Table that contains,line -by-line, all of the desired voltageforcing values (normally, inputs Vie, VILand power supplies Voo, Vss) for a

Table II. Truth table length.

Maximum No.of Pins

Maximum Length(masked with"don't cares")

16 10,000

32 5,000

48 3,333

64 2,500

80 2,000

96 1,666

100 1,428

logical "1" and "0" with correspondingacceptable maximum and minimumcurrent values ( /H max., 1H min., ILmax., IL min.) and all of the currentforcing values (normally outputs loH,10L) for a logical "I" and "0" with thecorresponding acceptable maximumand minimum voltage (VH max., VHmin., VL max., VL min.).

2. Generate a set of pin tables where eachtable assigns a value from the ValueTable to each pin.

3. Load a set of Truth Tables that assign alogical "I" or "0" or "don't care" to eachpin.

4. Assign leading edge and trailing edgetiming to desired pins.

5. Generate an instruction table that com-bines the above steps with desired clock-ing and jump routines, and binning oftest results to perform in sequence all ofthe tests desired.

A typical test program would performthe following tests:

Contact test; Terminal leakage test;

Functional test at nominal voltage; Functional test at maximum voltage with

input noise and output loads;

Functional test at minimum voltage withinput noise and output loads;

VDD or Vss leakage tests.

Future testequipment requirements

The high speed Datatron 45 can operate ata data rate of 10 MHz with a maximum of96 test terminals, but at the time of thiswriting, the high-speed tester shares peri-pheral equipment with the Datatron 44,and the two systems can be used only one ata time. Present plans call for the separationof the Datatron 44 and 45 in order toprovide a stand-alone 10 -MHz Datatron45 in the third quarter of 1980. Additional-ly, an off-line system used for the genera-tion of Datatron test programs and datareduction has been recently added to theSSTC test equipment.

The advent of newer, more complex LSIarrays with high input/ output pin countand higher operating speed requires theaquisition of newer and more advanced testequipment for SSTC.

High-speed testing is required not onlyfor testing devices at their specified max-imum test frequency but also to minimizethe total time required to test wafers andpackaged devices containing complexarrays with long test programs in a pilotproduction test environment.

The SSTC Test Technology Activityperforms a dual role. It operates in anengineering mode when providing testdebugging and design verification for newLSI arrays in development and, secondly,it operates in a production mode whenproviding testing for previously designed


arrays while they are in pilot production.Each year, the activity typically verifies thedesign of 60 new arrays and provides waferand packaged -device testing for more than50,000 commercial and H i-Rel screeneddevices consisting of over 200 array types.

Many of these devices provide RCAmajor operating business units with com-petitive advantages, new capabilities andnew markets. For example, SSTC-processed devices are used in the Van Nuysweather radars, GCS TENLEY/ SEELEYsecure communications systems and Sur-vival Avionics System, broadcast TVcameras, Meadowlands TAC TEC radios,MSR AEGIS and Sandia systems, ASDGVS-5 laser rangefinders, AED satellitecomputers, ATL ATM AC micro-processors, fault -tolerant computers, ad-vanced autonomous arrays and numerousother development programs, SSD micro-processors, memories and other customdevices and in many other applications.

The SSTC Test Technology operationparticipates in the following activities:

Wafer testing of bulk -silicon and SOSarrays and memory devices for SSTCengineering, RCA major operating unitsand other customers;

Wafer testing of bulk -silicon and SOScustom arrays and memory devices toobtain prototype quantities and establishthe producibility and yield levels ofproducts planned for production in theSolid State Division;

Final testing of commercial and H i-Relpackaged devices;

Supporting engineering in the designverification and array debugging;

Table III. Forecast of VLSI requirements.

Richard Bergman is a Manager in the SolidState Technology Center where he hasresponsibility for LSI Design, Applications,and Test. He has had more than 14 yearsexperience in the design and application ofMOS devices.

Contact him at.Solid State Technology CenterRCA LaboratcriesSomerville, N.J.TACNET: 325-6417

Tom Mayhew is Manager of Custom LSIApplications in the Solid State TechnologyCenter. He joined RCA in 1956 where heworked on circuit design for industrial andcomputer applications. Since 1964, he hasworked in the area of design, production,testing and applications of LSI.

Contact him atSolid State Technology CenterRCA LaboratoriesSomerville, N.J.TACNET: 325-6240

rummesi,Authors Torn Mayhew (left) and RichardBergman (right).

Characterizing and evaluating arrays todetermine design margin, sensitivities,process stability, and related testing re-quirements for SSTC and its customers;

Supporting reliability and qualityengineering by testing devices for processmonitoring, reliability verifications, anddevice qualification programs;

Providing input to Design Engineeringon matters pertaining to designingdevices for testability as they relate toexisting methods and equipment used fortest; and

Interacting with tester companies andother RCA organizations on test -relatedmatters and testing technology. The ef-

Year

1980 1982 1985

Maximum number of pins 84 120 250

Maximum frequency (MHz) 10 20 50

Maximum voltage 15 15 15

% Digital circuits 100 90 90

% Digital/analog circuits 0 10 10

A -D convenersNumber of bits 10 10-12 12 or 8Maximum sample rate (MB) 2 2 5 or 20

MemoryNumber of bits 4K 16K 64KOrganization IKx1 4K x 4 I6K x 4(Words x bits per word) 4K x 1 I6K x 1 8K x 8Access time (ns) 100 50 20

Cycle time (ns) 150 100 100

Design for testability Develop Essentialon chip

provision

Standardizedself test and

error correction

torts to keep pace with the changingtechnology should be incorporated intothe Technical Center operation in anorganized and timely manner.A forecast of device configurations and

complexity for very large scale integratedcircuits has been made based on inputsfrom SSTC and GSD personnel. Theseinclude requirements for Advanced -AEGIS, Banville, VHSIC, SEELEY,GVS-5, JPL, Sandia, AVS-WeatherRadar, Thornton, ManufacturingMethods programs with WPAFB, Fault -Tolerant Computer and others. Thefollowing test requirements (Table areanticipated for 1980 through 1985.

SSTC is presently considering theaquisition of a new high-speed high -pin -count tester in 1981. The leading contenderfor this equipment is the Fairchild SentrySeries 22 test system with 120 input/ outputpins and a 20 -MHz functional test datarate. This equipment will be softwarecompatible with test programs used on theSolid State Division Fairchild Sentry VII10 -MHz test equipment and will aid in thesmooth transfer of newly designed arraysinto production in SSD.

ReferencesI. Chung Ho Chen, "VLSI Design for Testability,"

1979 IEEE Test Conference. pp. 306-309.

2. Clary. J.B. and Cane, R.A.. "Self -Testing Com-puters." 1979 Computer. pp. 49-59.

3. West. D.G., "In Circuit Emulation and SignatureAnalysis: Vehicles for Testing Microprocessor -Based Products," 1979 IEEE Test Conference. pp.345-353.

4. Eichelberger, E.B. and Williams, T.W.. "A LogicDesign Structure for LSI Testability." Journal ofDesign Automation and Fault Tolerant Computing.Vol. 2. No. 2, pp. 165-178 (May 1978).

Bergman/Mayhew LSI testing methods and equipment 57

G. Skorup

The gate -universal-array for digital CMOS

Since the first application of the CMOS universal array wasbegun in 1973, seventy-two new gate -universal -arrays (GUA)have been implemented in commercial and military systems.

Abstract: The author reviews theapplications for and theory behind theCMOS gate -universal -array (GUA). Heshows that both commercial and militarylogic systems from a variety of RCAdivisions use the GUA; he shows thevarious approaches to a flexible designprocess allowed by the concept; and heshows how GUA advantages make this acost-effective, quick and efficient way tomake logic systems.

A gate -universal -array (GUA) consists of afixed placement of p devices, n devices andtunnels in a repetitive, ordered structure ona silicon or sapphire substrate. All devicenodes (gates, drains, sources and tunnelends) are accessible for logical inter-connect. All the mask definition levels,except the metal mask, are fixed. The metaldefinition mask uniquely defnes the deviceinterconnect metal for each application.

Figure I shows a typical SOS gate -universal -array layout. The interior areaconsists of internal cells of p and n devicesthat are intended for most of the logiccircuitry. The peripheral areas containlarger devices for use as input or outputbuffers. Bond pads, of course, are locatedon the periphery of the chip. Two rings

Reprint RE -26-2-10

Final manuscript received' July 28. 1980.

surrounding the internal cells distribute thepower.

The GU A technique provides the follow-ing attractive features:

Quick turnaround Cost-effectiveness for small -volume

applications High reliability Excellent probability of initial success Rapid implementation of design changes All the usual advantages of complemen-

tary metal -oxide semiconductors(CMOS)

During the past ten years GUA designtechniques have improved significantly. Inparticular, we can implement a design witha high probability of success on the initialeffort. For example, 14 of the last 15 GUAdesigns completed "worked right the firsttime." Additionally, as a result of the oneproblem -causing design, simulation tech-niques have been refined to avoid futureproblems.

The GUA has been used extensively forboth commercial and militaryapplications. Commercially, it has beenused in such applications as airborne radar,heart pacers, watches, TV cameras andcommunications control. Militaryapplications have included space com-puters, missiles and rangefinders. ManyLSI circuits have been delivered forlaboratory development and prototypeevaluation.

Importance to RCA

The first application of the CMOS univer-sal array was begun in 1973. It used the 168 -gate member of the metal -gate family.Since then, 72 GU As have been im-plemented. They are listed by RCA loca-tion in Table 1. Of these, 37 are currentlyactive in that they are either in continuingproduction or are being developed. GUAapplications have been implemented in allthree technologies. Table II gives a

breakdown by technology. Currently, theSOS GUAs account for most of the newerapplications because of their superior per-formance.

Table I. CMOS GUA applications summary.

RCA Location Number ofGUA Types

Somerville (SSD) 42

Van Nuys (AVS) 9

Camden (GCS) 3

Burlington (AS) 4

Lancaster (PTD) 4

Hightstown (AE) 4

Meadowlands (MCS)

Moorestown (MSR)

Princeton (Labs) 4

Total 72


Table II. GUA applications by technology.

Metal Gate

C2L

SOS

30

15

27

Several million dollars worth of GUAICs have been delivered to the Solid StateTechnology Center (SSTC) and the SolidState Division (SSD) customers during thelast two years. Table III gives areas of

O

no

240

230

220

2.0

200

Pro

110

.60

ISO

140

.30

..0

0 10 30 40 SO b TO

A

B

C

10 E

so

SO

0

ro

application. GUAs are used in commercialand military products. Every RCAbroadcast -TV camera, both studio andremote units, contains a universal TV syncgenerator that is compatible with a varietyof TV system broadcast standards. It is aunique proprietary design, and providesRCA with a performance/ cost/ size advan-tage over the competition. Figure 2 is aphotograph of the TK-76C broadcastquality color TV camera.

RCA Avionics Systems at Van Nuys,California, uses several GUAs in their

b 110 110 I.0 0 so

PRIMUS color weather radar. Com-mercial aviation uses this product toobserve unfavorable weather patterns andthereby avoid them. The GUA's ability toprovide low power, compact size andreduced cost together with additional per-formance features has contributed to thesuccess of the weather radar product line.

The GVS-5 Hand -Held LaserRangefinder is a versatile product beingmanufactured by RCA Burlington. Theunit is shown in Fig. 3. Artillery andinfantry forward observers can use the

1113 200 00 220 2110 140 110

IC/TES 0 \MAIM ARE 100 WINICTS NOT 101.1 0 0.1111161 NT.. DOTTED 1.1431 0623 AT ix 0 C. SIV: .2. GCS ON 041111 - f - - - --

i 3 3 444444 ID II .3 II M G MI I/ IA 0 20 2. 22 24

''''....," 200 E E .- . 'L-34 64-0 !",.--T1 tr-C.T.- '

+ -

!1.11 r=rl. rt'C nr-11-ir--1 --

ii . .

ri .14 1...JL.JL-.14.4.41",, r

,1 11" i 71, ,. ,,, 1 . 11, 712 TL I :.!! t..!!;',!.'?,,.?,, 1111j i. TR! i '43 T04

: : . " E71.-'-'1'.,,f'iIt.T. ' :T .',..., .4 4

i I i

d' .1°'S'Ii i I Ir''l 119' ''IIII2' Fei211"'I I 55r 'ri 55 'l k 55' '''1 I 55":51 i lr17,3, ' ACA TER: .

:.----17 v ', , . t,

.. Wt. '4.'4011.1-'4 a b V1-1'.1 o tiser...1 n ' . ........ . ':-...7..14- r ... o: ... 'ctitilitMftqf la if+, -1/I ORE111W-4.-_*... '-'',U '1'jr.... 11116. gr .1-1L -1,..`r - 7._-' '' r. ' ' -. ,...;;,1'

liiii.. I., a ... . - . a. 4 .. .. in .! Ia 'ladi a, , .. a .tit 7. ::: : :

: i -- I t !^01.1..a. eritiL r, ..1 ... 71 .. i - 1..:: II .1 o

+

L "C.

I ' .41..10.'1. F''. '4 ' ' *". F-. ,4 0". 0". '1 '1 0. 1 " + ' - ' r ' 1, - s e-

tri..... . cO 4100, r -, ,1, r s r, rt r J. r.

:), 5 -1:6'1.41-..ara-fl,01,..31,..?1iZEIRKWIL:.:!.

: .,,,. :,. - -

i-likii.E.'. eitf:.11: ::AL.c.41.-,e1- -i

'--.5'61tfl1 ,,:,......*:_ :,:mi ,.

1 -1A, --

ii; 4 V .1 l'3.2r4 F IV "Ir.; v.,. v411; :.f.',;io4ic.lar,,,li.,r,ii.,011,,,;i,:;i.

M r- rt f r ,111

'a 1

:!2:2'.i.k2:-:2:1;!::2--.2:',.!:2:!"..4.;Q:,1;:-.--..

i.:4,,,,,'.6-...,3.:.a:::. ::.Ti.':T:::45:: .11; .e:, ;r -1 A : ;2;: A-; A. : A.;:.A; :.,,..0 P

- ., ;3 ri,-elrlr101, s .2 tC nr

.

0 tj i11; ' 144E;

. 2440. ."4r. ..t . .DA rc r r4 ; r r r,,rvi,-

U.

Roy

-v ,v v,.y v0.v v v - rLw

Imr. syr1" .II

A

0

-

sf.4"404f.r1.1r44tfif"1.".°Pi

4.A a.41.4r4 i.1.41410.in4 ni 4,44.T.4,

in.'

3

L. -

G

. 4FIERH11"41Fkr14-6"litHi-ViTfiliFnvriNreen

" " " " " " li.rirl.f r, .1.l r, .

_V V,4"_LY . ".0.0IF* *1441-4-91- 14;

ft 0 Y. 0 it "V! 0-.0ar IV V 16.-

r

6 ro : : :PSI

on: 711 r3 ri rni ro r 111 L11,1 ri ril, r3 1;11,1 ro ;1;1 r,,i r 1 T r 1 r 1 r I1 :: my." I.02114, 6 1

11 i.

1111 10 o

1

IN I In 4, , lia e 1. ,.

.

onir-I ' . i :

1 . . LI . I. 747, '''; 41:1A4L-1. f 44:- 4 1-.11- ' i-Frli - 'Li 11 - :, 41- -.1-i.-ahl

. ,. .- .

4. I' '. '. : 1 1,43,1 IT 14'0 r 1 11;1;4 1 1 410 1 1 1!;;,r r 1 11,,,,i1 11140 11 imr I I 'm111,11401 I

fl .m. .0.1,1 iwki roLilLti im. ... -1C 'mi- -'IP_L-:riI. :.. 1:m ': 't2fit,

Iowa moo 7f M.7_, V c.-11.4. L : -

i

'..' 1. .1 7 [ : ''' I 1 1

IA.., A.`4&' imi--, , -

,_ -+

I

V3 30 SO 60 TO

1.142.12 is hs is II * lo tt tt 27 24

1+11

.

I FIGURE - TCS010- COSMOS UNIVERSAL ARRAY YE VAL PATTERNI

Fig. 1. A typical SOS gate -universal -array layout.IS II7S 4. 4. Po Igo lie TOO

p

-

.-Alr.TDR,

ou#1

F

w -#T,

_:!;:g 1:U

Z 2

X

-do do do do

Skorup: The gate -universal -array for digital CMOS 59

Table Ill. Significant applications.

Application RCA Busute.ss

Broadcast Color TV Camera

CCD Closed -Circuit TV Cameras

Classified Military Application

Global Positioning System

Laser Rangefinder

Military Computer (Navy)

Missile Fuze Timer

NASA Space Computer

PRIMUS Color Weather Radars

Standard Space &mputer

Stinger Missile

Telephone Station Circuit

GCS

PTD

SSD.

MSR

AS

SSD

SSD

SSD

AVS

AE

SSD

SSD

Vidicon Closed -Circuit TV Cameras PTD

Weather -Scout Weather Radars AVS

laser rangefinder. The operator aims andfires an invisible laser beam at the target.Then the beam's round trip travel time ismeasured, converted to target range, and"instantaneously" displayed in therangefinder eyepiece. RCA Burlington isnow developing an improved version ofthis binocular -sized unit that will pinpointtargets up to 10,000 meters away with 5 -meter resolution. The SOS UA in theimproved unit operates at 30 MHz.

Revenue from the sale of GUA devicesduring the next five years, from programsnow under development, is projected to beseveral million dollars per year.

Present GUAdesign vehicles

GUA types

Digital CMOS logic designs are now im-plementable in the metal -gate (MG),closed -cell logic (C2L) and silicon -on -sapphire (SOS) processes. The metal -gateCMOS, sometimes referred to as the "bulkprocess" or bulk CMOS, uses metal gateson p and n devices that are diffused into asilicon substrate. The C2L process usesdonut -shaped p and n devices diffused intoa silicon substrate, but uses polycrystalline -silicon for the gate material rather thanmetal. Silicon -on -sapphire (SOS) containssilicon gates on p and n silicon islands thatare formed on a sapphire substrate. Sincesapphire is an insulator, thep and n devicesare electrically isolated from each other.

Table IV lists the types of GUA designvehicles now available.

Because of their greater complexity, theC2L and SOS GUAs are being used in mostnew applications. But metal -gatetechnology has the greatest maturity andreliability history, so bulk CMOS is stillbeing usefully applied. Design turnaroundtime from layout to working parts for GUAapplications has been as short as six weeks,but more typically approaches eighteenweeks, and depends upon the design'scomplexity, the accuracy of customer -supplied information and the schedulingrequirements.

Fig. 2. TK-76C broadcast quality color TV camera.

Customer interfacing

Customers submit a logic design to theSSTC at any of the three levels notedbelow.

Level I - General Logic

The customer supplies: ( I) a general logicdiagram that has been simulated by RCA'sMIMIC (or other acceptable equivalent)software simulation program; (2) a

MIMIC -verified test pattern; and (3) othernecessary specifications. The SSTCdelivers packaged units that have beentested to the supplied test pattern and otherstandard or agreed -upon specifications.

Level II-Annotated Logic

The customer supplies: (1) a logic diagramannotated in GU A logic cells (as defined inthe CMOS Universal Array (UA) User'sManual) that has been simulated by theMIMIC software program; (2) a MIMICverified test pattern; and (3) othernecessary specifications. The SSTCdelivers ten packaged units that have beentested to the supplied test pattern and otherstandard or agreed -upon specifications.

Level III - Layout

The customer supplies all the informationof Level II, plus a layout of the logic on the125 x Mylar sheets (copies of the GUAformat of Fig. 1 at 125 times actual chipsize) provided. The MIMIC -verified testpattern must be of the logic from which thelayout was made.

Interfacing at Level I or II is

recommended when implementing onlyone or two designs. If the customer

Two universal array user's manuals are now available.For metal gate and CL applications the COSI MOSUniversal Array User's Manual is to be used. The SOSCOSI MOS Universal Array User's Manual isavailable for SOS applications.

Fig. 3. GVS-5 hand-held laser rangefinder.


Table IV. Universal -gate -array types.

Technology TypeArray Size Internal Total

( Mils) Gates GatesTotalPads

Metal -Gate CMOS TCC 040 189 x 188 138 168 40(MG COS/ MOS) TCC 051 229 x 232 240 276 48

Silicon -Gate CMOS TCC 220 156 x 155 138 168 40(CI COS/ MOS) TCC 221 186 x 188 240 276 48

TCC 222 216 x 220 370 410 48TCC 223 245 x 252 528 576 64

Silicon -Gate CMOS TCS 090 ISO x 150 144 182 40(SOS COS/ MOS) TCS 091 180 x 180 256 300 48

TCS 092 210 x 210 400 452 64TCS 093 240 x 240 576 632 64TCS 094 270 x 270 784 848 80

*A gate consists of two p and two n devices and is the equivalent of a two -inputNAND or NOR gate.

anticipates several GUA designs and wantsto minimize his cost, he may use the LevelIII interface. Although the layoutprocedure is straightforward and describedin detail in the COS/ MOS Universal ArrayUser's Manual. accurate and effectiveinterfacing at Level III requires sometraining.

Customers who want to interface atLevel Ill can take three to five days andattend a GUA design course given at RCA(several have done this).

Technology selectionWe select the technology for any specificapplication after comparing the applica-tion requirements with the attributes of thethree technologies available. See Table Vfor some of the more significant attributes.These general guidelines provide somequantitative feel for the tradeoffs betweencompeting technologies.

I. Metal gate ( MG) and CI vehicles canoperate at somewhat higher frequencieswhen used without set or reset. The SOSGUA has two custom binary stageswhich do not have set or reset and willoperate up to 100 MHz. These stages arequite useful for pre -scalers, where onlythe input stage must operate at thehighest frequency. The above values aretypical and they reflect a realistic com-parison of overall speed for com-binational (non -clocked) logic as well.In other words, CI, is twice as fast andSOS is four times as fast as MG CMOS.

2. Average pair delay is the averaged valueof inverter, two -high NOR, and four -high NOR gates with a fan -out (eachgate is considered a load or fan -out ofone) of one and no series tunnelresistance. Actual on -chip delays will be

Table V. Technology comparison at room temperature and10 -volt operation.

Attribute MG L SOS

Specification Mil/ Com Mil/ Com Mil/ Com

Maximum Binary 10 MHz 20 MHz 40 MHzwith reset (1)

Average Pair Delay (2) I6ns 8 ns 4ns

Mask Compatibility (3) yes yes no

Voltage Range 1.1 - 20 3 - 12 4 - 11

Power Dissipation low low 10w

Gate Complexity 168- 276 168 - 576 182 - 848

Number of Pads 40 - 48 40 - 64 40 - 80

increased by fan -out, series tunnel -resistance and coupling capacities.

3. A metal pattern defined for use on ametal -gate UA may be applied to its C2Lcounterpart (and vice versa) withoutany change in layout. New advances inbulk technology and continued progressis SOS promise increased performanceand greater density in bothtechnologies.

GUA procedures

Design

The design cycle begins with the customercreating a logic diagram of the intendedsystem. Logic to be implemented withuniversal arrays is annotated using theuniversal -array cell library listed in theCOS/MOS Universal Array User'sManual. An operator then enters a logicnet list of all logic functions and their inter-connect into a software file, and the list isexercised by a simulation program forcircuit evaluation.

The SSTC has recently developed asoftware program for logic simulationcalled MIMIC. This program is compati-ble with universal -array implementationsof LSI digital logic and we have used iteffectively for both pre -layout and post -layout circuit performance evaluations.

After verification, the complete logicconfiguration is partitioned into one ormore universal arrays. Array sizes arechosen to achieve the least number of inter -chip connections, as well as to minimize thenumber of different chips. Where possible,we specify more chips per system, but fewertypes. This minimizes the number of chipdesigns.

Once specific chip logic is defined, the

test pattern is generated. In the past, thechip was designed and implemented beforethe test pattern was generated. This ap-proach can be costly in time and resources.As chips become increasingly complex, thetesting aspect becomes paramount becausetesting is becoming increasingly expensiveand it is possible to design a chip thatcannot be tested. Tester time should beused primarily for testing chips withproven test patterns, and not fortroubleshooting. Troubleshooting needs tobe done off-line with software as much aspossible.

A chip must be designed for testability.Good design practice includes adding setsor resets to all counter states (for initializa-tion purposes) and sectionalizing longcounter chains into shorter ones (forreduced test time).

The test pattern is generated to exercisethe logic of the chip's intended use, or itmay be generated to exercise all inputs andoutputs. In either case, we use the testpattern to exercise the software logic priorto chip implementation. After completionof the software evaluation, the customerwill then layout the universal -array chip.

Implementation

The procedures for implementing a GUAdesign (Fig. 4) presume interfacing with thecustomer at Level III. Blocks A through Eare the inputs received from the customer.These are the input test pattern, the logicdiagrams (in UA logic cells), the UA layout(125 x Mylar), the expected output testpattern and other test specifications.

The Mylar layout (C) is a i 25X represen-tation of the given universal -array (Fig. I).The design is implemented by applyinglogic decals and manually drawing logicalinterconnections on the layout. This com-


(A

INPUTTEST

PATTERN

(B

LOGICDIAGRAM

(C

- H

MYLARLAYOUT

(0

4 -

OUTPUTTEST

PATTERN

(E

TESTSPECS

NO

DIGITIZELAYOUT

AGS 4(4)

CHKPLT

(2)

EXTRACTNET LIST

ARTCON NO

(5)

VERIFYTES -

PATTERN

MIMIC

(7)

CREATEMASK

MAPSANDRAMEBES

(8) (9)

FABWAFER

TES1WAFER

1DATA-aTRON

(10)

--410 PACKAGE

(II) (12)

TESTPACKAGE

DATA -"TRON

Fig. 4. The procedures for implementing a GUA design.

pletely specifies the custom metal of thedesign. Using the Applicon GraphicSystem ( AGS), the designer digitizes (I) thelayout. This step captures metal patterngeometries into a software file. A computerprogram (ARTCON) (2), creates a logicalnet list from the custom metal, device andtunnel -location information. It essentiallycreates a logic diagram of the actual IClayout and presents it in net -list format.The program compares (3) the ARTCONnet list with the customer -supplied logicdiagram. Concurrently, a Xynetics plottercreates a checkplot of the digitized infor-mation directly from an Applicon-generated magnetic tape. Any dis-crepancies made obvious by ARTCON arelocated on the checkplot and corrected.This cycle is repeated until the AGS designfile is exactly the same as the logic diagram.With this procedure, one is assured that thelogic of the actual chip design is exactly thesame as that of the customer -suppliedlogic.

Subsequently, an operator enters the netlist (2) and the customer -supplied input testpattern (A) into MIMIC (5) for test -

pattern verification. The MIMIC programwill exercise the actual chip logic with thesupplied input test patterns.

Any discrepancy between the two outputpatterns is due to an error in either theinput test pattern, the output test pattern,the logic diagram or the mylar layout. Theerror, wherever found, is corrected and theprevious cycles repeated (as required) untilcompare (6) is correct.

At this juncture, the actual chip designhas been tested and verified (by software)before any costly mask -making or wafer-fabrication expense occurs. The engineer-ing phase is complete. All unique aspects ofthe design are complete. The remainingsteps involve repetitive proven processes.This is not to say that mask -making, wafer -fabrication, testing and packaging aretrivial operations. On the contrary, theyinvolve sophisticated equipment and com-plex processing operations. But theprocedures described here assure, withhigh probability, that the finished parts willperform as intended.

A manufacturing electron -beam equip-ment system (MEBES) makes

SHIP TOCUSTOMER

photographic plates (masks) for waferfabrication (7). MEBES is driven by amagnetic tape derived from the verifiedAGS design file. Additional softwareprograms such as MAP and SANDRA areused for this purpose (to create the tape).MOS wafer fabrication (8) requiresfinished masks. Finished wafers are tested(9), and output test patterns (D) and othertest specifications (E) are applied to theDatatron for wafer test. Good pellets arepackaged (10) and retested (II) andshipped to the customer.

Future plans

Future GUA development will emphasizethe following areas:

Higher device count and density with agoal of approximately 2000 gates.

Use of computer -aided placement androuting to reduce layout time and cost.

Development of design for testing tech-niques and design vehicles that willreduce test time from an exponential to alinear function of logic complexity.


For years, the GUA has been designedconservatively to ensure ease of manufac-ture, predictability of performance andhigh reliability, making it applicable toboth military and commercial products.Current improvements in process engineer-ing will allow greater device density, highergate -count and improved performancewithout sacrificing a conservative design.

Increasing logic complexity per chipdemands that we develop more efficientmeans for logic placement and inter-connect routing. Significant progress hasbeen made. The Advanced TechnologyLaboratories (ATL) of GSD hasprogressed significantly toward this goalby developing an automatic placement androuting program for a universal array(AUA). Efforts are being made to apply theresults of the ATL program to the develop-ment of an operational AUA vehicle.

Again, LSI testing has become the mostdifficult, time-consuming, and costlyaspect of LSI design. The number ofrequired test patterns or vectors increasesexponentially with LSI complexity. Devicetesting is expensive for the componentmanufacturer, the equipment manufac-turer and field service personnel. The ICindustry recognizes this problem. Currentsolutions involve placing the logic at thedesign level so as to simplify the testingproblem. This means using more circuitry

Gordon Skorup, Senior Member of the Technical Staff, Solid State TechnologyCenter, joineo the Home Instruments Division of RCA in 1946 where he was engagedin the design of both tube and transistor TV receivers until 1960. He then transferred tothe Missile and Surface Radar (MSR) divi-sion where he had project engineeringresponsibility for the design and develop-ment of prototype optical -correlation equip-ment for undersea warfare. From 1966 to1969 he was responsible for all PMOSapplications and proposals in the MSRdivision, during which time he was awardedthe Chief Engineers' Technical ExcellenceAward. Since 1970, as a member of theMonolithics Applications group of Govern-ment Communications Systems, and laterSSTC, he has been responsible for thedesign and application of PMOS and CMOSuniversal arrays. For these efforts, he wasrecently awarded the PrincetonLaboratories Outstanding AchievementAward.Contact him at:Solid State Technology CenterRCA LaboratoriesSomerville. N.J.TACNET: 325-6388

for the same logic function, and increasingthe chip size for a given design. But weexpect that the additional costs of chipfabrication will be more than offset by thesavings in initiating and using test patterns.This is especially true for the GUA, wherethe cost of developing and verifying a testpattern is a large part of the design cost andis amortized over a relatively small volumeof product.

Conclusions

The gate -universal -array concept is a cost-,time- and resource -effective means for theimplementation of both commercial andmilitary logic systems. The concept willcontinue to assist the RCA divisions inusing in-house CMOS LSI technology tocompete more effectively in themarketplace.


E.J. Mozzil C.A. Schmidt

Custom LSI: an effective tool fordigital communications equipment design

Why LSI? When LSI? How LSI? Here's what RCA'sTENLEY/SEELEY program is doing to answer theseapplications problems.

Abstract: Practical, applications -orientedexamples from the TENLEY I SEELEYprogram to develop cost-effective,military, digital communications equip-ment show how LSI and computer -aideddesign can actually be used.

IntroductionA major thrust in military systems is to usecomplex digital communications equip-ment. This is economically possible only ifmodern LSI technology is employed. TheTENLEY/ SEELEY program is an out-standing example of the development ofcost-effective military equipment by thesuccessful application of custom LSItechnology. This program proved out afamily of LSI design automation and arigorous LSI design discipline. The results,from concept formulation to equipmentfield deployment and test, have been out-standing.

The TEN LEY / SEELEY program beganat RCA in 1972. It was obvious that theequipment performance and complexitycould only be realized through the use ofLSI. A total of 60 LSI array types weredesigned and developed, and more than50,000 arrays have been -produced to date.No arrays required redesign due tofunctional deficiencies. The technologyused was bulk CMOS in both custom andstandard cell configurations. All cost,

Reprint RE -26-2-11

Final manuscript received Aug. 15. 1980.

delivery and performance commitmentswere met or exceeded, and a contractualdelivery incentive award was earned.Equipment reliability tests fully sub-stantiated the anticipated LSI perfor-mance. A total of 1500 equipments of 29different types were delivered during theR&D phase.

A primary factor in program success wasthe design methodology employed.Computer -aided design (CAD) played avital role in design, simulation, layout andtesting efforts. Also significant, automatictest equipment and compatible complextest patterns were developed for LSI andprinted wiring assembly design verificationand failure diagnostics.

A final ingredient to the success ofTENLEY/ SEELEY was the skill andeffectiveness of the Government -contractor team. The program was con-ducted by RCA's Government Com-munications Systems (GCS) of Camden,New Jersey. Key support was provided byother RCA units: Advanced TechnologyLaboratories (ATL) also of Camden, andthe Solid State Technology Center (SSTC)and Solid State Division (SSD) both ofSomerville, New Jersey. This collectiveteam, bringing to bear a synergism oftechnology, device, equipment, systemsand dedicated design personnel, representsa total design and fabrication capability.Finally, the Government customer servedas a full member of the team, providingguidance and direction to all elements ofthe program, and sharing in the rewardsand (few) disappointments.

Why LSI?

In general, the advantages of LSI hinge onthose characteristics most important totoday's equipments - size, weight, power,reliability and cost. A decision to use LSImust also weigh the practicality - theability to design LSI devices that willsatisfy the particular application withincontractual budget and schedule con-straints. The design of new LSI devicesobviously introduces an element of riskwhich when recognized and addressedproperly can be retired effectively.

In the case of TENLEY/ SEELEY,deployment of the equipment would nothave been possible without the use of LSI.The functional performance requirementscoupled with the size, weight, power andcost constraints dictated a high -logic -density, low-cost, high -reliabilitytechnology.

Table I compares the significant designfactors of LSI with those of a CMOSSSI/ MSI CD4000 implementation. Thelogic speed, although a strong point for

Table I. Design factors.

Ratio ofDesign parameter CD4000 to LSIArea 37.8

Weight 128

Volume 74

Power 25

Life cycle cost 5.8

MTBF (Mean time between failures) 0.048


Table II. Why LSI?

Design advantages from Table /

Sin and weight Cost

Power

Reliability

Factors hearing on practicality(design risk factors)

Design automation availability

Radiation hardening

Customer acceptance

producibility

Military environment compatibility

LSI, was not a critical consideration - thespecified maximum clock frequency was 1MHz and maximum data rate was on theorder of 64 kHz. Note that LSI offersoutstanding advantages in all the factorslisted. In developing the ratios shown, theeffects on the total equipment design wereanalyzed, not just the specific componentsinvolved. For example, the weight, areaand volume take into account the wiring,printed board area, and overall equipmentdesign. Equipment quantities of 150 wereused in the analysis for life cycle cost.

Table II highlights the major reasons forusing LSI specifically for theTEN LEY/ SEELEY program. Includedare the design factors from Table I, pluscertain factors bearing on practicality ordesign risk. Design automation for designsupport, and performance verification aretwo factors that call for special emphasis. Adriving force for CAD has been thepractical need for LSI. The CAD toolsavailable in RCA and the industry for LSIare incomparably better than during theearly years of SS1 and MS1 development.Radiation hardening for survivability in atactical nuclear environment was achievedbasicallly by the technology selected (bulkCMOS) and the active device size andprocessing. Enhanced producibility was aninherent result of the reduced assemblylabor and component -part count. The ul-timate result was meeting the performancerequirements in an implementation con-figuration that was highly acceptable to thecustomer.

Figure 1 is a typical wirewrap boardwhich was used to breadboard and test theLSI logic prior to committing to a finaldesign. This particular wirewrap boardcontains 67 CD4000 SSI and MSI devices,which were ultimately replaced by thesingle LSI chip shown in the figure. Thesize reduction is impressive, but just as

I lk rural

Fig. 1. A typical CD4000 wirewrap board (front viewl.

significant is the elimination of the ap-proximately 600 wires on the reverse side ofthe wirewrap board (Fig. 2). This reducescost and enhances producibility andreliability.

The TENLEY/ SEELEY breadboardequipment was assembled using severalwirewrap boards to implement thefunctional logic, as partitioned into LSIarrays. Figure 3 illustrates one typicalbreadboard equipment composed of 16wirewrap boards, 1I of which arefunctionally equivalent to the LSI dis-played immediately next to them. As adirect result of the application of LSI tothis equipment design, the total equipmentfinal configuration was realized on basical-

ly one multilayer printed wiring assemblyas shown in Fig. 4.

When LSI?

One of the most important questions askedconcerning the application of LSI is4

"When does custom LSI application toequipment design and developmentbecome cost-effective?" A critical examina-tion was made of both recurring and non-recurring costs for a typical CD4000 designand its equivalent LSI implementation.Table Ill compares the non -recurring costsfor the two design configurations, assum-ing a printed circuit board assembly for

Fig. 2. A typical CD4000 wirewrap board (rear viers).

Mozzi/Schmidt: Custom LSI: an effective tool for digital communications equipment design 65

I

IV

ill11 I"hir I%:7t- .

1)111111:

[

11 11

if

N/A et.

Fig. 3. A typical breadboard equipment.

each of them. As expected, the non-recurring LSI costs are considerably higher(greater than 2 to 1) than the CD4000configuration. The significant costs for theLSI are in the simulation and automaticplacement and routing (APAR) layout andthe fabrication costs.

Table IV lists the recurring costs for thetwo techniques and obviously the LSI costs

Fig. 4. An LSI equipment.

are lower. In this example, the lower costsfor LSI must amortize non -recurring costdifferences. Quantities of 150 were used fordeveloping these costs.

Once the recurring and non -recurringcosts are established, the cost crossover canbe determined (Table V) by dividing thedifference in non -recurring by thedifference in recurring costs per unit. The

Table III. Non -recurring costs.

Non -recurring tasks CD4000 LSI

PCB drafting S 8,000 S 400

PCB artwork 2,100 210

PCB board test fixture 2,000 160

PCB assembly process 1,800 90

PCB test process 2,400 120

PCB assy/ test fixtures 1,700 85

Initial fabrication* 11,600

Simulation/ APAR 16,500

Computer cost 2,250

Reticle fabrication 1,000

Data coordination 1,500

Qual test 3,000

= 18,915

Total S18,000 $36,915

*Compensated for sample chips

somewhat unexpected result is that the costcrossover occurs at 49 units, which isconsiderably lower than commonlyreferenced. In fact, this cost crossoverpoint would be even lower if life cycle costfactors were considered: e.g., logistics(sparing one part versus several parts, etc.),training of service personnel, reliability,cost of ownership, etc.

How LSI?

No design or implementation technology,whatever its promises and illusions ofgrandeur, is worth its weight in salt (orsilicon) without a useful methodology toserve as a proven guide to successfulapplication. It is no accident of fortune thatthis methodology does exist for LSI arraydevelopment. Many years of study andpractical experience within RCA(specifically TEN LEY / SEELEY) and theindustry have resulted in the methodologydescribed in Fig. 5. The importance of thismethodology cannot be overemphasized,and although it cannot guarantee success100 percent of the time, it certainly canavoid correctable disasters.

The primary keys noted in Fig. 5 are thefour reviews, which serve as toll gates in amainstream serial fashion prior to designrelease for device fabrication. The initialstep in the design cycle is the systemconcept review (I) which establishes thefunctional performance and detailedsystem interface required. Subsequently,the logic partitioning and design is ac-complished followed by a preliminary logicreview (2). For this review, the designerprepares a detailed design review package


Table IV. Recurring costs.

Recurring CD4000 LSI

Active parts $327.0 $70.00(67 CD4000 DIPS)

PC board 45.0 3.75

Connectormounting pair 38.00 3.16

Assembly 26.25 1.74

Test troubleshoot 16.00 1.25

QC PM1 14.00 .70

= 386.65

Total $466.25 $80.60

Table V. Cost crossover.

Non -recurring = $36,915- 18,000 = 18,915, LSI

Recurring = $386/ CD4000

Crossover = 18.915 = 49 units386

which specifies the requirements, thedesign to satisfy these requirements, worst -case circuit and timing analyses, and designfor testability. Testing of an LSI chip is notan afterthought, but rather a very impor-

0(SYSTEMCONCEPTREVIEW

RELEASEFINAL

WAFERPRODUCTION

-1--

LOGIC

PARTITIONAND

DESIGN

0_elPACKAGE FINAL

SAMPLES TEST

WAFER

PROBE

WAFER

PROBE

tant part of the design process. Present atthe review are representatives of thecustomer as well as all design disciplinesnecessary (such as reliability, test process,nuclear survivability, parts application,system, logic and circuit engineers, etc.).Action items generated at the reviews mustbe answered prior to design finalization.

Following the preliminary logic review,a very critical phase is entered wherecomputer -aided -logic simulation and test -pattern development is initiated, in parallelwith the CD4000 equivalent breadboarddevelopment. The results of both of theseefforts are compared and analyzedrepeatedly, and brought to the final logicreview (3), together with action itemresponses from the preliminary logicreview. Pending design approval at thefinal logic review and/or satisfactoryresponses to any action items generated,the array layout effort is started, followedby a layout review (4). At this point, we arestarting to "pour the concrete," and anyresidual errors will prove costly in subse-quent artwork generation and chip fabrica-tion.

Once the layout review is completed and

0PRELIMINARY

LOGICREVIEW

_IBUILD

LSIBREAD-BOARD

VISUALCHIP

INSPECTION

WAFER

PRODUCTION

EDEVELOPCD 4000

LOGICBREADBOARD

LOGICSIMULATION

ANDTEST PATT

INTEGRATEAND TESTLSI BB

IN SYSTEMBB

all action items are resolved, the devicefabrication cycle (5) is initiated, leading topackaged, tested samples (6). Thesesamples are put into the same breadboardthat was used to test their CD4000 counter-part as a functional replacement. Thepackaged LSI arrays are then tested bothfunctionally and parametrically, asapplicable. This testing serves as a mostcritical design verification prior to finalwafer production release. Now the con-crete has been poured, but in a form whichhas passed through a series of critical tollgates to develop a high degree of con-fidence in the final result. There is a distinctthrill of victory in completing a disciplinedmethodology and realizing militaryqualified parts meeting all the functionalrequirements of the total design. Withoutthe disciplined approach, the almost cer-tain alternative is an agony of defeat.

The time scale at the bottom of Fig. 5identifies approximate schedules for ac-complishing the milestones. Elapsed timesshould be taken as typical, and can beimproved or worsened, depending uponthe difficulty of the design, the size of thearray and the fabrication cycle queueing.

BOND

CHIP INPACKAGE

MIL -STD883

PRE -CAPVISUAL

( METHOD1k 2010 /

MASK

PRODUCTION

SEALPACKAGE

UPDATELOGIC

DESIGN

1

FINALLOGIC REVIEW

7

ARTWORK

GENERATION

LAYOUTREVIEW

ARTWORK TAPER,,LFASF-DFL TAPE

0 2 4 8 10 12 14 16 IR

ELAPSED TIME IN WEEKSFig. 5. LSI array development methodology.

MIL -STD883

SCREENING

m-41.BURN -IN125'C MIN

FOR 160 HRS

CHIPLAYOUT

0FINAL

ELECT TESTHI /L0 TEMP

( METHODL5004 -

MIL - 38510 GRADE PARTSMIL- STD 583 -CLASS B

, 1

20 22 24 26 28


Table VI. LSI CAD design tools.

Design tool Function Where available

I. TESTGEN

2. LOGSIM

3. APAR (MP2D)

4. CRITIC

5. ARTGEN

6. RCAP

7. Applicon ( DFL translation)

K. TACC (SOS)

9. APRAIS (Bulk CMOS)

10. CALCOM P

I I. SPICE

12. Data conversion programs

13. MIMIC

Logic simulation

Logic simulation

Chip layout

Layout rule violations check

Artwork generation programs

Circuit analysis

Manual layout Mod.

Routing & interconnect rules

Routing & interconnect rules

Layout plotting

Circuit & failure analysis

Data format translations

Logic simulation

Time share (CMS)/ Prime

Time share (CMS)

Prime

Time share (ISO)

Time share ITSO) Prime

Time share (CMS)

ATL

ATL Comp. CIR.

ATI. Comp. CI K.

ATL Comp. CFR.

Prime

Prime

Time share (CMS ISO)

In summary, the successful applicationof LSI depended on the design process,which in turn was made possible by the useof the CAD tools available within RCA.Table VI lists thirteen design tools whichconstitute an impressive capability forsupporting design, development andtesting of LSI arrays. Comprehensiveprograms are available covering all thenecessary design elements: logic simula-tion, array layout, circuit analysis, designand layout rules checking, failure analysisand layout plotting. Table VI also lists thesource for these tools. Some of the toolswere used on TENLEY/ SEELEY, somewere not necessary, since some of the toolsare design options presented to the user forspecific design optimization compatibility.It should be borne in mind that these toolsare continually being updated and im-proved, based on user feedback, and thatnew tools are also being developed as theneed arises.

Testing the results

Almost as critical as the design itself is thetesting methodology and the developmentof the necessary techniques and tools forthe testing of LSI arrays and the assembliesand equipments in which they are used.During the TENLEY / SEELEY program,every design review included intensiveattention to testability. Manual testing ofindividual devices which include thousandsof gates in complex logic functions, withmultiple inputs and outputs, is notpracticable. Such testing would require avast number of very highly skilled testerswith infinite patience, who would be will-ing to spend many hours with a complexassortment of test equipment trying to

verify the performance of an LSI array toextremely demanding functional andparametric specifications. If there weresuch talents in the numbers required, therecertainly would not be enough moneyaround to pay for them.

The basic problem escalates when 20 or30 of these LSI devices are assembled ontoa printed board, and escalates again whenmultiple assemblies are integrated into afunctional equipment. If the basic design isconducted properly, the logic is functional-ly partitioned into testable groups suchthat, as the degree of integration increases,the testing complexity decreases. Further-more, the basic logic elements are designedto be testable, that is, registers are settableto known states, counter states aredeterministic, outputs are predictable, etc.

On TEN LEY/ SEELEY, specialautomatic test equipment was developedfor the depot, intermediate. andorganizational level equipment mainte-nance levels; techniques were alsodeveloped for individual part testing onstandard equipment. Significantly, theequipment maintenance functions wererequired to include both go/no-go accep-tance and failure diagnostics functions.The two areas where LS1 testing is ofprimary importance are (1) at the depotlevel maintenance area, where test equip-ment must be capable of isolating faults ina defective assembly to the bad component,and also to verify corrective action prior toreturning a repaired assembly to the field,and (2) at the LSI fabrication area, whereperformance of individual devices to aspecification must be verified.

On TEN LEY / SEELEY, designersdeveloped LSI array test patterns for theDATATRON 4400 equipment; complex-ities were as great as 2000 test patterns each

42 -bits wide. For the printed wiringassemblies, greater than 60,000 testpatterns up to 160 -bits wide were necessaryper printed wiring assembly. Theseassembly test patterns were not onlycapable of doing go/ no-go testing, but theywere also required by specifications todetect greater than 95 percent of the faultson the assembly, and to isolate greater than85 percent of these faults to a single node.Both of these specifications, for fault detec-tion and isolation, were met or exceeded.

The LS1 assemblies used onTEN LEY/ SEELEY were multilayerprinted wiring boards with a maximum offourteen layers. The LSI devices wereinserted into the boards with through -holelead insertions and one-time wave solder-ing was used for the integrated assembly.No problems were observed with theprinted wiring boards or in implementing areliable LSI component interface. TheTEN LEY LSI printed wiring assemblyshown in Fig. 6 includes twelve custom 42 -lead CMOS LSI arrays plus some discretecomponents. The obvious advantages ofusing LSI are evident, as are the problemsof testing a board of this complexity andisolating faults to a single node.

The special automatic test equipmentwas developed to accomplish faultdiagnostics for printed wiring assemblies( PWA). This equipment used a minicom-puter processor in conjunction with anX/ Y movable table and fixed single andmultiple pin probes. For go/ no-go testing,the probes were in general not necessary,since all tests were accomplished throughthe board connector. The basic principleused for the automatic test equipment(ATE) is to apply input patterns to aknown good PWA and record outputresponses on a disk. These responses aresubsequently compared with the responsesof a board being tested. Any differences arenoted and recorded as a failure or no-gocondition. Once a no-go or fault conditionis found, a diagnostic program is enteredwhere nodes are probed in a sequentialpattern from the fault until the faulty nodeis discovered. The special ATE developedwas capable of applying input patterns at a10 kHz rate, and diagnostic and go/no-gotesting was rapid and extremely cost-effective.

The conclusive facts

Now that we have covered the why, whenand how of custom LSI design and applica-tion, and the testing methodology, we can


Fig. 6. An LSI printed wiring assembly.

turn to the conclusive results on theTENLEY/SEELEY program. These es-tablish beyond question the advantages ofLSI in military systems and environments.

The technology used was proven metal -gate bulk CMOS, primarily in standardcell designs, using totally custom im-plementation only where dictated by thedesign complexity, or where obviousdesign improvements were possible (suchas in regular repeated functions). Thestandard cells used were developed byRCA in conjuction with the necessaryassociated CAD (largely by ATL, onGovernment funding as well as extensiveinternal support).

There were 60 LSI types developed, withno reworks decessary to achieve the re-quired functionality. This was a first-timeachievement for both the customer andRCA on any program of comparablecomplexity. Of the 54 types developedearly in the program, 37 were developed in23 months on TEN LEY, and 17 onSEELEY in 11 months. There were 19,000chips of 37 types produced on TEN LEY insix months, primarily at RCA's SSTCfacility in Somerville. The total number ofchips produced to date is greater than50,000, the majority of which were suppliedby RCA's SSTC facility supported by SSDand two external sources (Hughes andSolid State Scientific, both qualified byRCA for the TENLEY/SEELEYprogram).

Table VII lists the TENLEY/ SEELEY

LSI array statistics, the range of complexi-ty and size further attest to the designflexibility. The largest chip shown (213 x231 mils) was a custom design which used aspecially designed large cell (not a part ofthe standard cell library) to produce a cost-effective functional partitioning within athen practical large physical size. At thetime that the TENLEY/ SEELEY chipswere designed, 1972-1977, greater than 200mils on a side was considered a large array.

Table VIII sets forth the complexity ofthe LSI arrays developed. These complex-ities represented the state of the art at thetime, and are still compatible with goodprocessing yields for high quantity produc-tion.

Extensive reliability testing was ac-complished in functional equipmentqualification for military environments.On the TEN LEY effort, 1200 LSI arrays of36 different types were tested in threeoperational equipments per MIL -STD -781B Level E over a temperature range of-45°C to +65°C. A total of 2,160,000device hours were compiled with zero

Table VII. LSI array statistics.

Table VIII. LSI array complexity.

Minimum Maximum

No. of cells (STANDARD) 51 188

No. of devices (XSTRS) 341 1554

Linear mils 335 1359

Largest LSI was a custom design 213 x 231 (49.2Kmil-) containing 2348 devices.

failures. Reliability testing conducted onthe SEELEY effort demonstrated confor-mance of the two high usage LSIequipments to mean time between failure(MTBF) requirements of greater than 5000hours. During this equipment testing, over1,000.000 LSI device hours were ac-cumulated. The equipments wereoperational during the testing, which in-cluded temperature and vibration stress-ing.

At the present time, all of the TENLEYequipments (which include 31,261 chips)have been delivered and are being used inthe field. To date, the equipment andassembly depot repair effort at RCA hasreported 18 LSI failures repaired in

defective hardware. This represents a smallpercentage of the equipment failuresrecorded, and is an extremely smallnumber considering the quantity of devicesdeployed in field service.

A specific requirement on theTENLEY/ SEELEY program was equip-ment survivability in a nuclear environ-ment. The equipment test results showedno failures during electromagnetic pulse(EMP), gamma total dose, gammatransient dose or neutron fluence at-tributable to LSI devices. In addition,individual device tests on LSI arraysdemonstrated the relative inherenthardness of the CMOS LSI devices for atactical nuclear environment.

A representative custom bulk CMOSstandard cell LSI array developed on theprogram is shown in Fig. 7. This arraymeasures 211 x 209 mils, contains 1482devices, 188 cells, and uses 1348 linear mils.The regular pattern and physical layoutcharacteristic of a standard cell designconfiguration is evident.

ProgramNo. of types Largest chip Smallest chip Quantity produced Technologydeveloped (mils) (mils) to date (9/79) used

TENLEY

SEELEY

41 (213 x 231) (128 x 148) 31,261 Bulk CMOS customand standard cell

19 (208 x 225) (167 x 1581 19.312 Bulk CMOSstandard cell


Edy Mozzi is a program manager in theDigital Communications Systems Group ofGovernment Communications Systems. Hewas employed by RCA in 1952 and has beeninvolved in advanced technology develop-ment for military applications, both digitaland analog, for the majority of hisassignments. He has been a member ofAdvanced Technology Laboratories, Astro-Electronics, Solid State Division andGovernment Communications Systems.Contact him at:Government Communications SystemsCamden. N.J.TACNET: 222-3729

Charles Schmidt is presently Manager, In-tegrated Communications Systems inGovernment Communications Systems. Hehas held various management positions inCSD and GCS. This management ex-perience has included positions inengineering, program management andmanufacturing.Contact him at:Government Communications SystemsCamden, N.J.TACNET: 222-4697 Authors Charles Schmidt (left) and Edy Mozzi (right).

Concluding remarks

The TENLEY/ SEELEY programrepresents a significant achievement in theapplication of custom LSI to militarydigital communications equipment.Successful results were achieved throughthe use of a disciplined designmethodology, coupled with close attentionto the total design problem and emphasison testability and intelligent logicpartitioning. Computer -aided design was amajor contributor, without which it is

doubtful that the program objectiveswould ever have been met. The design tech-niques and methodologies developed haveserved and are continuing as guidelines formany new programs. The equipment statushas gone from R&D to the anticipatednear -future initial production. The es-sential role of collective achievement,based on the intelligent use of the requiredskills available in ATL, SSTC, SSD andGCS as well as the active participation ofthe Government customer, was a majorfactor on the program. Although there wasconsiderable skepticism at the programoutset, particularly regarding the LSIdevelopment schedules, the team dedica-tion never faltered. In the end,TEN LEY/ SEELEY made "believers" outof many of us, both Government and RCApersonnel.

RCA Engineer 26-2 Sept./Oct. 1980

R.E. Stricker A.G.F.Dingwall

Advances in CMOS static memory development

RAMs contribute a lion's share to the overall memory/micro-processor total business and RCA locks horns with thecompetition by improving circuit densities and access timesin bulk CMOS and CMOS/SOS static memories.

Abstract: The historical development of05 RAMs, together with a summary of

the general modifications and trends indevice structure, interconnect topologyand access times, leads to projections forfuture developments in LSI and VLSI.

Recent advances in very large scale integra-tion (VLSI) have brought about majorgains in the size and performance of metal -oxide semiconductor (MOS) memories.Using dynamic NMOS memory tech-niques and a one -transistor cell, thesemiconductor industry has pushedbeyond the 16K level, is delivering smallquantities of 64K random access memories(RAMs) and has fabricated a few 256Kdevices in the laboratory. With thesedevelopments, we believe the semiconduc-tor market could exceed one billion dollarsby the mid -1980s.

Semiconductor memories havehistorically been at the leading edge oftechnology providing the driving force fortechnology advancement. Any intelligentcontrol system, data acquisition system ordata manipulation system is rich insemiconductor memory content. For ex-ample, a typical microprocessor -basedsystem for engine control in the automobileindustry uses one microprocessor or micro-computer for data manipulation and in-struction execution, one read-onlymemory (ROM) for resident programstorage, an input/output (I/O) circuit forinterface with various sensors and one tosixteen RA Ms for intermediate data

Reprint RE -26-2-12

Final manuscript received July 15, 1980.

storage and calculation. As system com-plexity increases, the memory content ofthe system increases drastically. Thus,RA Ms contribute a lion's share to theoverall memory/ microprocessor totalbusiness.

While much of the memory market willbe served by the lowest -cost, largest -capacity dynamic NMOS memory chips,an important section of the market willrequire the performance advantages af-forded by static memory that complemen-tary metal -oxide semiconductor (CMOS)technology can provide. Among the advan-tages provided by static memory areshorter access times, lower standby power,easy interfacing, improved reliability, andthe ability to operate over a wide range oftemperatures and power -supply voltagelevels. The advantages will provide asignificant performance edge in industrialand military systems, in automobiles whereextreme temperature conditions are en-countered, in cash registers where protec-tion of data against power -supply failure iscritical, and in hand-held portable systemswhere low battery -drain levels must bemaintained.

High densityCMOS/SOS RAMs

RCA has participated actively in both thebulk CMOS and CMOS / silicon -on -sapphire (SOS) memory markets whichhave also achieved circuit density im-provements in recent years. Figure I com-pares recent trends for both CMOS anddynamic NMOS memories. DynamicRAM density has been doubling ap-

proximately every two years. Dueprincipally to the larger number oftransistors employed per cell, static RAMsare typically a factor of five -to -six timessmaller in capacity than dynamic RA Ms atany given time. We can infer from thistrend that static RAM designs lag theirdynamic RAM counterparts by four years.Assuming trends of Fig. I remain valid, theCMOS suppliers will want to be preparedto make 64K RAM chips in 1983.

400K

2

100K

4

2

108

4

2

I K3

5

4

2

0.IK1975 1980

YEARFig. 1. Growth of MOS memory capacity.

1970 1985


We should, at this point, examine thehistorical development of CMOS RAMs.The two major driving forces behind RAMdevelopment, so far, are the cost per bit ofmemory storage and performance.Although the cost of any product isgoverned by many complex relationships,we assume that the cost is strongly relatedto the number of bits of storage of memoryper given circuit. Simply stated, improvedcircuit density, or the ability to pack moretransistors into a given area, is the drivingforce behind low cost memory develop-ment.

There are two fundamental methods ofincreasing density: reduction in featuresites in order to produce smallertransistors; and changes in the topologicaldevice structures and the fabrication se-quences to obtain higher density. Reducedfeature sizes, and the fabrication equip-ment required to produce these smallfeatures, is discussed in another article inthis issue ("Advanced Process Technologyat the Solid State Technology Center" byE.C. Douglas). A summary of the generalmodifications to device structures andinterconnect topology is presented here.

Since memory cells typically occupy 40 -to -60 percent of the active area in CMOSLSI RAM chips, cell sizes must shrink toachieve needed gains in density. The basicsix -transistor CMOS memory cell with twocross -coupled inverters and two accesstransistors is shown in Fig. 2. Implementa-tion of this cell using the RCA Metal -GateCMOS Technology (the basis of the stan-dard RCA CD4000 product series)presents an area -consuming topologicalnightmare to the integrated circuit layoutdesigner. Interconnection of the metalgates and device source/drains in the singleplane of an integrated circuit is difficult atbest. The addition of an independent inter-connect level, namely polysilicon, was used

+VDD

Fig. 2. Ideal circuit model for six -transistorCMOS memory cell.

Table I. Past and projected evolution of high density CMOS and CMOS/SOSprocesses for high density static RAMs.

Typical processMinimumRAM cell size(sq. microns)

Typicaldimension(micron)

RAMsize(K)

Metal gate 36,000 8 .25

C2L Si -gate 9,000 6 I

CMOS/SOS Si -gate 3,000 5 4

CMOS/SOS + buried contact 1,200 5 16

CMOS-I Isoplanar + buried contact 2,600 5 4

CMOS-II Si -gate 1,500** 3 16**

CMOS-II buried contact 800' 3 32"+ 2 levels poly

CMOS-II with poly loads 360 3 64"VLSI CMOS 150" 2 128**

VLSI CMOS/SOS 80** 1.5 256"

**Projected developments

only as a means of routing signals undermetal lines and resulted in a 256 -bit RAMwith a cell area of 36,000 square microns(Table I).

The self -aligned silicon -gate technologyled to the next improvement in RAMdensity. Here, poly -Si is used both as theMOS gate electrode and as an additionallevel of interconnect. The TC-1024, a I K-

devices produced using this technique. A1K -bit RAM was made with a cell area ofapproximately 9,000 square microns.Another application of the self -alignedsilicon gate technology on bulk silicon isthe closed -cell logic (C2L) technology.2

ADDRESS

0 METAL CONTACT (mc)Cs SHARED METAL

CONTACT

DATA

1/2 mc

ADDRESS

0 BURIED CONTACTS

0 SHARED METALCONTACT

Here, a closed -transistor structure wasused to improve device performance andresulted in the basic technology of the RCACD P1800 series of microprocessorproducts.'

Silicon -on -sapphire (SOS) fabricationtechniques contributed significantly tomemory development, as shown in Table I.The basic density improvement inherent inCMOS /SOS results from minimum arearequirements for device isolation, and theability to place PMOS and N MOS deviceswithout regard to a p -well, as in bulksilicon. RAM density improved by a factorof 12 over C2L RAMS because of theCMOS/ SOS technology.

VDD

1/2 mc

1/2 mc

STANDARD SOS

* METAL CONTACTS/CELL7 1/2

BURIED CONTACTS/CELL0

METAL CONTACTS/CELL

BURIED CONTACTS/CELL4

BURIED CONTACT SOSFig. 3. Comparison of standard SOS and buried -contact five -transistor static memory cell.

72 Stricker/Dingwall: Advances in CMOS static memory development

BURIED n+ POLYSILICON BURIEDCONTACT INTERCONNECT CONTACT

Fig. 4. Cross-section of burled -contact structure in SOS showing direct contactbetween polysilicon and drains of two MOS transistors.

Fig. 5. TCS-130, 16K static CMOS/SOS RAM.

rj--1 -17rj

Fig. 6. 4K static CMOS RAM with a 2600 -square -micron cell area.

Now new circuit design techniques inconjunction with a structural change in theCMOS 'SOS device have led to the firstI 6K Static RAM!' This 87,000 transistorcircuit has a cell area of 1,200 squaremicrons. Advances in circuit design tech-niques let us use a five -transistor memorycell -a one element reduction over thestandard cell of Fig. 2. The five -transistorcell, shown in Fig. 3, also makes use of a"buried contact," or direct contact betweenthe polygates and the source drain diffu-sion. The buried contacts allow completeinterconnection of the internal memory cellwithout wasting space with metal contacts.The buried contact physical structure isshown in Fig. 4 and the TCS- 130, I 6K

static CMOS/SOS RAM (a researchapplication) is shown in Fig. 5.

The buried contact approach has alsobeen applied to bulk silicon CMOS/ LSI.Isoplanar oxidation, an approach whichreplaces the junction isolation of deviceswith insulation or silicon -dioxide isolation,coupled with buried contacts, has led to a4K static CMOS RAM with a 2600 squaremicron cell areas (Fig. 6). This technology,called CMOS I, is thirteen times moredense than C2L, which is approximatelyequivalent to CMOS/SOS. Although notas dense as buried contact CMOS/ SOS,CMOS I is a relatively low-cost technologybecause sapphire -wafer substrates costmuch more than bulk -silicon substrates.

The remaining items in Table I showmemory cell areas as low as 80 squaremicrons that will support RAM designs ofup to 256K bits. More innovations indevice design will be required. For exam-ple, additional levels of polysilicon inter-connect, level -to -level buried contacts, andhigh -resistivity as well as low -resistivityloads will be needed. But clearly, staticCMOS RAM density will continue toincrease throughout the 1980s.

Future industry RAM efforts to increasedensity will rely heavily on shorterchannels and tighter designs. The RCACMOS-II process with three -microndesign rules and even more difficult VLSICMOS processes with design rules of two -micron or less are projected in Table I, toallow up to 256K RA Ms on a single chip.

Memory circuit designParasitic capacitance is the major factorcontrolling the access time of MOSsemiconductor memory. As the size ofMOS memories has increased, internalparasitic capacitance has also increasedbecause larger numbers of cells now share


the common sense lines. Although thiseffect is somewhat offset by the use ofsmaller cells, the net result would have beendistinctly slower memory chips without theinnovative memory circuit developmentswhich accompanied the IC processdevelopments.

Table II summarizes recent trends inaccess time for CMOS/ SOS RAMdesigns. Access time has decreased up to anorder of magnitude in the past years, whilememory capacity has increased 64 times.Increased speed requires significantly moresophisticated and larger amounts ofperipheral circuitry. The net trend has beenthat the peripheral circuitry continues tooccupy a constant 40 -to -60 percent of thetotal chip area, even in the large -capacityRA Ms with small cells.

Several circuit techniques and strategieshave been employed to reduce internalcircuit delays. CMOS, SOS designs arefaster than bulk CMOS designs. Withshorter channels and finer geometry, newMOS transistors have been helpful, es-pecially for bulk designs, because ofreduced parasitic capacitance and higherdrive currents. Important speed gains havealso been achieved through the develop-ment of noise -rejecting regenerative senseamplifiers. Internal signals of 50 to 100 myare now sensed rather than full logic swingsof 2.5 to 5 volts as in the earliest designs.Extremely large output drivers are routine-ly used throughout to minimize delays.Early CMOS output drivers were typically500 ohms. Modern designs now haveoutput drivers in the 20 to 50 ohm range,while critical internal nodes use 100 ohmdrivers. Finally, changes in input addresslines can be sensed and dynamic precharg-ing and lookahead. pulses can set upcritical signal propagation logic at their"toggle" points to enhance the rate at whichon -chip signals propagate.

ReferencesI. Dingwall. A.G.E. and Stricker. R.E.,"High-Density

COS MOS 1024 -Bit Static Random AccessMemory: IEEE J. Solid -State Cir.. Vol. SC -10.No. 4 (Aug. 1975).

2. Dingwall, A.G.F. and Stricker, R.E., "CL: A NewHigh -Speed High -Density Bulk CMOSFechnology," IEEE Solid -State Cir.. Vol. SC -12.No. 14. (Aug. 1977).

3. Dingwall. A.G.E. and Stricker, R.E., "A High -Speed Bulk CMOS Cl. Microprocessor: IEEE J.Solid -State Cir.. Vol. SC -I2. No. 5 (Oct. 1977).

Table II. Trends in speed performanca of RCA CMOSRAMs.'

Year Type TechnologiAccess timeVDD = VDC Size

1970 CD4061 Metal gate bulk 300ns .25K1974 TCI024 Si -gate bulk 600 I.K1976 TC 1190 200 1K1978 5114 CMOS/ SOS 450 4K1978 TCS151 CMOS/ SOS 130 4K1979 TCS 165 CMOS/ SOS 60 4K1979 TCS 130 CMOS/ SOS 120 16 K

1980 TCS24I CMOS /SOS 50 4K

TC signifies Tech Center researchchanged.

cevice. When the part goes into production, the number is

4. Dingwall, A.G.F., Stewart, R.G.. Leung. B.C. and CMOS SOS Asynchronous Static RAM. IEEE).Stricker. R.E.. "High -Density. Buried -Contact Solid State Cir., Vol. SC -I4, No. 5 (Oct. 1979).CMOS SOS Static RAMs," IEEE Electron DeviceMeeting. Washington, D.C. (Dec. 1978).

5. Dingwall. A.G.E. and Stewart. R.G . "16K

6. Stricker. R.E. and Hobrook. M., Unpublishedmanuscript (Aug. 1979).

Roger Stricker is currently the Manager ofCMOS Technology Transfer within theSolid State Technology Center where h.sprimary responsibilities include develop-ment of a new bulk CMOS LSI integratedcircuit technology and establishing newlydeveloped technologies in manufacturing inthe Solid State Division. He has worked inthe areas of CMOS device design andprocess development since joining RCALaboratories in 1973. Dr. Stricker hasauthored several papers and has received anRCA Laboratories Outstanding Achieve-ment Award for his work on reliability ofpackaged CMOS ICs.Contact him at:Solid State Technology CenterRCA LaboratoriesSomerville, N.J.TACNET: 325-6440

Andy Dingwall is a Fellow of the RCALaboratories and Leader of the TechnicalStaff in Advanced LSI Technology. He hasworked in all phases of integrated circuitdesign and process development.

Prior to joining the Solid StateTechnology Center, Dr. Dingwall worked inthe Solid State and Electron DevicesDivisions on thermoelectric generators andelectron tube devices.Contact him at:Solid State Technology CenterRCA LaboratoriesSomerville, N.J.TACNET: 325-6474

74 Stricker/Dingwall: Advances in CMOS static memory development

D.P. Bortfeld I. Gorog P.D. SouthgatelL.P. Beltz

Electro-optical techniques formeasurement and inspection

Small, state-of-the-art lasers and solid -sate optical sca,-mingarrays make possible a whole new generation of elen-o-optical measurement and inspection systems.

Abstract: The authors discuss a number ofnew techniques and some developingtechnology for electro-optical measure-ment and inspection. To date, most ofthese have been applied to problems of theRCA Picture Tube Division, but theirflexibility allows them to have wider im-pact. Current work aims to increase thespeed of these systems and to incorporatethem in on-line process control. Oneexample of this is hand -eye coordinationfor industrial robots, a fast -emerging fieldin manufacturing research.

IntroductionIn response to consumer demands forhigher quality in the products they buy,manufacturers have instituted more andbetter in -process -control systems. Butthese systems cannot be allowed todecrease productivity if the manufacturerwishes to remain in the marketplace. Oneanswer to this quandary is to use moreautomatic and programmable on-line in-spection and measurement systems, oftenincorporating sophisticated electro-opticaltechnology.'

The use of optical methods in theproduction environment is by no meansnew; visual inspection, for example,abounds. But the pressure for increasedspeed and accuracy has driven us to exploitnon -contact, flexible, optics -based tech-niques in new ways. Recently, inexpensive,reliable, small lasers and a range of solid -

Reprint RE -26-2-13Final manuscript received Aug. 12. 1980.

state sensors have made our task easier.We wish to discuss a number of electro-

optical methods which we have been in-vestigating as they relate to the needs of theRCA manufacturing divisions. Theemphasis will be mainly on applications forwhich no suitable commercial systemsexist.

We will divide our discussion ofmeasurement systems into two main areas:planar methods, in which themeasurements are made by scanning in theimage plane; and out -of -plane methods, inwhich measurements are made along theline -of -sight or optic axis of the system. Wewill also discuss exploratory work on a newinspection system which mimics an aspectof the human visual process. While we willnot discuss any Princeton work oncoherence -based optical methods, severalsuch instruments developed at the Zurichlaboratory were described in a recent RCAEngineer article.2

Planar methodsMost of our work in the planar measure-ment and inspection area has made use of alinear, self -scanning, diode -array fromEGG-Reticon. Such linear arrays comewith up to 2048 elements; we typically use512, 1024, or 1728 element scanners. Inaddition to linear arrays, matrix arrayssuch as those used in the popular "Optoma-tion" cameras from GE are also available,but with decreased linear resolution(typically 128 x 128). The dimensionalstability offered by such solid-statescanners gives them a significant advantage

over conventional vidicons which, at best,have one percent linearity. In contrast, thecombination of a high -resolution lineararray with mechanical motion in theorthogonal axis can yield accuracies ofbetter than one part per thousand.

We have built two prototype measure-ment instruments using the Reticonscanner, a device for measuring the widthsof the openings in the shadow mask and asimilar apparatus for measuring the widths

CAMERA

SWEEP MIRROR(GALVO DRIVE )

FOCUSMOTOR

FLOOD LIGHT

( AUTOMOBILEHEADLIGHT)

RETICONLINE- SCANARRAY & BOARD

SHADOWMASK

Fig 1. Schematic drawirg of the basicReticon camera system.


16

16

16

SLIT WIDTH MEASUREMENTTECHNIQUE

ROUGH DOG -BONE TEAR -DROP

SLIT SHAPE PROBLEMSFig. 2. Diagrammatic representation of theslit -width measurement system showing thescan pattern and slit -shape problems.

N.207. +0.1

E

z0 0.0

ow -0.1

f 14f IHy fi

7. 0.10 N.20E

20.05 EE dr

MASK NUMBER

Fig. 3. Results of experimental comparisonbetween visual and machine measurementsof slit width. The upper graph shows thedeviation between the average visualmeasurement and the machine data.Thevalues shown are average visual variances;machine variances are shown by bars. Thelower curve compares the variances only.

of the matrix lines on a kinescope cap. Thecamera which we used is shownschematically in Fig. 1. In addition to theline scanner, it has a focus motor which isdriven by auto -focus circuitry and agalvanometer -type scanning mirror toallow sweep in the direction perpendicularto the linear scan. Both units use backillumination provided by an automobileheadlight.

The scanning pattern on the shadow

mask is shown in Fig. 2. As the galvomirror sweeps downward, the electronicsrecognizes the end of one slit andautomatically makes measurements of theslit -width in the adjacent slit. An average offour such slit readings gives a represen-tative reading of the center mask openings.The problem with such measurements isthat the slits may suffer from a range ofmaladies such as those depicted in thebottom of the figure. These effects oftenmake an accurate comparison between amachine and a human measurementdifficult as judgments must be made in theprocess. One may legitimately questionwhat a human observer measures in such acase.

In spite of these difficulties, however,machine and human measurements canagree. In a test run, twenty 19 -inch shadowmasks were measured with a Vickerstranslated -image microscope and by theslit -width measuring device. The entire setof masks was rotated through the machine20 times and statistics were gathered.Figure 3 shows the difference between themachine and average visual readings; thebars indicate the standard deviation. Notethat an occasional difference of up to 0.1mil occurs which may result from thejudgment factor mentioned above. If onecompares the variances of the machine andof a human (bottom of Fig. 3), however, wefind them both to be about 0.03 mils,indicating similar accuracy in both cases.

The prototype for an on-line instrumentdesigned and built for measuring thewidths of matrix lines on a kinescopescreen is shown in Fig. 4. The camera islocated below the table in this case and thelight source swings out over the cap duringmeasurement ( Fig. 5). The electronics anda printer are located on the side. Inoperation, the cap is placed face -downagainst the camera. Upon removal of themask, the lamp comes forward, the cap isautomatically centered, the measurementis made and the light returns to its originalposition. The whole cycle takes about 10seconds.

A serious visual inspection problemfaced by PTD is the checking of the largeglass plates which are used to expose theshadow mask pattern. Before actual use,these plates are subjected to a detailedmicroscopic examination to search fordefects, a process which takes up to threehours. After 250 masks are exposed, theplate is checked against a negative plate tofind major defects. The entire process istime-consuming and fraught with error.We are currently testing a third systemdeveloped to automatically locate plate

defects in which a line -scan cameramechanically scans the surface of the work-ing plate, identifies potential defects andmarks the reverse side of the plate so thatthe operator need only inspect theseregions for the suspected defect. We stilldepend upon a person to categorize thedefect as to whether it is meaningless,repairable, or fatal, but this task, too, caneventually be automated.

The algorithm used by the scanner todetect a defect is described in Fig. 6. Theupper portion of the figure depicts thenegative of the shadow -mask slits. Asindicated, the region of the line scanincludes a particulate defect. The resultantdigitized video from the scanner is shownin the lower part of the figure. A simpleapproach to finding defects would be todelay the scan by one period of the maskand to compare the results with the nextscan (autocorrelation). If the pattern weretruly repetitive, this technique would allowthe adjacent area to serve as a template forthe inspected one. However, the shadowmasks made by RCA have a variableperiod or A -spacing which causes shifts inthe pattern between adjacent areas.Although the resultant offsets encounteredwithin one period are unimportant, theaccumulated error over several periodscauses a large number of erroneous defectindications, as shown schematically in thefigure.

Making the algorithm adaptive bychanging the delay to correspond to theprevious A -spacing overcomes thisproblem. To do this, the electronics alignsthe leading edges of each slit pattern asshown. Note that the particle shows uptwice in the scan, once when its region iscompared to the previous one and againwhen it is compared to the followingregion. In the actual machine, an errormust be present on two successive linearscans to define a defect.

The line -scan applications we have out-lined so far have a lot in common. Theirimplementation, however, took a signifi-cant amount of time since all the logic hadto be hard -wired. In a new approach, wehave developed a special interface boardbetween the camera proper and a micro-computer data bus. The board allows thecomputer to set digitizing thresholds, clockrates, data acquisition formats and muchmore. This results in a software -basedsystem which should be easy to modify andto program for a wide range of tasks. Itshould eventually allow anyone familiarwith the Intel microcomputers to set uptheir own inspection system tailored totheir needs.


Fig. 4. Overall view of the matrix line -width reader showing thelight source, the side -mounted electronics and the cap positioningmechanism.

Out -of -plane methods

One of the more difficult problems to solveoptically is to measure distances along theoptic axis of the system (out -of -planemeasurements). Two techniques areypically used: focus sensing and optical

Fig. 5. Clase-up view of the matrix reader showing the cap and lightsource in the reading position. The camera is mounted below thecap. Note the shadow mask ,Dri the tray above.

triangulation. One form of focus sensing isthat used in the line -scan camera describedearlier: an electronic filter isolates the high -frequency components of the video signaland a servo system moves the lens tomaximize this signal component. Thistechnique works well but it tends to be slow

ERROR

DIGITIZEDVIDEO

ADAPTIVEDELAY

Fig. 6. Timing diagrams for the adaptive logic on the working -plate scanner (see text).

and requires an area with sufficient struc-ture to produce the required high fre-quencies. However, where it can be used, itis relatively easy to implement and can bevery accurate.

Figure 7 shows an alternative form offocus sensor on which we have beenworking for some time which has thepotential of being very fast, is relativelyinsensitive to angle, and uses a small spotsize. (The spot is produced by a lasercoupled into the system via a beam splitterwhich has been left off the figure forclarity). In the original balanced state, theposition of the spot image is equidistantfrom the near and far detectors, yieldingequal outputs SN and SF respectively.Displacement of the surface by a distance xmoves the image a distance amplified by anamot.nt equal to the square of the lateralmagnification M. As a result, the signal SNincreases because more light passesthrough its aperture while SFcorrespondingly decreases. These twosignals are passed through sum anddifference amplifiers to yield thecharacteristic curves shown at the upperright. Clearly, these outputs could be usedto control a feedback loop which would

Bortfeld, et a/ Electro-optical techniques for measurement and inspection 77

keep the sensor locked at a given heightabove the surface; the resultant motioncould be measured to give a surface heightprofile of the part. For small heightvariations, the linear portion of thedifference characteristic can also becalibrated to yield a direct -readingprofilometer.

As a test of the accuracy of the focussensor, the surface of a one -inch diametersteel ball was measured. Figure 8 shows theresult of a radial scan out to about 80 milsas compared with the curve calculatedfrom the nominal ball diameter. The totalscatter of the points has a variance of ±0.1mil. The deviation of the points from thecurve beyond 60 mils results partially fromsurface tilt, which is about seven degrees atthis point. When a perfect mirror is

measured, the scatter in the data is of theorder of 50 microinches or less. Pressedsteel electron gun parts tend to exhibitfrom 0.1 to 0.2 mils due, we feel, to surfaceroughness and, possibly, speckle noise. Theresults are clearly encouraging and devel-opment is continuing to improve bothspeed and accuracy.

Another form of out -of -plane measure-ment is the technique of optical triangula-tion shown schematically in Fig. 9. A lightbeam, either from a laser or a line source, isprojected onto the surface at an angle. Theline -scan camera system views the spotnormal to the surface such that, when thesurface is moved, the camera sees a lateralmotion proportional to the line -of -sight

Sr

x

SN4- D

SF+SN

X M2%

M MAGNIFICATION

ORIGINAL SURFACE--- DISPLACED SURFACE

Fig. 7. Schematic description of the focussensor optics and electronics. The solidlines indicate the light path in the balancedstate; dotted lines correspond to a displacedsurface.

DISTANCE IN milFig. 8. Measurements (dots) of the height of a steel ball bearing as a function of radialdistance. The solid curve is the result expected on the basis of the known one -inch diameter.

displacement. This technique requires thatthe surface scatter sufficient light into thecamera to obtain a signal. A highlyreflecting, specular surface cannot bemeasured by such a system. If the surface istruly perpendicular to the camera axis andis planar over the region traversed by thelight beam, the instrument can be madedirect reading. More typically, the dis-placement signal is used to drive a servosystem as was done in the focus sensor.

An extension of the optical triangulationtechnique is optical sectioning in which"sheets" of light are used in place of thesingle light spot or line, generating a seriesof lines on the surface which, when viewednormally by a matrix array camera givesthe profile over a reasonable area veryquickly. The sharpness with which the spotor line edges can be defined determines theultimate limit to the accuracy of bothtriangulation methods.

Inspection methods

As a final example, we would like to discussan ongoing experimental program whichinvolves the inspection of shadow masksfor point defects and so-called general non -uniformities. The human eye is verysensitive to slight variations in brightness.Note your ability to distinguish subtlechanges in surface texture. As a result, all

shadow masks are subjected to a criticalvisual evaluation to eliminate those whichwould cause any objectionable variationsin picture quality. Most of us would behard pressed to find the defects whichtrained personnel routinely weed out, atleast those which they do when they arefresh and alert.

The new technique is based on resultsobtained in a multi -year investigation ofthe psychophysics of human vision at theLabs which shows that one can quantify aperson's ability to distinguish differencesbetween various displays by takinglocalized transforms of the scene, each ofwhich selects spatial frequencies lying withan octave frequency band. A non-linearresponse function is then applied to eachtransform to determine its visibility to theobserver. When properly summed, theresponse, so defined, gives a number whichuniquely describes the perceived deviationfrom uniformity.

Using the above results as a startingpoint, we are investigating a mask scannerwhich appears capable of sorting out goodfrom bad masks. As shown in Fig. 10, aseries of scans is made across the shadowmask, 25 in this case. Recorded is theshadow mask transmission as measuredthrough a Gaussian smoothing filter whicheliminates the periodic effect of the slitopenings. Were this not done, the "noise"from the individual slit openings would


SPECULARLIGHT

LINE -SCANCAMERA

INCIDENTLASERBEAM

ORIGINAL SURFACE

--DISPLACED SURFACE

F

4

Fig. 9. Schematic diagram of the optical triangulation method for height measurement.

swamp the desired overall transmissionresponse. Note that the scan for the badmask shows a mottled effect when com-pared with the rather regular nature of thepattern for the good mask.

The data are analyzed by dividing themask area into about 400 separate regionsand calculating the perceivable non -uniformity in each region. The histogramsplot the number of regions having different

r-i

degrees of non -uniformity. The histogramsare superposed on the left to emphasize thedifference between good and bad masks.The single area with very high non -uniformity on the good mask correspondsto the partially blocked aperture visible inthe middle of the scan.

When these data are properly weightedand summed, a quality factor can bedefined which is capable of distinguishing

"SMOOTHED" TRANSMISSION PROFILES

"BAD"

NON -UNIFORMITY NON -UNIFORMITY

Fig. 10. Results of scans on "good" and "bad" shadow masks. Note the blo:ked aperturenear the center of the "good" mask.

K -hGOOD"MASKS -.."BAD"MASKS

3

Ct0

a2

1.1 3

N

02

0

13V 19V 21V

'.UTOMATIC MASK CLASSIFICATION

Fig. 11. Classification of "good" and "bad"masks for three different sizes.

between good and bad masks (Fig. II).Note that the masks fall into separate"good" and "bad" groups. If thesepreliminary results hold up and means canbe found to speed up the scanning andcomputing processes, this could be asignificant new inspection technique. Itssuccess is directly relatable to the fact thatit uses an accurate model of the humanvisual decision process to define what willor will not be acceptable. This serendipitybetween the needs of manufacturing andresearch into the human visual system willhopefully yield other useful inspectiondevices in the future.

SummaryPrototype instruments have been designedand built at the Princeton Labs which useReticon line -scanners to measure thewidths of openings in a shadow mask; thewidths of lines on a matrix kinescope cap;and to inspect the working plates used inmask exposure. Techniques are beingdeveloped to measure height variations ofthe metal parts used in electron guns to anaccuracy of ±0.1 mil using auto -focus oroptical triangulation methods. An ongoingprogram applies the results of psy-cophysical investigations of human visionto the automated inspection of shadowmasks for non -uniformities in transmis-sion.

Acknowledgment

The authors would like to acknowledge thehelp of Nelson Crooks and David Fair-

Bortfeld, et al Electro-optical techniques for measurement and inspection 79

banks in various phases of the above work.In addition, thanks are due to the engineer-ing staffs at the Picture Tube Division( PTD), Lancaster, Pennsylvania, and theTechnology Transfer Laboratory for aid inthe design and testing phases of the in-struments.

ReferencesI. Two good state-of-the-art reviews are:

"Imaging Applications for Automated IndustrialInspection and Assembly, SP/E. Vol. 182 (1979).

Wick, C.. "Automatic Electro-optical Inspection."Manufacturing Engineering. pp. 64-77 (Nov. 1979).

2. Men/. W.J. and Mills. R.A.. "RCA's ZurichLaboratories." RCA Engineer. Vol. 25. No. 5, pp.25-33 (Feb. March 1980).

Dave Bortfeld has been Head, Manufac-turing Systems and Process Control since1978. Starting with RCA in 1960, he spenttwo years in the Semiconductor andMaterials Divisions. In 1967 he joined RCALabs in Zurich working on elec-troluminescence and electro-opticalapplications. After transferring to Princetonin 1974, he concentrated on electron gundesign and on gun and picture tubemanufacturing technology. In addition he isinvolved in programs on frozen foodprocessing and TV instrument design. Hehas also done R&D in lasers and non-linearoptics.Contact him at:RCA LaboratoriesPrinceton, N.J.TACN ET: 226-2515

Istvan GorogManufacturingManufacturing

has been Head of theResearch Group in the

Systems and Technology

From left, John Beltz, Dave Bortfeld, Istvan Gorog and P. David Southgate.

Research Laboratory of RCA Laboratoriessince 1970. In this capacity he is directingand carrying out research and developmentin primarily the areas of instrumentation,process control, and applied physics rele-vant to color picture tube and VideoDiscmanufacturing. Dr. Gorog joined RCALaboratories as a Member of the TechnicalStaff in 1964. His main area of interest hasbeen electro-optical systems.Contact him at:RCA LaboratoriesPrinceton, N.J.TACN ET: 226-3202

P. David Southgate joined RCA Labs,Princeton in 1966 where his interests haveincluded optical and electronic effects insemiconductors and organic materials, andpyroelectric effects and their use in thermaldetectors. Currently, he is working onvarious aspects of instrumentation and in-spection algorithms for manufacturing

technology. Prior to his association withRCA he worked on high-speed camera andoscilloscope development and on solid stateacoustics.Contact him at:RCA LaboratoriesPrinceton, N.J.TACNET: 226-2820

John Beltz joined RCA EDP Division inJune, 1958 with the optical characterrecognition group. In 1968, John joined theGraphic Systems Division and helped todevelop graphics capability on thephotocomposition system. He has been anMTS at Princeton Labs since 1977 workingon contact inspection systems and digitalcircuit design for manufacturingapplications in PTD and VideoDisc.Contact him at:RCA LaboratoriesPrinceton, N.J.TACNET: 226-2934


Patents

CommercialCommunications SystemsAbt, R.F.Pre-processing apparatus for FM stereoovershoot elimination -4207526

Abt, R.F.Pre-processing apparatus for FM stereoovershoot elimination -4207527

Bazin, L.J.1Peterson, G.R.'Schneider, D.M.Synchronizing apparatus for remote televi-sion apparatus -4214261

Dischert, R.A.lCosgrove, W.J.System for increasing the sharpness in atelevision picture -901822

Ferrie, R.G.Signal selecting system -845213

Herrmann, D.C.IBazin, L.J.Low-pass filter with remotely controllablerise time -4206474

Hopkins, R.S., Jr.Circuit for displaying characters on limitedbandwidth, raster scanned display -4212008

Orchard, L.P.Food product extrusion apparatus -4205415

Perlich, W.A.Frequency signal splitting circuit -4207532

Consumer Electronics

Giger, R.J.Surge protection of full -wave rectifier bybiased ionization -949062

Harford, J RSynchronization and gain control circuit -934822

Harford, J.R.AGC keying signal circuit -4213151

Harwood, L.A.Automatic kinescope bias control circuit -4207592

Harwood, L.A.Stabilized automatic brightness controlnetwork in a video signal processing systemincluding an automatic kinescope beamcurrent limiter -4209808

Naimpally, S.V.1Yost, T.D.Combined phase shift and filter network in acolor video signal processing systememploying dynamic flesh tone control -4207590

Parker, R.P.Gated automatic beam current limiter in avideo signal processing system -4207591

Smith, L.E.Regulated deflection circuit -4209732

GovernmentCommunications SystemsDaniel, J.W., Jr.Phaselock receiver with phaselockdetector -4213096

Nossen, E.J.Digitized phase modulating means -4206423

Nossen, E.J.Digitized phase modulating means -4206424

Nossen, E J.Digitized frequency synthesizer -4206425

Packer, MSealing composition -4214067

Packer, M.IBlack, O.D.Water soluble adhesive coating formounting components to printed wiringboards -4215025

Rauchfuss, C.G., Jr.IHerman, R.Barton, H.R., Jr.Web position controller for web transportsystems -4212422

Stakun, W.H.Testing the divergence of a beam from alaser -4212540

LaboratoriesBabcock. W.E.Switching regulator with reduced inrushcurrent -4207516

Bohringer, W.Regulated deflection circuit -4214189

Botez, C.Single filament semiconductor laser -4215319

Clemens. J.K.Recording/playback apparatus using a

single pilot tone for active tracking andcontrol of a video disc pickup device -13148

Dingwall, A.G.Circuit for limiting voltage differential indifferential amplifiers -4206418

Dingwall, A.G.1Stewart, R.G.Precharge circuit for memory array -4208730

Flory, R E.INelson, M.R.Memory addressing system for automaticsetup IV camera system -020851

Forster, G.Cathode ray tube arc -over protection -946017

Gale, M.T.Projector for reading out color -encodedfocused image holograms employing anoptimum encoding scheme -903687

Goel, J.Temperature compensation circuit -938267

Goldman, A.Aqueous photoresist of casein and N-methylol acrylamide-023391

Gorog, 1.IFirester, A.H.Optical recording with track dropcompensation -938234

Halor, B.'Hoffman, D.M.Method for making adherent pinhole freealuminum films on pyroelectric and/orpiezoelectric substrates -933603

Hawrylo, F.Z.Apparatus for the deposition of a materialfrom liquid phase -4214550

Hitch. T.T.Mercury vapor leaching from microelec-tronic substrates -4207138

Klein. N.S.Mounting for solar cell -4209347

Kleinknecht, H.P.Optical testing of a semiconductor -4211488

Kleinknecht, H.P.IBosenberg, W.A.Photomask alignment system -4211489

Kosonocky, W.F.ISauer, D.J.CCD gate electrode structures and systemsemploying the same -4211936

Levine, P.A.Reduction of sparkle noise in CCD images -42C6372

Maithies, D.L.IMehalso, R.M.Kaganowicz, G.Metallized video disc having an Insulatinglayer thereon -4206256


Miko, S.1Mullis, P.R.Magnetic switching regulator for a deflec-tion circuit -4209731

Miller, A.Waveguide method for determining stress atthe convex surface of a body -4207000

Rockett, L.R., Jr.CCD A- to -D converter -4206446

Ross, D.L.Novel ortho-quinone diazide photoresistsensitizers -4207107

Stanley, T.O.Cadence scanned flat image displaydevice -4215293

Tuska, J.W.IRobbi, A.D.Impedance measuring circuit -4206648

Upadhyayula, L.C.Exclusive OR circuit -4207476

Weimer, P.K.CCD with differently doped substrateregions beneath a common electrode -4206371

Weisbecker, J.A. I Baltzer, P.K.Color display using auxiliary memory forcolor information -4206457

Williams, R.IArie, Y.Tellurium Schottky barrier contact foramorphous silicon solar cells -4213798

Williams, R.Liquid junction Schottky barrier solar cell -4215185

Wipff, F.P.Cadence suppression sytem-4214126

Picture Tube DivisionHopen, L.F.Method for spot -knocking the electron -gunmount assembly of a CRT -4214798

Nubani, J.I.ISawicki, F.S.Wet carbon -dioxide treatment of a partially -completed CRT -4213663

"SelectaVision"Stave, F.R.VideoDisc player having record sideidentification apparatus -4206926

Torrington, L.A.Record side identification apparatus forVideoDisc player -4205853

Torrington, L.A.VideoDisc player having adjustable end -of -play switch -4211421

Solid State Division

Ahmed, A.A.Transistor saturation control -4213068

Neilson, J.M.Gate turn-off triac with dual low conductivi-ty regions contacting central gate region -4214255

Rosnowski, W.Diffusion apparatus -4211182

Rosnowski, W.Method of fabricating semiconductordevices -4213807

Schade, 0.H., Jr.Integrated circuitry including low -leakagecapacitance -4211941

Penand Podium Recent RCA technical papers and presentations

To obtain copies of papers, check your library or contact the author or his divisionalTechnical Publications Administrator (listed on back cover) for a reprint.

Astro-Electronics

E. DusioPresentation-Test software-MissionAssurance Conference, Los Angeles, CA(4/28/80)

F. GargioneComputer -aided design of welded wireboards-Astronautics & Aeronautics (April)

L. GombergIJ. StaniszewskiMission assurance & proposalpreparation-Industry/Space Div./NASAMission Assurance Conference Workshop,Los Angeles, CA (4/28/80)

A. Kidd*. AltmanIE. HutterWind sensing lidar system testing on freeflying satellites-Topical Mtg. on CoherentLaser Radar Atmospheric Sensing (9/15/80)

V. MancinoTraining & quality awareness-Conference& Workshop on Mission Assurance, LosAngeles, CA (4/28/80)

J. McClanahanRCA's steel reverberant chamber -26th An-nual Tech. Mtg. Institute EnvironmentalSciences, Phila., PA (5/11/80)

0. RegaladoSatcom finite element model-CDC/UNISTRUC Seminar, Rockville, MD(5/22/80

A. Schnapf20 years of weather satellites-where wehave been and where we are going -17thAnnual Space Congress, Coca Beach, FL(5/80)

Automated Systems

M.J. Cantellal H. HonickmanJ.D. JohnsonIJ.J. KleinIF.F. MartinInterpretation of field data for design of IRSchottky barrier array seekers (U)-JointService Guidance & Control CommitteeSymposium Institute of Defense Analysis,Arlington, VA (9/18-19/80)

J.C. PhillipsCreating winning proposals -28th AnnualTechnical Writers' Institute, Troy, NY (6/80)

Laboratories

R. CrandallTrap spectroscopy of a-Si:H diodes usingtransient current techniques-Journal ofElectronic Materials, Vol. 9, No. 4 (1980)

W.R. CurticeA MESFET model for use in the design ofGaAs integrated circuits-IEEE Tran-sactions on Microwave Theory and Tech-niques, Vol. MTT-28, No. 5 (5/80)

B. Goldstein I D.J. SzostakGrowth of thin platinum films onhydrogenated amorphous silicon and itsoxide-J. Vac. Sci. Technol., Vol. 17, No. 3(5-6/80)

L.L. JastrzobskiThe measurement of deep centers in float


zone silicon by photovoltagespectroscopy-RCA Review, Vol. 41, No. 2(6/80)

W. KernTitanium dioxide antireflection coating forsilicon solar cells by spray deposition-RCAReview, Vol. 41, No. 2 (5/80)

W. Kern IE. TracySummary abstract: Spray -on antireflectioncoatings for silicon solar cells-J. Vac. Sci.Technol., Vol. 17, No. 1 (1-2/80)

S.G. Liu lE.C. DouglasIC.P. WuC.W. MageelS.Y. NarayanIS.T. JollyF. KolondralS. JainIon implantation of sulfur and silicon ;nGaAs-RCA Review, Vol. 41, No. 2 (6/80)

V. MangulisLanchester-type equations of combat whichaccount for multiple killing hits-Operations Research, Vol. 28, No. 3, Part I(5-6/80)

D. MeyerhofferPhotosolubility of diazoquinone resists-IEEE Transactions on Electron Devices, Vol.ED -27, No. 5 (5/80)

G.H. OlsenIT.J. ZamerowskiCrystal growth and properties of binary,ternary and quaternary (In,Ga) (As,P) alloysgrown by the Hydride Vapor Phase Epitaxytechnique-Prog. Crystal Growth Charact.,Vol. 2, pp. 309-375 (1979)

J.I. PankovelC.P. Wu1C.W. MageeJ.T. McGinnLaser annealing of hydrogenatedamorphous silicon-Journal of ElectronicMaterials, Vol. 9, No. 5 (1980)

H.S. Sommers. Jr.A comprehensive model of the injection

laser: Formulation and test of the currentdependence of spontaneous and coherentemission-J. Appl. Phys., Vol. 51, No. 4(4/80)

D.L. StaeblerlC.R. WronskiOptically induced conductivity changes Indischarge -produced hydrogenatedamorphous silicon-J. Appl. Phys., Vol. 51,No. 6 (6/80)

H. Stares' L. SchiffEfficient data transfer in an SS-TDMAsystem with a non -uniform trafficdistribution-reprinted from InternationalConference on Communications, (6/80)

L.C. UpadhyayulaGaAs MESFET comparators for gigabit -rateanalog -to -digital converters-RCA Review,Vol. 41, No. 2 (6/80)

J.L. Vossen!J.J. O'Neill, Jr.IG.W. HughesF.A. TaftIR. SnedekerSource of radiation damage to MOS devicesduring S -Gun metallization-J. Vac. Sci.Technol., Vol. 17, No. 1 (1-2/80)

Laboratories, Zurich

D. Baeriswyl, et al.On the instabilities of the one-dimensionalinteracting electron gas-The Institute ofPhysics (1980)

D. Baeriswyl, et al.Phase fluctuations, disorder and nonlineari-ty in one dimension: I the linear limit-TheInstitute of Physics (1980)

H. Kiess, W. RehwaldElectric conduction in amorphouspolymers-Colloid and Polymer Science,Vol. 258, No. 3 (1980)

H. KiessiW. MeyerD. BaeriswylIG. HarbekeInvestigation on the doping ofpolyacetylene films-Journal of ElectronicMaterials. Vol. 9, No. 4 (1980)

Missile and Surface Radar

C.N. CampopianoiR.S. Berkowitz*Comparison of phase -only and con-ventional monopulse In thermal noise-RCA Review, Vol. 41, No. 2 (6/80)*Univ. of Pa., Phila.

W.C. Grubb, Jr.Mini computers and microprocessors fornon -electrical engineers and solid stateelectronics for non -electrical engineers-ASME Meeting, San Francisco, CA (8/80)

D.R. HiggsTechnology quiz -written communica-tions- TREND, Vol. 20, No. 3 (7-80)

W.J. O'LearySEASCAPE-A methodology for shipboardsparing strategy-Society of LogisticEngineers Annual Symposium, Pasadena,CA (8/80)

R.W. OttingerAEGIS technology program (U)-Tri-Services Radar Symposium, West Point, NY(7/80)

Engineering News and Highlights

Staff Announcements

Consumer ElectronicsDivisionD. Joseph Donahue, Division Vice -President, Operations, announces the ap-pointment of James R. Smith, as Director,Product Assurance.

Perry C. Olsen, Manager, Product DesignEngineering, announces the appointment ofJames J. Kopczynski as Manager, ProjectEngineering; and the appointment of RobertD. Altmanshofer as Manager, Engineering,Juarez.

Bennie L. Borman, Director, Manufacturing

Engineering and Technology, announcesthe organization of ManufacturingEngineering and Technology as follows:Edward J. Byrum, Manager, ManufacturingPrograms; Alfred Crager, Manager, TestTechnology; Robert E. Fein, Manager,Manufacturing Planning and Services;Horst E. Haslau, Manager, EquipmentDevelopment; Charles J. Limberg, Manager,Manufacturing Technology Center; andRobert R. Russo, Manager, ProcessDevelopment.

P.G. McCabe, Manager, Plant Manufac-turing Engineering, Bloomington, an-nounces the organization of Plant Manufac-turing Engineering as follows: B.J.CaughNn, Manager, Assembly Process andTool Design; J.V. Keith, Manager. Test

Engineering; R.D. Orman, Manager,Assembly Process and Tool Design; A.M.Tinsley, Manager, New Metnods and Equip-ment Development; and O.O. Watkins,Manager, Standards, Indirect Studies, andMaterial.

Laboratories

Robert D. Lohman, Director, VideoDiscSystems Research Laboratory, announcesthe appointment of Paul W. Lyons asManager, VideoDisc Testing Center.

David Richman, Director, Materials andProcessing Research Laboratory, an-nounces the appointment of Robert J. Ryanas Head, Polymer Processing Research.

83RCA Engineer 26-2 Sept./Oct. 1980

Brown F. Williams, Director, Display andEnergy Systems, Research Laboratory,announces the appointment of Thomas L.Credelle as Head, Advanced DisplaySystems Research.

Bernard Hershenov, Director, Solid StateDevices Laboratory, announces the ap-pointment of John P. Russell as Head,Optical Device Concepts Research.

RCA Service Company

Raymond J. Sokolowski, Division Vice -President, Consumer Services, announcesthe appointment of Joseph E. Steoger asDirector, Engineering Support.

Solid State Division

Carm J. Santoro, Division Vice -President,Integrated Circuits, announces theorganization of Integrated Circuits asfollows: Marvin B. Alexander, Manager, ICOperations Analyses; Larry J. French,Director, Photomask Technology; Carm J.Santoro, Acting Manager, OffshoreManufacturing; Heshmat Khajezadeh,Director, Bipolar and MOS LogicOperations; Donald W. Laird, Manager, ICAdministration & Offshore Support; John P.McCarthy, Director, Government & Hi -Reliability Operations; and Carm J. Santoro,Acting Director, Memory, Microprocessorsand Timekeeping Operations.

Heshmat Khajezadeh, Director, Bipolar andMOS Logic IC Operations, announces theorganization of the Bipolar & MOS Logic ICMarketing as follows: Andrew J. Bosso,Manager, Marketing - Industrial BipolarICs; James L. Magos, Manager, ProductMarketing - C-MOS Logic ICs; SeymourReich, Manager, Product Marketing-Consumer Bipolar ICs.

Promotions

Americom

Raymond E. Dombroskl, from AssociateMember to Member, Engineering Staff,Technical Operations.

Robert Lukach, from Associate Member toMember, Engineering Staff, TechnicalOperations.

Laboratories

Arthur L. Greenberg, from Associate MTS toMember of Technical Staff.

Louis A. DlMarco, Macy E. Heller, andJoseph Zelez, from STA to Associate MTS.

Mark D. Jacobs, from TA to SeniorTechnical Associate.

John H. Morewood, from RT to TechnicalAssociate.

Barbara J. Banko, from Managing Analyst toManager, Business Systems Development.

Ralph DeStephanis, from AssociateMember of Technical Staff to Administrator,Manufacturing Technical Programs.

Jeffrey R. Eldridge, from TechnicalAssociate to Administrator.

Morris Chazin, Anthony R. Cooke, Walter M.Janton, John A. Kopen, Jr., Henry F.Milgazo, and Donald B. Wenner, fromTechnical Associate to Senior TechnicalAssociate.

Picture Tube Division

Raymond L. Muenkel, from MemberTechnical Staff to Engineering Leader,Product Development.

RCA Service Company

Thomas J. Barry, from Manager of SystemsEngineering to Division Vice -President,Field Operations.

John M. Leopold, to Manager of RCASystems Engineering.

Professional Activities

Redfield appointed toenergy unit

Dr. David Redfield, a scientist with RCALaboratories in Princeton, has been ap-pointed to a one-year term on the SolarPhotovoltaic Energy Advisory Committee ofthe U.S. Department of Energy. The com-mittee, which includes representatives fromindustrial, academic, and professionalgroups, advises the Secretary of Energy onresearch and development projects and oneconomic, technological and environmentalconsequences of the use of solarphotovoltaic energy systems.

Dick Landers honored

Dr. Richard R. Landers has been presented a"1980 Annual Merit Award" by the ChicagoAssociation of Technological Societies.Dick, who is presently RCA Satcom ProductAssurance Administrator, was cited for hisresearch in reliability, maintainability, andavailability of complex systems (such asmine safety, missile, navigation, ocean, andspace systems) and for his pioneeringstudies in self -repairing and self-sustainingsystems.

GCS presents Technical Excellence Awards

Crowley Llsowskl

The Technical Excellence Committee atGovernment Communications Systems haspresented two awards for outstanding andinnovative accomplishments. The awardwinners and brief summaries of theircitations are given below.

A.T. Crowley-for his highly innovativework in the design and development of thedigital phase -locked -loop tracking system

of the Survival Avionics DME. Al wasresponsible for both tracking loops in thesystem, the transponder loop, and the in-terrogator measuring loop. He wrote thetrack loop section of the proposal, includinga theoretical analysis of the phase -locked -loop required to give the specified perfor-mance, designed and built the all -digitalsystem on the resulting contract and made itwork as predicted by his calculations. Thistracking system required a measuring dis-tance accuracy of 14 feet, had to use anarrowband signal compatible with stan-dard military voice radios and have a round-trip measurement time of less than onesecond. The half duplex, interrogate/trans-pond system had to measure the signalfrequency to an accuracy of 10-' andphaseto within 28 ns. In addition to meeting thesignificant technical challenge, Al beat avery optimistic program schedule by onemonth.

R.M. Lisowskl - for his outstanding work

in the design and development of the Dis-tance Measuring Equipment of the AF Sur-vival Avionics System. Bob evolved systemsconcepts for PSK/AM signal correlation to arealizable range determining system,designed and developed the control systemrequired to perform the specifiedinterrogate/transpond range measurementand peripheral functions, and was responsi-ble for integration of the DME system com-ponents, including other contractors' radioequipments, into a fully operationaldevelopmental model system. Hissuccessful completion of the system con-cept verification, breadboard anddevelopmental model stages in nine monthswas an extraordinary accomplishment.Bob's insight and creativity brought manynovel solutions to the digital implementa-tion problems to minimize the circuitry,reduce the size of custom LSI chips andrealize a package meeting the maximumsize requirement of two cubic inches.


EditorialRepresentatives

Contact your Editorial Represertative. at the extensions listedhere, to schedule technical papers and announce your professionalactivities.

' Technical Publications Administrators, responsible for reviewand approval of papers and presentations, are indicated herewith asterisks before their names.

Americom' Murray Rosenthal Princeton, New Jersey Ext 4192

Commercial CommunicationsSystems Division (CCSD)

Missile and Surface Radar Don Higgs Moorestown, New Jersey Ext. 2836Jack Friedman Moorestown. New Jersey Ext. 2112

National Broadcasting Company (NBC) Bob Mausler New York, New York Ext 4385

Patent OperationsJoseph Tripoli Princeton, New Jersey Ext. 2992

Broadcast Systems Bill Sepich Camden, New Jersey Ex: 2156 Picture Tube Division (PTD)Krishna Praba Gibbsboro, New Jersey Ex: 3605Andrew Billie Meadowlands, Pennsylvania Ex: 6231 Ed Madenford Lancaster, Pennsylvania Ext. 3657

Nick Meena Circleville, Ohio Ext. 228

Mobile Communications Systems Jack NubaniJ.R. Reec?

Scranton, PennsylvaniaMarion, Indiana

Ext. 499Ext. 5566

Meadowlands, Pennsylvania Ext. 6439or 6229 RCA Limited (Canada)Avionics Systems

Stewart Metchette Van Nuys, California Ext. 3806 Bob Mclrtyre Ste Anne de Bellevue (5'4) 457-9000

Cablevision Systems RCA Records John Ovnick Van Nuys, California Ext. 3011 Dave Devarajan Indianapolis, Indiana Ext. 6109

Consumer Electronics (CE) RCA Service Company' Clyde Hoyt Indianapolis, Indiana Ext. 5208Francis Holt Indianapolis, Indiana Ext. 5217 Joe Stecger Cherry Hill, New Jersey Ext. 5547Chuck LimbergDon Willis

Indianapolis, IndianaIndianapolis, Indiana

Ext. 5117Ext. 5883

Ray MacWilliamsDick Dombrosky

Cherry Hill, New JerseyCherry Hill, New Jersey

Ext. 5986Ext. 4414

Distributor and SpecialProducts Division (DSPD)' Charles Rearick Deptford, New Jersey Ext 2299

Globcom' Walt Leis New York, New York Ext. 7711

Research and EngineeringCorporate Engineering Hans Jenny

LaboratoriesMaucie MillerJudy Yeast

Cherry Hill, New Jersey Ext. 4251

Princeton, New Jersey Ext. 2322Somerville. New Jersey Ext. 7357

Government Systems Division (GSD) "SelectaVision" VideoDisc OperationsVv. 2IK',1,1,1 Indianapolis, Indiana Ext. 3235Astro-Electronics

Ed Goldberg Princeton, New Jersey Ext 2544 Solid State Division (SSD)Automated Systems

John Schoen Somerville. New Jersey Ext. 6467 Ken Palm Burlington, Massachusetts Ext. 3797Gene Gallagher Burlington. Massachusetts Ext. 2975 Power Devices

Government Communications Systems Harold Ronan Mountaintop, Pennsylvania Ext. 1633or 1827

' Dan Tannenbaum Camden. New Jersey Ext. 3081 Sy Silve-stein Somerville, New Jersey Ext. 6168Harry Ketcham Camden, New Jersey Ext. 3913

Integrated CircuitsGovernment Engineering Fred Foerster Somerville, New Jersey Ext. 7452 Merle Pietz Camden, New Jersey Ext. 2161 John Ycung Findlay, Ohio Ext. 307

GSD Staff Electro-Optics and Devices Ed Moore Cherry Hill, New Jersey Ext. 5833 John Grosh Lancaster, Pennsylvania Ext. 2077

RCA EngineerA technical journal published byCorporate Research and Engineering"by and for the RCA engineer"

Printed in the U.S.A. Form No. RE -26-2

rca engineer - fbcoverup.com · precise, closed -loop manufacturing systems for wafer processing....

Documents