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3. R.Ubar. Publications

PUBLICATIONSProf. Raimund Ubar,Tallinn Technical University,

Raja tee 15, Tallinn 12618, EstoniaTel. (+372) 620 22 52FAX (+37) 620 22 53E-mail: [email protected]

Books:1. A. Seleznev, B. Dobriza, R. Ubar. Design of Automatic Test Equipments.

Mashinostrojenie, Moscow, USSR, 1983, 224 pp., (in Russian).2. D. Bochmann, R. Ubar. Fehler in Automaten. VEB Verlag Technik, Berlin, 1989, 216

p.Booklets:3. R.Ubar. Functional blocks in Digital Computers. Tallinn Technical University, 1978,

103p. (in Estonian)4. R.Ubar. Diagnosis of Digital Devices. I. Tallinn Techn. University, 1980, 114 pp. (in

Russian). 5. R.Ubar. Diagnosis of Digital Devices. II. Tallinn Techn. University, 1981, 112 pp. (in

Russian). 6. P.Kitsnik, T.Lohuaru, R.Ubar. Test Design System for Digital Automata. Tallinn

Techn. University, 1984, 58p. (in Russian)7. R.Ubar. Operational Automata in Digital Computers. Tallinn Technical University,

1987, 96 p. (in Estonian).8. R. Ubar. Design of Digital Systems for Testability. Tallinn Technical University,

1988, 68 pp. (in Russian). Patents in USSR:9. T. Lohuaru and R.Ubar. Equipment for Testing LSI. A.C. No.1218390, Inf. Bulletin

No.10, 1986. 10. T.Evartson, R.Ubar, A.Viilup. Equipment for Testing Synchronized digital circuits.

A.C. No.3772884/24, Inf. Bulletin No.25, 1986. 11. T.Evartson, H.Haak, T.Lohuaru, R.Ubar. Equipment for Fault Localization in Digital

Objects. A.C. No.3984709/24, Inf. Bulletin No.19, 1987. 12. T.Lohuaru, M.Mannisalu, P.Pukk, R.Ubar, E.Vanamölder. Equipment for testing

VLSI. A.C. No. SU 1652976 A1, Inf. Bulletin No.20, 1991. Papers:196813. R.Ubar. About Minimization of the Test Length for Complex Technical Systems. Proc. of

the All-Union Conference “Applications of the Information Theory”, Moscow, 1968 (in Russian).

197014. R.Ubar. About a Scheduling Task in Time Domain. Proceedings of Tallinn Technical

University, No 291, 1970 (in Russian).197115. R. Ubar. About Selection of Test Points. Automatics and Computer Engineering.

Avtomatica i Vychislitel’naja Tekhnika, Vol.5, No.3, 1971, pp.28-32, (in Russian).

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16. V. Maslennikow, R.Ubar. Using Monte-Carlo Method for Optimization of Test Processes. Proceedings of Bauman Technical University, No.148, 1971, Moscow, (in Russian).

17. V. Maslennikow, R.Ubar. Minimization of Average Time of Fault Detection Processes in Technical Devices. Proceedings of Bauman Technical University of Moscow, No.148, 1971, Moscow, (in Russian).

18. R.Ubar. Choice of Controlled Parameters. Plenum Publishing Corporation. Automation and Computer Engineering, 1971, USA, pp. 27-31.

197219. R.Ubar. Algorithm for optimization of test programs for complex technical systems. 2nd

Conference of Universities “Developments in Technical Cybernetics”. Moscow, 30. Mai – 2. June, 1972, pp.126.

197320. U.Heiter, R.Ubar, A.Viilup. Diagnosis of Multiple Faults in Combinational Circuits.

Proceedings of Tallinn Techn. University, No.350, 1973, Tallinn, (in Russian). 21. B.Dobritza, R.Ubar. Synthesis of Test Procedures for Complex Technical Objects.

Journal of Bauman Technical University of Moscow, No.162, 1973, Moscow, (in Russian), p.13-19.

197622. R.Ubar. Equivalent Transformations of Diagnostic Dictionaries. Journal of Bauman

Technical University of Moscow, No.210, 1976, Moscow, (in Russian), pp.4-7.23. R.Ubar. Test Generation for Digital Circuits with Alternative Graphs. Proceedings of

Tallinn Technical University, No.409, 1976, Tallinn, pp.75-81 (in Russian). 24. R.Ubar. About General Definition of the Diagnosis Problem for Digital Circuits.

Proceedings of Tallinn Technical University, No.409, 1976, Tallinn, pp.69-73 (in Russian).

25. R.Ubar. Ein Deductives Verfahren zur Testsatzanalyse für digitale Schaltungen. Proc. of Ingenieurhochschule Dresden No.1, 1976, Dresden, p.2-11.

26. R.Ubar. Über einige Probleme der Testsatzanalyse für digitale Systeme. Proceedings of Technical University Dresden, No.3, 1976, Dresden.

27. P.Kitsnik, R.Ubar, Aviilup. Simulating System for Minicomputer Diagnostic Programs. Preprints of IFAC/IFIP 1st Int. Symp., Tallinn, August, 1976, pp.115-117.

28. R.Ubar. Berechnung von Tests für die Fehlerdiagnose in digitalen Systemen. Proc. of 21. Int. Wiss. Koll., Technical University of Ilmenau, October, 1976, pp.33-35.

197729. R.Ubar. Analysis of Diagnostic Tests for Combinational Circuits by the Method of

Fault Backtracing. Automatics and Telemechanics, No.8, 1977, Moscow, pp.168-176 (in Russian).

30. P.Kitsnik, R.Ubar, A.Viilup. Deductive Fault Analysis in Synchronized Digital Devices without Global Feedbacks. Proc. of the All-Union Conf. on CAD of Computers, Kaunas, June, 1977, pp.178-181 (in Russian).

31. M.Plakk, R.Ubar. Using Alternative Graphs in Test Synthesis for Combinational Circuits. Proc. of Tallinn Techn. University, No.432, 1977, Tallinn, pp.3-13 (in Russian).

32. P.Kitsnik, R.Ubar. Formulas for Deductive Analysis of Tests for Synchronized Digital Devices. Proc. of Tallinn Technical University, No.432, 1977, Tallinn, pp.15-23 (in Russian).

33. P.Kitsnik, R.Ubar, A.Viilup. Deductive Test Analysis Method for Logic Devices. Proc. of Technical Diagnosis Conference, Rostow-at-Don, May, 1977, pp.46-51 (in Russian).

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34. R.Ubar. Deductive Fault Analysis in Sequential Circuits. Proc. of Int. Conference on Technical Diagnostics, Praha, Czechoslovakia, 1977, pp.189-192 (in Russian).

35. R.Ubar. Berechnung von Boole'schen Ableitungen bei der Testsatzanalyse für digitale Schaltungen. Nachrichtentechnik/Elektronik, 1977, H.1, S.21-23. Nachrichtentechnik/Elektronik, 1977, H.4, S.149-150.

36. R.Ubar. Über einige Probleme der Testsatzanalyse für digitale Systeme.37. R.Ubar. Multiple Fault Analysis in Logic Circuits. Proc. of the IFAC Symposium on

Discrete Systems, Dresden, 1977, Band 4, pp.48-57.38. T.Lohuaru, R.Ubar, A.Viilup. Fault Localization in Digital Circuits with Automatic

Test Equipments. Proc. of Tallinn Technical University, No.432, 1977, Tallinn, pp.37-45 (in Russian).

197839. R.Ubar. A Decomposition Method of Fault Diagnosis in Combinational Circuits.

Proc.of Tallinn Technical University, No.457, 1978, Tallinn, pp.3-22 (in Russian).40. R.Ubar. Module Level Fault Diagnosis in Combinational Networks. Proc. of the 1st

Conference on Fault-Tolerant Systems and Diagnostics, Gdansk, Poland, 1978, pp.297-314.

41. R.Ubar). Analysis of Diagnostic Tests for Combinational Circuits by Method of Backtracking of Faults. Automation and Remote Control, Vol.40, No.11, part 2, Nov. 1978. Plenum Publishing Corporation, USA, pp. 1254-1260.

42. B.T.Dobritsa, R.Ubar. Test generation for Multiple Faults in Combinational Circuits. Proceedings of Bauman Technical University Moscow, No 270, 1978, pp.6-10. (in Russian)

197943. R.Ubar. Description of Digital Devices by Alternative Graphs. Proc. of Tallinn

Technical University, No.474, 1979, Tallinn, pp.11-33 (in Russian).44. M.Plakk, R.Ubar. Synthesis of Test Pairs for Combinational Circuits. Proceedings of

Tallinn Technical University, No.474, 1979, Tallinn, pp.45-68 (in Russian).45. M.Plakk and R.Ubar. Aufstellung von Testfolgen für logische Schaltungen. Proc. of

The 24th International Conference, Technical University of Ilmenau, October, 1979, H.2, pp.93-96.

46. M.Pall and R.Ubar. Computer-Aided Module-Level Test Generation for Digital Devices on the Basis of their Alternative-Graph Model. Preprints of IFAC/IFIP 2nd Int. Symposium, Prague, Czechoslovakia, 1979, v.1, pp. C-XIII-1-4.

47. R. Ubar. Alternative Graphs and Test Generation for Digital Systems. Proc. of the 2nd Conf. on Fault-Tolerant Systems and Diagnostics, Brno, Czechoslovakia, 1979, pp.177-184.

48. R.Ubar. Fault Diagnosis in Combinational Circuits by Solving Boolean Differential Equations. Automatics and Telemechanics, No.11, 1979, Moscow, pp.170-183 (in Russian).

49. K.Grigorjeva and R.Ubar. Fault Diagnosis in Sequential Circuits. Proc. of Tallinn Technical University, No.474, 1979, Tallinn, pp.35-44 (in Russian).

50. R. Ubar. Diagnosis of Combinational Circuits in the Extended Class of Faults. Proc. of the Conference on CAD of Electronic Equipments, Vilnius, June, 1979, pp.177-180 (in Russian).

51. T.Lohuaru, R.Ubar, A.Viilup. Minicomputer Software for Fault Localization Control in Digital Circuits. Preprints of IFAC/IFIP 2nd Int. Symposium, Prague, Czechoslovakia, 1979, v.1, pp. P-XIV-1-4.

1980

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52. R. Ubar. Fault Specification in Digital Devices. Proc. of Tallinn Technical University, No.497, 1980, Tallinn, pp.3-9 (in Russian).

53. R.Ubar. Desription of Computers by Vector Alternative Graphs for Diagnostic Microprogram Synthesis. Proc. of Tallinn Technical University, No.497, 1980, Tallinn, pp.11-20 (in Russian).

54. M.Plakk and R.Ubar. Test Generation for Digital Circuits by Alternative Graphs. Automatics and Telemechanics, No.5, 1980, Moscow, pp.152-163 (in Russian).

55. R.Ubar. Fault Localization in Digital Circuits in the Dialogue Mode. Proc. of Technical Diagnosis Conference, Rostow-at-Don, May, 1980, pp.76-85 (in Russian).

56. R. Ubar. Test Simulation for Digital Devices on the Alternative-Graph-Model. Proc. of the 3rd Conf. on Fault-Tolerant Systems and Diagnostics, Katowice, Poland, 1980.

57. R.Ubar. Beschreibung Digitaler Einrichtungen mit Alternativen Graphen für die Fehlerdiagnose. Nachrichtentechnik/Elektronik, (30) 1980, H.3, pp.96-102.

58. M.Plakk, R.Ubar. Digital Circuit Test Design using the Alternative Graph Model. Automation and Remote Control, Vol.41, No 5, part 2, Nov. 1980, Plenum Publishing Corporation, USA, pp. 714-722.

59. R.Ubar. Detection of Suspected Faults in Combinational Circuits by Solving Boolean Differential Equations Automation and Remote Control, Vol.40, No 11, part 2, Nov. 1980, Plenum Publishing Corporation, USA, pp. 1693-1703.

60. E.Kivi, R.Ubar. Synthesis of Test Groups for Digital Circuits on Alternative GraphsXXXI Student Papers, TTU, Tallinn, 1980, pp.52-55 (in Russian).

61. T.Toome, R.Ubar. Control of Fault Localization in Digital Circuits. XXXI Student Papers, TTU, Tallinn, 1980, pp.55-57 (in Russian).

62. E.Kivi, R.Ubar. Synthesis of Functional Alternative Graphs for Digital Circuits. Proceedings of the Conference on Radio Broadcasting, Tallinn, 1980, pp.23-24 (in Russian).

63. R.Ubar. Multivalued Simulation of Digital Circuits on Alternative Graphs Proceedings of the Conference on Radio Broadcasting, Tallinn, 1980, pp.25-26 (in Russian).

198164. R.Ubar. Vektorielle Alternative Graphen und Fehlerdiagnose für digitale Systeme.

Nachrichtentechnik/Elektronik, (31) 1981, H.1, pp.25-29.65. T.Evartson, R.Ubar. Optimization of Fault Localization Procedures in Digital Systems.

Proceedings of the All-Union Conference on CAD of Computers, Kaunas, June,1981, pp.175-184 (in Russian).

198266. R.Ubar. Generation of Complete Tests for Combinational Circuits. Journal of Academy

of Sciences of Estonia, Vol.31, Phys.& Math., 1982, No.4, pp.418-427 (in Russian).67. A.Toomsalu, R.Ubar. Data Generation In Test Development for Microprocessors.

Proc. of Tallinn Technical University, No.530, 1982, Tallinn, pp.63-73 (in Russian).68. M.Pall, R.Ubar, A.Voolaine. General Approach to Multi-Valued Simulation of Digital

Circuits on Alternative Graphs. Proc. of Tallinn Technical University, No.530, 1982, Tallinn, pp.23-38 (in Russian).

69. E.Thoma, R.Ubar. Optimierte Steuerung der Fehlersuche auf digitalen Leiterplatten. Proc. of the 27th International Conference, Technical University of Ilmenau, October, 1982, H.3, pp.65-68.

70. R.Ubar. Reducing the Combinatorial Complexity in Test Generation for Digital Automata. Proc. of Tallinn Techn. University, No.550, 1982, Tallinn, pp.111-119 (in Russian).

1983

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71. R.Ubar. General Model of Alternative Graphs for Test Generation in Digital Systems. Proc. of Tallinn Technical University, No.550, 1983, Tallinn, pp.97-109 (in Russian).

72. R.Ubar. Test Pattern Generation for Microprocessor Systems on the Alternative Graph Model. Proc. of the 3rd Symp. of the IMEKO Techn. Committee on Technical Diagnostics. Moscow, 1983, pp.403-410.

73. R.Ubar. Test Generation for Digital Systems on the Vector Alternative Graph Model. Proc. of the 13th Annual Int. Symp. on Fault Tolerant Computing, Milano, Italy, 1983, pp.374-377.

74. R. Ubar. Test Generation for Microprocessors. Proc. of the 6th Conf. on Fault-Tolerant Systems and Diagnostics, Brno, Czechoslovakia, 1983, pp.209-215.

75. T.Lohuaru, M.Pall, R.Ubar. Automated Test Synthesis for Fault Diagnosis in Digital Devices. Journal of Academy of Sciences of Estonia, Vol.32, Phys.& Math., 1983, No.1, pp.84-94 (in Russian)

76. R.Ubar. About Synthesis of Full Test Set for Microprocessor Systems. Proceedings of the Conference of the Day of Radio. Section “Microproceesor Technology”, Tallinn, 1983, pp.16-20 (in Russian)

198477. R.Ubar. General Approach to Test Synthesis for Digital Circuits and Systems. Proc. of

the 10th All-Union Workshop on Technical Diagnostics, Tallinn, Oct., 1984, pp.75-81. (in Russian).

78. R.Ubar. Optimization of Fault Search Processes in Digital Devices. Journal of Applied Automata Theory, Humboldt University, Berlin, 1984, pp.71-106 (in Russian).

79. T.Evartson, R.Ubar, A.Viilup. Fault Localization Control in Digital Circuits with Counters. Proc. of the 10th All-Union Workshop on Technical Diagnostics, Tallinn, Oct.,1984, pp.28-32 (in Russian).

80. R. Ubar. Computer-Aided Test Generation for Digital Circuits on the Model of Alternative Graphs. Proc. of Technical Diagnosis Conference, Rostow-at-Don, May, 1984, pp.120-127 (in Russian).

198581. T. Evartson and R.Ubar. About Simulation of Long Input Sequences for Digital circuits

with Counter Structures. Proc. of Tallinn Techn. University, No.601, 1985, Tallinn, pp.61-74 (in Russian).

82. R. Ubar. Using Alternative Graphs for Automatization of Test Program Synthesis for Microprocessor LSI. Electronic Techniques Ser.8, 1985, Vol.5 (116), Moscow, pp.110-113.

83. R. Ubar. Generation of Universal Tests for Digital Devices by Alternative Graphs. Proc. of Tallinn Techn. University, No.601, 1985, Tallinn, pp.51-60 (in Russian).

84. T.Lorenz, G.Knospe, R.Ubar. Testverfahren ftr Assembler-Programme. Proceedings of The Ingenieurhochschule Wismar, No4, 1985, s.8-19 (in German).

198685. T.Lohuaru, R.Ubar, T.Evartson. General Approach to Solving Diagnosis Tasks for

Digital Systems. Proc. of the 9th All-Union Symposion on Redundancy in Information Systems, Leningrad, May, 1986, pp.32-35 (in Russian).

86. R.Ubar. Research and Development of Testing Methods for Digital Systems Thesis of Dr.Sc. Dissertation, Riga, 1986, 43 pp. (in Russian).

87. R.Ubar. Research and Development of Testing Methods for Digital Systems Dr.Sc. Dissertation, Riga, 1986, Part 1. 337 p. (in Russian).

88. R.Ubar. Research and Development of Testing Methods for Digital Systems Dr.Sc. Dissertation, Riga, 1986, Part 2. 168 p. (in Russian).

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89. R.Ubar. Description of Microprocessor LSI by Alternative Graphs. Proc. of Technical Diagnosis Conference, Rostow-at-Don, USSR, May, 1986, pp.24-30 (in Russian).

90. R.Ubar. Methods of Testing Digital Systems. Proc. of Tallinn Technical University, No.626, 1986, Tallinn, pp.61-73 (in Russian).

198791. T.Lohuaru, R.Ubar. About Test Synthesis for Microprocessor VLSI. Journal of Design

and Diagnostics of Computers, Institute of Cybernetics, Tallinn, 1987, pp.30-42 (in Russian).

92. R.Ubar. Test Generation for Microprocessor Control Mechanisms. Proc. of the 10th Conf. on Fault-Tolerant Systems and Diagnostics, Varna, Bulgaria, September, 1987, pp. 305-311.

93. R.Ubar. About the History of Research in Diagnostics of Computers in Estonia. Proc. of TTU, No 678, 1988, pp.110-127 (in Estonian).

198894. R.Ubar. Test Generation for Microprocessors on Alternative Graphs. Proc. The 33rd

Int. Conference, Technical University of Ilmenau, October, 1988, pp.11-14 (in German).

95. T.Lohuaru, R.Ubar. Description of Digital Objects with Alternative Graphs for Test Generation Purposes. Proc. of the 11th Conf. on Fault-Tolerant Systems and Diagnostics, Suhl, May 1988, pp.157-163.

96. V.Alango, T.Kont, R.Ubar. Test Program Compilation in Automated Test Generation for Microprocessors. Proc. of Tallinn Technical University, No.674, 1988, Tallinn, pp.78-87 (in Russian).

97. G.Elst, T.Lohuaru, B.Straube, R.Ubar. Test Generation for Data Parts in Digital Systems. Proc. of Tallinn Technical University, No.674,1988, Tallinn, pp.65-77 (in Russian).

98. R.Ubar. Alternative Graphs and Technical Diagnosis of Digital Devices. Electronic Techniques, Vol.8, No.5 (132),1988, Moscow, pp.33-57 (in Russian).

99. V.Grigorenko, T.Lohuaru, R.Raud, R.Ubar). Integrated CAD of Testable Digital Systems for PCsProc. of. 5th International Workshop on Automation and Scientific Instrumentation (ASI’88), Varna, October 11-21, 1988, pp. 250-256 (in Russian).

100. R.Ubar. About the History of Research on Testing of Computers in Estonia. Proceedings of TTU No 678, Tallinn, 1988, pp.110-127 (in Estonian).

1989101. R.Ubar. Functional Level Test Set Generation Methods. Invited paper. Proc. of the 12th

Conf. on Fault-Tolerant Systems and Diagnostics, Prague, Sept.,1989, pp.46-55.102. R.Ubar, A.Voolaine. Multi-Valued Simulation on the Alternative Graph Model of

Digital Devices. Proc. of the 12th Conf. on Fault-Tolerant Systems and Diagnostics, Prague, Czechoslovakia, September, 1989, pp.101-104.

103. A.Toomsalu, R.Ubar, V.Zaugarow. Generation of Test Experiments for Digital Devices. Proc. of the 9th Int. Conf., Mittweida, Germany, September, 1989, pp.46-54.

104. V.Alango, T.Kont, R.Ubar. Automatic Test Program Generation System for Digital Systems. Proc. of the 1st Int. Conf.on CAD of Digital Systems, Leningrad, 1989, pp.23-31 (in Russian).

105. R.Ubar. Probabilistic Testing Digital Circuits using Alternative Graphs. Proc. of Tallinn Technical University, No.696, 1989, Tallinn, pp.89-96 (in Russian).

106. R.Ubar. Functional Specification and Testing of Digital Systems. Proc. of the 3rd Symp Multimicroprocessor Systems Vol.1, Stralsund, Germany, October, 1989, pp.207-217.

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107. R.Ubar, T.Lohuaru). Ein universeller Weg zur Automatisierung des Testentwurfs für digitale Objekte. In “Fehler in Automaten” von D. Bochmann und R. Ubar, VEB Verlag Technik Berlin, 1989. S. 16-30.

1990108. T.Lohuaru, M.Mannisalu, P.Pukk, R.Ubar, E.Vanamolder. Test System for Fault

Detection and Diagnosis in Microprocessor Control Devices. Proc. of Tallinn Technical University, No.708, 1990, Tallinn, pp.70-84.

109. V.Alango, T.Kont, R.Ubar. New Test Design Techniques for Fault Detection in Digital Objects. Proc. of Tallinn Technical University, No. 708, 1990, Tallinn, pp.52-69.

110. K.Kuchcinski, Z.Peng, R.Ubar. Test Generation for Digital Systems at Functional Level. Research Report LiTH-IDA-R-90-06, Linkoping University, Sweden, 1990, 21 p.

111. R.Ubar. An approach to develop intelligent digital test systems. Periodica Polytechnica Ser. Electrical Engineering, Vol.34, No.4, Budapest, 1990, pp.233-244.

1991112. R.Ubar. Digital test design based on alternative graphs. Proc. of the 2nd European

Design Automation Conference, Amsterdam, February 25-28, 1991.113. R.Ubar, K.Kuchcinski, Z.Peng. Test generation of digital systems at functional level.

The 2nd European Test Conference, Munich, Germany, April 10-12, 1991. 114. R.Ubar. New test design techniques for fault detection in digital devices. Proc. of the

Int. Design Automation Conference APK'91, Kaunas, June, 1991115. T.Lohuaru, R.Ubar. A set of tools for diagnosis of digital devices. PC World,

Information Computer Enterprise, Moscow, No1, 1991, pp.122-125 (in Russian).116. R.Ubar. Fault simulation in digital systems using alternative graphs. 36. Int. Wiss.

Koll., TH Ilmenau, Oct. 21-24 1991. pp.737-742.117. R.Ubar. Test generation for ASICs. The 1st Finnish-Estonian Workshop on Digital

Circuits and Algorithms, Tallinn, Estonia, March 18-20, 1991.118. R.Ubar. Digital test design based on alternative graphs. The 1st Finnish-Estonian

Workshop on Digital Circuits and Algorithms, Tallinn, Estonia, March 18-20,1991.1992119. R.Ubar. Alternative graphs and test pattern design in digital systems. Proc. of the 6th

Workshop on new directions for testing, Montreal, Canada, May 20-22, 1992.120. R.Ubar. Multi-Level Test Generation and Fault Diagnosis in Digital Systems. Research

Report, TIM3/IMAG/INPG, France, 1992, 88 p.121. R.Ubar, K.Kuchinski. Functional Level Controllability Analysis for Digital Circuits

Proc. of Design Automation Conference, Kaunas, June 1-4, 1992, pp.13-21.122. R.Ubar. Diagnostic Software for Systems. In "Concise Encyclopedia of Software

Engineering" Pergamon Press,1992, pp.101-106.123. R.Ubar. Testing of systems using software. In "Concise Encyclopedia of Software

Engineering" Pergamon Press,1 992, pp.354-357.124. R.Ubar. CAD für Digitaltechnik - Eine Programmfamilie für den Entwurf von

Testmustern zum Test von Digitalschaltungen. IBM Hochschulkongress'92. Offene Grenzen - offene Systeme. Dresden 1992, S. IV9 1-14.

125. R.Ubar, K.Kuchcinski. Algorithms of Functional Level Testability Analysis for Digital Circuits. Periodica Polytechnica Ser. El. Eng., Vol.36, No.3-4, Budapest, 1992, pp.295-308.

126. R.Ubar. Functional Level Testability Analysis for Digital Circuits. Research Report LiTH-IDA-R-92-03, Linkoping University, Sweden, 1992, pp.16.

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1993 127. R.Ubar, J.Dushina, V.Zaugarov, E.Krupnova, S.Storozhev. FTGEN - A System for

Functional Test Generation Proceedings of CAD-93: New Information Technologies for Science, Education and Business. Yalta May 4-13, 1993, pp.123-125 (in Russian).

128. R.Ubar, K.Kuchcinski. Functional Level Testability Analysis for Digital Circuits. Proc. of European Test Conference ETC'93, Rotterdam, April 19-22, 1993, pp.545-546.

129. R.Ubar, J.Dushina,V.Zaugarov, E.Krupnova, S.Storozhev.Test Generation System for Microprocessors. Proc. of Int. Conf. "Technical Diagnostics-93", St.-Peterburg, June 8-10, 1993, pp.87-89 (in Russian).

130. R.Ubar,V.Tulit, A.Buldas, M.Saarepera. Laboratory Course for Training "Digital Design and Test". Proc.of IV EUROCHIP Workshop on VLSI Design Training, Toledo, Sept.30-Oct.2, pp. 112-117, 1993.

131. R.Ubar, V.Tulit, A.Buldas, M.Saarepera. TURBO TESTER. A Set of Software Tools for CAD of Test for Digital Circuits. Proc.of IV EUROCHIP Workshop on VLSI Design Training, Toledo, Sept.30-Oct.2, pp. 396, 1993.

132. R.Ubar. Alternative Graph Based Test Design in Digital Systems. Invited paper. Proc. of the 11. NORCHIP Seminar, Trondheim (Norway), Nov. 9-10, pp.48-62, 1993.

1994 133. R.Ubar,J.Dushina, H.Krupnova, S.Storozhev, V.Zaugarov. Functional Test Program

Generation for Digital Systems. Proc. of the 6. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", Vaals (Niederlande), March 6-8, pp. 14-18, 1994.

134. R.Ubar. Book review Boundary-Scan Test. By H.Bleeker, P.Van Den Eijnden and F.De Jong. Kluwer Academic, Boston (1993). 225 pp. In Engineering applications of Artificial Intelligence. Pergamon Press Ltd. 1994.

135. R.Ubar. Test Generation for Digital Systems Based on Alternative Graphs Theory. Lecture Notes in Computer Science No 852. Dependable Computing - EDCC-1. Springer-Verlag, 1994, pp.151-164.

136. R.Ubar. Parallel Critical Path Tracing Fault Simulation Proc. of the 39. Int. Wiss. Kolloquium. Ilmenau (Germany), Sept. 27-30, 1994. Band 1, pp. 399-404.

137. R.Ubar. Fault Diagnosis of VLSI Devices Using Alternative Graph Representation. Proc. of The 8th Symposium on Microcomputer and Microprocessor Applications. Budapest, October 12-14, 1994, Volume I, pp.34-44.

138. R.Ubar, A.Buldas, P.Paomets, J.Raik, V.Tulit. A PC-based CAD System for Training Digital Test. Proc. 5th EUROCHIP Workshop on VLSI Design Training. Dresden, October 17-19, 1994, pp.152-157.

139. R.Ubar. Alternative Graphs as a Mathematical Tool and Knowledge Representation for Diagnosis Purposes in Digital Systems. Proc. 4th Biennial Baltic Electronics Conference. Tallinn, October 9-14, 1994.

140. H.Krupnova, R.Ubar. Constraints Analysis in Hierarchical Test Generation for Digital Systems. Proc. 4th Biennial Baltic Electronics Conference. Tallinn, October 9-14, 1994.

141. M.Brik, R.Ubar. Hierarchical Test Generation for Finite State Machines. Proc. 4th Biennial Baltic Electronics Conference. Tallinn, October 9-14, 1994.

142. J.Raik, P.Paomets, E.Ivask, R.Ubar. A CAD System for Teaching Digital Test. Proc. 4th Biennial Baltic Electronics Conference. Tallinn, October 9-14, 1994.

143. R.Ubar, K.Vainomaa. Electronics Competence Centre at the Tallinn Technical University. Proc. 4th Biennial Baltic Electronics Conference. Tallinn, October 9-14, 1994.

1995

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144. M.Glesner, T.Hollstein, B.Courtois, P.Amblard, R.Ubar, K.Vainomaa. New Curricula and a Competence Centre through TEMPUS at the Technical University of Tallinn. Proc. EC Workshop on Design Methodologies for Microelectronics, Smolenice, 1995, pp. 347-353.

145. R.Ubar. Hierarchical Test Generation Based on Alternative Graph Model. Proc. of 2nd Workshop on Hierarchical Test Generation, Duisburg, 1995.

146. R.Ubar. Case Study in Testing Digital Systems. Invited paper. Baltic Electronics, Vol. 1, No. 1, Sept. 1995, pp.24-27.

147. R.Ubar. Fault Diagnosis in Digital Devices. Proceedings of the Estonian Academy of Sciences, Engineering, 1995, No. 1/1, pp.51-67.

148. R.Ubar. Electronics Competence Centre as a Result of European Projects at the Technical University of Tallinn. Baltic Electronics, Vol. 1, No. 2, Dec., 1995, pp.9-11.

149. R.Ubar. Hierarchical Test Synthesis for Digital Systems Using Alternative Graph Model. Dagstuhl-Seminar-Report 132, ISSN 0940-1121. Schloss Dagstuhl, 1995, pp.14-15.

1996150. M.Ajaots, M.Min, T.Rang, R.Ubar. Education Environment for Electronics and

Microsystems. Proc. of the First European Workshop on Microelectronics Education. Villard de Lans, France, February 5-6, 1996, p.39.

151. R.Ubar, P.Paomets, J.Raik. Low-Cost CAD Software for Teaching Digital Test. Proc. of the First European Workshop on Microelectronics Education. Villard de Lans, France, February 5-6, 1996, p.48.

152. R.Ubar. Test Synthesis with Alternative Graphs. IEEE Design and Test of Computers. Spring, 1996, pp.48-59.

153. G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Teaching Test and Design for Testability with TURBO-TESTER Software. Proc. of the 3rd Workshop on Mixed Design of Integrated Circuits and Systems, Lodz, May 1996, pp. 589-594.

154. R.Ubar. Combining Symbolic Techniques with Topological Approach in Test Generation. Proc. of the 3rd Workshop on Mixed Design of Integrated Circuits and Systems, Lodz, May 1996, pp. 377-382.

155. R.Ubar, M.Brik. Multi-Level Test Generation and Fault Diagnosis for Finite State Machines. Lecture Notes in Computer Science No 1150. Dependable Computing - EDCC-2. Springer-Verlag, 1996, pp.264-281.

156. M.Ajaots, M.Min, T.Rang, R.Ubar. Education Environment for Electronics and Microsystems. Microelectronics Education. World Scientific Publishing Co. Pte. Ltd. 1996, p.145-148.

157. R.Ubar, P.Paomets, J.Raik. Low-Cost CAD System for Teaching Digital Test. Microelectronics Education. World Scientific Publishing Co. Pte. Ltd. 1996, p.185-188.

158. M.Min, T.Rang, R.Ubar. Electronics as Infrastructure of the Innovation in Estonia. Congress of Estonian Scientists, Tallinn, 1996, pp.265.

159. R.Ubar, A.Markus, G.Jervan, J.Raik. Fault Model and Test Synthesis for RISC Processors. Baltic Electronics Conference. Proceedings. Tallinn, October 7-11, 1996, pp. 229-232.

160. R.Ubar, M.Brik. Test Generation for Finite State Machines. Baltic Electronics Conference. Proceedings. Tallinn, October 7-11, 1996, pp. 233-236.

161. J.Raik, R.Ubar, G.Jervan, H.Krupnova. A Constraint-Driven Gate Level Test Generation. Baltic Electronics Conference. Proceedings. Tallinn, October 7-11, 1996, pp. 237-240.

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162. R.Ubar. Electronics Competence Centre and Research in Digital Test at Technical University of Tallinn. Invited paper. IEEE 14th NORCHIP Conference, Helsinki, November 4-5, 1996, pp.134-141.

1997163. A. Benso, P.Prinetto, M.Rebaudengo, M.Sonza, R.Ubar. A New Approach to Build a

Low-Level Malicious Fault List Starting from High-Level Description and Alternative Graphs. Proc. IEEE European Design & Test Conference, Paris, March 17-20, 1997, pp.560-565.

164. G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. CAD Software for Digital Test and Diagnostics. Proc. of International Conference on Design and Diagnostics of Electronic Circuits and Systems. Beskydy Mountains, Czech Republic, May 12-16, 1997, pp.35-40.

165. R.Ubar, J.Raik. Multi-Valued Simulation with Binary Decision Diagrams. Proc. IEEE European Test Workshop, Cagliari (Italy), May 28-30, 1997, pp.28-29.

166. R.Ubar. Boolean Derivatives and Multi-Valued Simulation on Binary Decision Diagrams. 4th International Workshop on Mixed Design of Integrated Circuits and Systems. Poznan, June 12-14, 1997, pp.115-120.

167. M.Brik, G.Jervan, A.Markus, J.Raik, R.Ubar. A Hierarchical Automatic Test Pattern Generator Based on Using Alternative Graphs. 4th International Workshop on Mixed Design of Integrated Circuits and Systems. Poznan, June 12-14, 1997, pp.415-420.

168. R.Ubar. Representing Transparency Conditions in Test Generation for VLSI by Decision Diagrams. The 1st Electronic Circuits and Systems Conference. Bratislava, September 4-5, 1997.

169. R.Ubar. Multi-Valued Simulation of Digital Circuits. 21st International Conference on Microelectronics. Nis, Yugoslavia, September 14-17, 1997.

170. R.Ubar. Behavioral Level Modeling of Digital Systems for Testing. Purposes 42nd

International Conference, Ilmenau (Germany), September 22-25, 1997.171. G.Jervan, A.Markus, J.Raik, R.Ubar. Automatic Test Generation System for VLSI. 1st

Electronic Circuits and Systems Conference. Bratislava, September 4-5,1997, pp. 255-258.

172. G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. A Set of Tools for Estimating Quality of Built-In Self-Test in Digital Circuits. Proc. of the International Symposium on Signals, Circuits and Systems. Iasi, (Romania), October 2-3, 1997, pp.362-365.

173. A.Benso, P.Prinetto, M.Rebaudengo, M.Sonza Reorda, J.Raik, R.Ubar. Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Paris, October 20-22, 1997, pp. 212-216.

174. G. Jervan, A.Markus, J. Raik, R. Ubar). Assembling Low-Level Tests to High-Level Symbolic Test Frames. IEEE 15th NORCHIP Conference, Tallinn, November 10-11, 1997, pp. 275-280.

175. M.Brik, G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Mixed-Level Test Generator for Digital Systems. Proceedings of the Estonian Acad. of Sci. Engng, 1997, Vol. 3 , No 4, pp. 271-282.

1998176. R.Ubar. Combining Functional and Structural Approaches in Test Generation for

Digital Systems. Journal of Microelectronics and Reliability, Elsevier Science Ltd. Vol. 38:3, pp.317-329, 1998.

177. R.Ubar. Multi-Valued Simulation of Digital Circuits with Structurally Synthesized Binary Decision Diagrams. OPA (Overseas Publishers Assotiation) N.V. Gordon and Breach Publishers, Multiple Valued Logic, Vol.4 pp. 141-157, 1998.

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178. R.Ubar. Dynamic Analysis of Digital Circuits with 5-valued Simulation. In "Mixed Design of Integrated Circuits and Systems". Kluwer Academic Publishers, pp.187-192, 1998.

179. M.Brik, G.Jervan, A.Markus, J.Raik, R.Ubar. Hierarchical Test Generation for Digital Systems. In "Mixed Design of Integrated Circuits and Systems". Kluwer Academic Publishers, pp.131-136, 1998.

180. G.Jervan, A.Markus, P.Paomets, J.Raik, R.Ubar. Turbo Tester: A CAD System for Teaching Digital Test. In "Microelectronics Education". Kluwer Academic Publishers, pp.287-290, 1998.

181. J.Raik, R.Ubar. Feasibility of Structurally Synthesized BDD Models for Test Generation. Proc. of the IEEE European Test Workshop, Barcelona (Spain), May 27-29, 1998, pp.145-146.

182. G.Jervan, A.Markus, J.Raik, R.Ubar. Hierarchical Test Generation with Multi-Level Decision Diagram. Models Proc. of the 7th IEEE North Atlantic Test Workshop, West Greenwich RI, USA, May 28-29, 1998, pp.26-33.

183. R.Ubar. Mixed Bottom-Up/Top-Down Hierarchical Test Generation for Digital Systems. Proc. of the 9th European Workshop on Dependable Computing, Gdansk (Poland), May 14-16, 1998, pp.37-40.

184. R.Ubar. Teaching Dependability Issues in System Engineering at the Technical University of Tallinn. Preprints of Proceedings, 90th Anniversary Jubilee Seminar on Engineering Education. University of Wismar, Germany, May 6-8 1998, pp.1-5. Invited paper.

185. J.Raik, R.Ubar. Test Generation with Structurally Synthesized BDD Models. Proceedings of the 5th Electronic Devices and Systems Conference, Brno, June 11-12, 1998, pp.66-68.

186. G.Jervan, A.Markus, J.Raik, R.Ubar. VHDL Based Test Generation System. Proceedings of the 5th Electronic Devices and Systems Conference, Brno, June 11-12, 1998, pp.145-148.

187. G.Jervan, A.Markus, J.Raik, R.Ubar. Mixed-Level Deterministic-Random Test Generation for Digital Systems. Proc. of the 5th International Conference on Mixed Design of Integrated Circuits and Systems. Lodz (Poland), June 18-20, 1998, pp. 335-340.

188. R.Leveugle, R.Ubar. Synthesis of Decision Diagrams from Clock-Driven Multi-Process VHDL Descriptions for Test Generation. Proc. of the 5th International Conference on Mixed Design of Integrated Circuits and Systems. Lodz (Poland), June 18-20, 1998, pp. 353-358.

189. J.Raik, R.Ubar. Hierarchical Test Generation for Digital Systems Based on Combining Bottom-Up and Top-Down Approaches. World Multiconference on Systemics, Cybernetics and Informatics. Orlando, Florida, July 12-16, 1998, Vol.1, pp. 374-381.

190. R.Ubar. Dynamic Analysis of Digital Circuits with Multi-Valued Simulation. Microelectronics Journal, Elsevier Science Ltd., Vol. 29, No. 11, Nov. 1998, pp.821-826.

191. R.Ubar, D.Borrione. Localization of Single-Gate Design Errors in Combinational Circuits by Diagnostic Information about Stuck-at Faults. Proc. of the 2nd International Workshop on Design and Diagnostics of Electronic Circuits and Systems. Szczyrk, Poland, Sept. 2-4, 1998, pp.73-79.

192. G.Jervan, A.Markus, J.Raik, R.Ubar. DECIDER: A Decision Diagram Based Hierarchical Test Generation System. Proc. of the 2nd International Workshop on Design and Diagnostics of Electronic Circuits and Systems. Szczyrk, Poland, Sept. 2-4, 1998, pp.269-273.

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193. R.Ubar, D.Borrione. Generation of Tests for the Localization of Single-Gate Design Errors in Combinational Circuits Using the Stuck-at Fault Model. Proc. of the 11th IEEE Brasilian Symposium on Integrated Circuit Design. Rio de Janeiro, Brazil, Sept. 30 – Oct. 3, 1998, pp.51-54

194. M.Brik, R.Ubar. An Improved Test Generation Approach for Sequential Circuits using Decision Diagrams. Proc. of the 6th Baltic Electronics Conference, Oct. 7-9, 1998, Tallinn, pp. 155-158.

195. G.Jervan, A.Markus, J.Raik, R.Ubar. A Decision Diagram Based Hierarchical Test Pattern Generator. Proc. of the 6th Baltic Electronics Conference, Oct. 7-9, 1998, Tallinn, pp. 159-162.

196. E.Ivask, J.Raik, R.Ubar. Comparison of Genetic and Random Techniques for Test Pattern Generation. Proc. of the 6th Baltic Electronics Conference, Oct. 7-9, 1998, Tallinn, pp. 163-166.

197. A.Markus, J.Raik, R.Ubar. Test Set Minimization Using Bipartite Graphs. Proc. of the 6th Baltic Electronics Conference, Oct. 7-9, 1998, Tallinn, pp. 175-178.

198. R.Ubar, J.Heinlaid, J.Raik, L.Raun. Calculation of Testability Measures on Structurally Synthesized Binary Decision Diagrams. Proc. of the 6th Baltic Electronics Conference, Oct. 7-9, 1998, Tallinn, pp. 179-182.

199. R.Leveugle, G.Saucier, R.Ubar. Compaction of Decision Diagrams for Describing Multi-Process VHDL Descriptions. Proc. of the 6th Baltic Electronics Conference, Oct. 7-9, 1998, Tallinn, pp. 195-198.

200. R.Ubar. Teaching Dependability Issues in System Engineering at the Technical University of Tallinn. Global J. of Engineering Education, Vol.2, No 2, 1998 UICEE, Printed in Australia, pp. 215-218.

201. R.Ubar, D.Borrione. Generation of Tests for the Localization of Single Gate Design Errors in Combinational Circuits Using the Stuck-at Fault Model. Research Report, TIMA, INPG, Grenoble, France, May 1998, 12 p. (http://www-tima-vds.imag.fr/Publications/ PubliVDSlong.html).

1999 202. T-S. Lande, R.Ubar. Guest Editorial Analog Integrated Circuits and Signal Processing.

Kluwer Publishers, Vol.18, No 1., January 1999, pp. 5-6.203. R.Leveugle, R.Ubar. Modeling VHDL Clock-Driven Multi-Processes by Decision

Diagrams. J. of Electron Technology, Vol. 32, (1999) No.3, pp.282-287.204. R.Ubar, D.Borrione. Single Gate Design Error Diagnosis in Combinational Circuits.

Proceedings of the Estonian Acad. of Sci. Engng, 1999, Vol. 5 , No 1, pp.3-21.205. J.Raik, R. Ubar. Sequential Circuit Test Generation Using Decision Diagram Models.

IEEE Proc. of Design Automation and Test in Europe. Munich, March 9-12, 1999, pp. 736-740.

206. R.Ubar, A.Moraviec, J.Raik. Cycle-based Simulation with Decision Diagrams. IEEE Proc. of Design Automation and Test in Europe. Munich, March 9-12, 1999, pp.454-458.

207. R.Ubar, D.Borrione. Automatic Diagnosis of Simple Design Errors. TIMA Annual Report 1998, May 1999, p.97-98.

208. G.Elst, K-H.Diener, E.Ivask, J.Raik, R.Ubar. FPGA Design Flow with Automated Test Generation. Proc. of German 11th Workshop on Test Technology and Reliability of Circuits and Systems. Potsdam, 1999, pp. 120-123.

209. R.Ubar, J.Raik. Hierarchical Test Generation for Complex Digital Systems with Control and Data Processing Parts. In “Test, Assembly and Packaging”, SEMICON Technical Symposium, Singapur May 3-6, 1999, pp.43-52.

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210. R.Ubar, J.Raik. Hierarchical Test Generation. SEMI Show slides. In “Test, Assembly and Packaging”, SEMICON Technical Symposium, Singapur May 3-6, 1999, pp. 53-64.

211. J.Raik, R.Ubar. High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation. Compendium of Papers. IEEE European Test Workshop, Constance, May 25-28, 1999, 5 p.

212. R.Ubar, A.Jutman. Hierarchical Design Error Diagnosis in Combinational Circuits by Stuck-at Fault Test Patterns. Proc. of the 6th International Conference on Mixed Design of Integrated Circuits and Systems. Krakow (Poland), June 17-19, 1999, pp. 437-442.

213. A. Markus, J.Raik, R.Ubar. Fast and Efficient Static Compaction of Test Sequences Using Bipartite Graph Representations. Proc. of 2nd Electronic Circuits and Systems Conference. Bratislava, September 6-8, 1999, pp. 17-20.

214. R.Ubar, D.Borrione. R. Design Error Diagnosis in Digital Circuits without Error Model. Research Report, TIMA, INPG, Grenoble, France, May 1999. (http://www-tima-vds.imag.fr/Publications/ PubliVDSlong.html).

215. G.Jervan, P.Eles, Z.Peng, J.Raik, R.Ubar. High-Level Test Synthesis with Hierarchical Test Generation. IEEE 17th NORCHIP Conference, Oslo, Nov. 8-9, 1999, pp.291-296.

216. M.Brik, R.Ubar.Two-Level Simulation-Based Test Generation for Finite State Machines. IEEE 17th NORCHIP Conference, Oslo, Nov. 8-9, 1999, pp.211-216.

217. R.Ubar, D.Borrione. Design Error Diagnosis in Digital Circuits without Error Model. 10th IFIP Int. Conf. on VLSI’99. Lisboa, Dec. 1-4, 1999, pp.281-292.

218. J.Raik, R.Ubar. High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation. Proc. of IEEE European Test Workshop, Constance, May 25-28, 1999, pp.84-89.

2000219. A.Jutman, R.Ubar. Design Error Diagnosis in Digital Circuits with Stuck-at Fault

Model. Journal of Microelectronics Reliability. Pergamon Press, Vol. 40, No 2, 2000, pp.307-320.

220. J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. Journal of Electronic Testing: Theory and Applications. Kluwer Academic Publishers. Vol. 16, No. 3, pp. 213-226, 2000.

221. R.Ubar, D.Borrione. Automatic Diagnosis of Simple Design Errors. In “Techniques of Informatics and Microelectronics for Computer Architecture”, TIMA, France, 1999, pp. 91.

222. J.Mermet, A.Morawiec, R.Ubar. Methods for Improving the Simulation Performance. In “Techniques of Informatics and Microelectronics for Computer Architecture”, TIMA, France, 1999, pp. 91-94.

223. R.Ubar, A.Jutman. Design Error Localization in Digital Circuits by Stuck-at Fault Test Patterns. IEEE 22nd Int. Conference on Microelectronics, Nis, Yugoslavia, May 14-17 2000, pp.723-726.

224. R.Ubar, J.Raik. Efficient Hierarchical Approach to Test Generation for Digital Systems. 1st Int. Symp. on Quality of Electronic Design, San Jose, California, March 20-22, 2000, pp. 189-195.

225. R.Ubar, A.Morawiec, J.Raik. Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. IEEE Proc. of Design Automation and Test in Europe. Paris, March 27-30, 2000, pp. 743.

226. R.Ubar, A.Morawiec, J.Raik. Vector Decision Diagrams for Simulation of Digital Systems. DDECS’2000, Smolenice, April 5-7, 2000, pp. 44-51.

227. K.-H.Diener, G.Elst, E.Ivask, G.Jervan, Z.Peng, J.Raik, R.Ubar. Digital Design Flow with Test Activities. VILAB User Forum, Smolenice, April 8, 2000, 11 p.

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228. M.Blyzniuk, T.Cibakova, E.Gramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Defect Level Test Quality Analysis. VILAB User Forum, Smolenice, April 8, 2000, 11 p.

229. R.Ubar, H.-D.Wuttke. Action Based Learning System for Teaching Digital Electronics and Test. Proc. of 3rd European Workshop on Microelectronics Education, Aix-en-Provence (France), May 18-19, 2000, pp.65-66.

230. E.Ivask, J.Raik, R.Ubar. Fault Oriented Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. IEEE European Test Workshop, Cascais, Portugal, Mai 23-26, 2000, pp. 319-320.

231. M.Blyzniuk, FT.Cibakova, E.Gramatova,W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Defect-Oriented Fault Simulation for Digital Circuits. IEEE European Test Workshop, Cascais, Portugal, Mai 23-26, 2000, pp.151-156.

232. R.Ubar, A.Morawiec, J.Raik. Back-Tracing and Event-Driven Techniques in High-Level Simulation with Decision Diagrams. Proc. of the IEEE ISCAS’2000 Conference, Geneva, May 28-31, 2000, Vol. 1, pp. 208-211.

233. M.Blyzniuk, T.Cibakova, E.Gramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Defect Oriented Fault Coverage of 100% Stuck-at Fault Test Sets. Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems. Gdynia (Poland), June 15-17, 2000, pp.511-516.

234. R.Ubar, M.Brik. Hierarchical Concurrent Test Generation for Synchronous Sequential Circuits. Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems. Gdynia (Poland), June 15-17, 2000, pp.533-538.

235. R.Ubar, A.Morawiec, J.Raik. High-Level Decision Diagrams for Simulation Performance. Proc. of the World Multiconference on Systemics, Cybernetics and Informatics, SCI- 2000. Orlando, Florida, USA, July 23-26, 2000. Vol. IX Industrial Systems, pp.62-67.

236. M.Blyzniuk, FT.Cibakova, E.Gramatova,W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Defect-Oriented ault Simulation for Digital Circuits. IEEE Proceedings ETW 2000, Cascais, Portugal, Mai 23-26, 2000, pp.69-74.

237. R.Ubar, E.Orasson, H.-D.Wuttke. Interactive Teaching Software “Introduction To Digital Test”. 45th International Conference, Ilmenau (Germany), October 4-6, 2000, pp.949-954.

238. R.Ubar. Hierarchical Approach to Test Generation for Digital Systems at System, Circuit and Defect levels. 45th International Conference, Ilmenau (Germany), October 4-6, 2000, pp.711-716.

239. K.-H.Diener, G.Elst, E.Gramatova, W.Kuzmicz, Z.Peng, R.Ubar. Virtual Laboratory for Research in Dependable Miroelectronics. 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.217-220.

240. R.Ubar, A.Jutman. BEC: Increasing the Speed of Delay Simulation in Digital Circuits. 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.31-34.

241. R.Ubar, E.Orasson, J.Raik, H.-D.Wuttke. Combining Learning, Training and Research in Laboratory Course for Design and Test. 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, 221-224.

242. A.Morawiec, J.Raik, R.Ubar. Simulation of Digital Systems with High-Level Decision Diagrams. 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.35-38.

243. M.Brik, J.Raik, R.Ubar. Hierarchical Fault Simulation for Finite State Machines. 7 th

Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.145-148.244. R.Ubar. Virtual Research and Development Laboratory. A European Project. Int. User

Forum “Electronics Design and Test”. Tallinn, October 12, 2000, 14 p.

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245. E.Ivask, J.Raik, R.Ubar. Fault Oriented Test Pattern Generator for Sequential Circuits Using Genetic Algorithms. 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000, pp.129-132.

246. G.Jervan, Z.Peng, R.Ubar. Test Cost Minimization for Hybrid BIST. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems. Tokio, October 25-28, 2000, pp.283-291.

247. R.Ubar, A.Jutman, Z.Peng. Improving the Efficiency of Timing Simulation in Digital Circuits by Using Structurally Synthesized BDDs. IEEE Norchip conference, Turku, November 7-8, 2000, pp.254-261.

248. R.Ubar. Removing Design Errors from Digital Circuits. Proc. of the 4th International Conference on New Information Technologies. Minsk, December 5-7, 2000, Volume 1, pp.118-125.

249. R.Ubar, H.-D.Wuttke. Action Based Learning System for Teaching Digital Electronics and Test. In “Microelectronics Education”, Kluwer Academic Publishers, Dordrecht/ Boston/London, 2000, pp. 107-110.

2001250. R.Ubar. Design Error Diagnosis in Scan-Path Designs. 2nd Latin-American Test

Workshop. Cancun, Mexico, February 11-14, 2001, pp. 162-168.251. A.Jutman, R.Ubar, Z.Peng. Algorithms for Speeding-Up Timing Simulation of Digital

Circuits. DATE, Munich, March 13-16, 2001, pp.460-465.252. R.Ubar, W.Kuzmicz, W.Pleskacz, J.Raik. Defect-Oriented Fault Simulation and Test

Generation in Digital Circuits. 2nd Int. Symp. on Quality of Electronic Design, San Jose, California, March 26-28, 2001, pp.365-371.

253. E.Ivask, R.Ubar, J.Raik, A.Schneider. Internet Based Test Generation and Fault Simulation. Design and Diagnostics of Electronic Circuits and Systems – DDECS‘2001, Györ, Hungary, April 18-20, 2001, pp.57-60.

254. T.Cibaková, E.Gramatova, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Defect-Oriented Library Builder for Functional Test Generation. Design and Diagnostics of Electronic Circuits and Systems – DDECS‘2001, Györ, Hungary, April 18-20, 2001, pp.163-168.

255. J.Raik, A.Jutman, R.Ubar. Fast and Efficient Static Compaction of Test Sequences Based on Greedy Algorithms. Design and Diagnostics of Electronic Circuits and Systems – DDECS‘2001, Györ, Hungary, April 18-20, 2001, pp.117-122.

256. A.Schneider, E.Ivask, J.Raik, P.Miklos, K.H. Diener, R.Ubar, W.Kuzmicz, W. Pleskacz, E. Gramatova. VILAB Test Generation Tools Running Under the MOSCITO System. VILAB User Forum Györ, Hungary, April 18-20, 2001, 12 p.

257. J.Mermet, A.Morawiec, R.Ubar. Methods for improving the performance of simulation. TIMA Laboratory, Annual Report 2000, Grenoble, May 2001, pp.90-94.

258. J.Raik, A.Jutman, R.Ubar. Fast Static Compaction of Test Sequences Using Implications and greedy Search. Digest of European Test Workshop, Stockholm, May 29 – June 1, 20001, pp. 207-210.

259. A.Jutman, R.Ubar. Laboratory Training for Teaching Design and Test of Digital Circuits. MIXDES’01, Zakopane, Poland, June 21-23, 2001, pp. 521-524.

260. T.Cibakova, M.Fischerova, E.Gramatova, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Defect-Oriented Test Generation Using Probabilistic Estimation. MIXDES’01, Zakopane, Poland, June 21-23, 2001, pp.131-136.

261. R. Ubar, J. Raik, E. Ivask, M. Brik. Hierarchical Fault Simulation in Digital Systems. Proceedings of Int. Symp. on Signals, Circuits and Systems SCS’2001, Iasi, Romania, July 10-11, 2001, pp.181-184.

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262. T.Hollstein, Z.Peng, R.Ubar, M.Glesner. Challenges for Future System-on-Chip Design. Proceedings of European Conference on Circuit Theory and Design. Part III. Espoo, Finland, August 28-31, 2001, pp.173-176.

263. R. Ubar, G.Jervan, Z.Peng, E.Orasson, R.Raidma. Fast Test Cost Calculation for Hybrid BIST in Digital Systems. Proc. of EUROMICRO Symposium on Digital Systems Design, Warsaw, September 4-6, 2001, pp.318-325.

264. R.Ubar. Multi-Level Test Generation for Digital Systems at System, Circuit and Defect Levels. Proc. of 7th International Scientific Conference “Theory and Technique of Information Transmission, Reception and Processing”. Tuapse, October 1-4, 2001, pp.286-288.

265. R.Ubar, H.-D.Wuttke. The DILDIS-Project – Using Applets for More Demonstrative Lectures in Digital Systems Design and Test. Proceedings of the 31st ASEE/IEEE Frontiers in Education Conference, FIE’2001, Oct. 10-13, 2001, Reno, NV, USA, pp.SIE-2-7.

266. R.Ubar, H.-D.Wuttke. The DILDIS-Project – Using Applets for More Demonstrative Lectures in Digital Systems Design and Test. 31st ASEE/IEEE Frontiers in Education Conference. Abstracts, Oct. 10-13, 2001, Reno, NV, USA, pp.83.

267. M.Aarna, J.Raik, R.Ubar. Parallel Fault Simulation in Digital Circuits. Proc. of 42th International Scientific Conference of Riga Technical University. Riga, October 11-13, 2001, pp.91-94.

268. M.Blyzniuk, I.Kazymyra, W.Kuzmicz, W.A.Pleskacz, J.Raik, R.Ubar. Probabilistic Analysis of CMOS Physical Defects in VLSI Circuits for Test Coverage Improvements. Journal of Microelectronics Reliability. Pergamon Press. Vol 41/12, Dec. 2001, pp 2023-2040.

269. W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Module Level Defect Simulation in Digital Circuits. Proceedings of the Estonian Academy of Sciences, No 7/4, 2001, pp.253-268.

270. A. Jutman, R. Ubar. Application of Structurally Synthesized Binary Decision Diagrams for Timing Simulation of Digital Circuits. Proceedings of the Estonian Academy of Sciences, No 7/4, 2001, pp.269-288.

271. H.Kruus, R.Ubar, G.Jervan, Z.Peng. Using Tabu Search Method for Optimizing the Cost of Hybrid BIST. XVI Conference on Design of Circuits and Integrated Systems, Porto, Portugal, Nov. 20-23, 2001, pp.445-450.

272. R.Ubar, J.Heinlaid, L.Raun. Improved Testability Calculation for Digital Circuits. 19th

IEEE Conference NORCHIP’2001, Stockholm, Sweden, pp.264-270.2002273. R.Ubar, J.Raik, E.Ivask, M.Brik. Multi-Level Fault Simulation of Digital Systems on

Decision Diagrams. IEEE Workshop on Electronic Design, Test and Applications – DELTA’02, Christchurch, New Zealand, 29-31 January 2002, pp.86-91.

274. R.Ubar. Testability Calculation for Digital Circuits with Decision Diagrams. 3 rd IEEE Latin-American Test Workshop – LATW’2002, Montevideo, Uruguay, February 10-13, 2002, pp.137-143.

275. A.Schneider, E.Ivask, P.Mikloš, J.Raik, K.H.Diener, R.Ubar, T.Cibáková, E.Gramatová. Internet-based Collaborative Test Generation with MOSCITO. IEEE Proc. of Design Automation and Test in Europe – DATE’02. Paris, March 4-8, 2002, pp. 221-226.

276. T.Cibáková, M.Fischerová, E.Gramatová, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Test Generation for Combinational Circuits with Real Defects Coverage. Pergamon Press. Journal of Microelectronics Reliability, Vol. 42, 2002, pp.1141-1149.

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277. G.Jervan, H.Kruus, Z.Peng, R.Ubar. About Cost Optimization of Hybrid BIST in Digital Systems. 3rd Int. Symp. on Quality of Electronic Design, San Jose, California, March 18-20, 2002, pp.273-279.

278. R. Ubar, E. Orasson, T. Evartson. Java Applet for Self-Learning of Digital Test Issues. 13th EAEEIE Conference, York, Great Britannia, April 8-10, 2002.

279. A.Jutman, J.Raik, R.Ubar. On Efficient Logic-Level Simulation of Digital Circuits Represented by the SSBDD Model. 23rd Int. Conf. on Microelectronics. Nis, Yugoslavia, May 12-15 2002, Vol.2, pp.621-624.

280. R.Ubar, J.Raik, E.Ivask, M.Brik. Mixed-Level Defect Simulation in Data-Paths of Digital Systems. 23rd Int. Conf. on Microelectronics. Nis, Yugoslavia, May 12-15 2001, Vol.2, pp.617-620.

281. R.Ubar. E.Orasson, H.-D.Wuttke. Internet-Based Software for Teaching Test of Digital Circuits. 23rd Int. Conf. on Microelectronics. Nis, Yugoslavia, May 12-15 2002, Vol.2, pp.659-662.

282. R.Ubar, J.Raik, E.Ivask, M.Brik. Defect-Oriented Mixed-Level Fault Simulation in Digital Systems. Facta Universitatis (Nis), Ser.: Elec. Energ. Vol.15, No.1, April 2002, pp.123-136.

283. R.Ubar, A.Jutman, E.Orasson, J.Raik, T.Evartson, H.-D.Wuttke. Internet-Based Software for Teaching Test of Digital Circuits. In the book "Microelectronics Education", Marcombo Boixareu Ed., 2002, pp.317-320.

284. J.Raik, A.Jutman, R.Ubar. Exact Static Compaction of Sequential Circuit Tests Using Branch-and-Bound and Search State Registration. 7th IEEE European Test Workshop, Corfu, May 26-29, 2002, pp.19-20.

285. A.Jutman, J.Raik, R.Ubar. SSBDD Model: Advantageous Properties and Efficient Simulation Algorithms. 7th IEEE European Test Workshop, Corfu, May 26-29, 2002, pp.345-346.

286. A.Jutman, M.Kruus, A.Sudnitsyn, R.Ubar. Distance-Learning Tools for Digital Design and Test Issues. Proc. of Information Technologies in Science, Education, Telecommunication and Business. Gurzuf, Mai 20-30, 2002, pp.269-272.

287. S.Devadze, A.Jutman, A.Sudnitsõn, R.Ubar. WEB-Based Training System for Teaching Basics of RT-Level Digital Design, Test and Design for Test. Proc. of the 9 th

Int. Conf. MIXDES 2002, Wroclaw, June 20-22, 2002, pp.699-704. 288. T.Nõmmeots, J.Raik, R.Ubar. Testability Analysis for Efficient Register-Transfer Level

Test Generation. Proc. of the 9th Int. Conf. MIXDES 2002, Wroclaw, June 20-22, 2002, pp.555-558.

289. A.Schneider, K.-H.Diener, E.Ivask, R.Ubar, E.Gramatova, T.Hollstein, W.Pleskacz, W.Kuzmicz, Z.Peng. Integrated Design and Test Generation Under Internet Based Environment MOSCITO. EUROMICRO Conference, September 3-6, 2002, pp. 187-194.

290. R.Ubar, J.Raik, E.Ivask, M.Brik. Test Cover Calculation in Digital Systems with Word-Level Decision Diagrams. Proc. of the International Conference on Computer Dependability, Tomsk, Russia, September 10-13, 2002, pp.315-319. Invited paper.

291. A.Jutman, R.Ubar, V.Hahanov, O.Skvortsova. Practical Works for On-Line Teaching Design and Test of Digital Circuits. Proc. of the 9th IEEE International Conference on Electronics, Circuits and Systems – ICECS’2002 Vol. III. Dubrovnik, Croatia, September 15-18, 2002, pp.1223-1226.

292. J.Raik, A.Jutman, R.Ubar. Fast Static Compaction of Tests Composed of Independent Sequences: Basic Properties and Comparison of Methods. Proc. of the 9th IEEE International Conference on Electronics, Circuits and Systems – ICECS’2002 Vol. II. Dubrovnik, Croatia, September 15-18, 2002, pp.445-448.

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293. A. Jutman, J. Raik, R. Ubar. SSBDDs: Advantageous Model and Efficient Algorithms for Digital Circuit Modeling, Simulation & Test. 5th Int. Workshop on Boolean Problems. Freiberg, Germany, September 19-20, pp.157-166.

294. A.Jutman, E.Aleksejev, R.Ubar. A New Evolutionary Techniques Based Approach to Optimize Pseudorandom TPG for Logic BIST. Proc. of the 1st Int. Congress on Mechanical and Electrical Engineering and Technology. Varna, October 7-11, 2002, Part I, pp.247-252.

295. A.Schneider, K.-H.Diener, E.Ivask, R.Ubar, E.Gramatova, M.Fisherova, W.Pleskacz, W.Kuzmicz. Defect-Oriented Test Generation and Fault Simulation in the Environment of MOSCITO. Proceedings, BEC-2002, Tallinn, October 6-9, 2002, pp.303-306.

296. A.Schneider, K.-H.Diener, J.Raik, R.Ubar, G.Jervan, Z.Peng, T.Hollstein, M.Glesner. High-Level Synthesis and Test in the MOSCITO-Based Virtual Laboratory. Proc. BEC-2002, Tallinn, October 6-9, 2002, pp.287-290.

297. S.Devadze, A.Jutman, A.Sudnitsõn, R.Ubar, H.-D.Wuttke. Java Technology Based Training System for Teaching Digital Design and Test. Proceedings, BEC-2002, Tallinn, October 6-9, 2002, pp.283-286.

298. J.Raik, A.Jutman, R.Ubar. Exact Static Compaction of Independent Test Sequences. Proceedings, BEC-2002, Tallinn, October 6-9, 2002, pp.315-318.

299. A.Schneider, K.-H.Diener, G.Elst, E.Ivask, J.Raik, R.Ubar. Internet-Based Testability-Driven Test Generation in the Virtual Environment MOSCITO. Proc. IFIP Conference on IP Based SOC Design, Grenoble, France, October 30-31, 2002, pp.357-362.

300. R.Ubar, Jaan Raik, Tanel Nõmmeots. Testability Guided Hierarchical Test Generation with Decision Diagrams. 20th IEEE Conference NORCHIP’2002, Copenhagen, Denmark, November 11-12, 2002, pp.265-271.

301. S.Devadze, A.Jutman, A.Sudnitson, R.Ubar, H.-D.Wuttke. Teaching Digital RT-Level Self-Test Using a Java Applet. 20th IEEE Conference NORCHIP’2002, Copenhagen, Denmark, November 11-12, 2002, pp.322-328.

302. R.Ubar, E.Orasson, T.Evartson. Self-learning tool for digital test. Proceedings of 2nd

Int. Conf. “Distance learning – educational sphere of the XXI century”, Minsk, Belarus, Nov. 26-28, 2002, pp. 36-38.

303. H.-D. Wuttke, M.Ali-Ebert, D.Dascaly, E.Gramatova, M.Hristov, W.Kuzmicz, V.Nelayev, R.Seinauskas, V.Stepanets, R.Ubar. Internet in training of engineers: a tool or a toy? Educational workshop associated with the EC conference "IST for Broadband Europe", Bucharest, Romania, October 11, 2002, 6 pages.

2003304. R.Ubar. Design Error Diagnosis with Resynthesis in Combinational Circuits. Journal of

Electronic Testing: Theory and Applications 19, 73-82, 2003. Kluwer Academic Publishers.

305. J.Raik, T.Nõmmeots, R.Ubar. New Method of Testability Calculation to Guide RT-Level Test Generation. LATW´03.

306. R.Ubar, E.Orasson. E-Learning tool and Excercises for Teaching Digital Test. Tuneesia.

307. NOC-BookCoauthors:Estonia: M.Aarna, M.Ajaots, V.Alango, E.Aleksejev, M.Brik, A.Buldas, S.Devadze,

J.Dushina, T.Evartson, V.Grigorenko, K. Grigorjeva, H.Haak, J.Heinlaid, U.Heiter, E.Ivask, G.Jervan, A, Jutman, P.Kitsnik, E.Kivi, T.Kont, H.Krupnova, H.Kruus, M.Kruus, T.Lohuaru, M.Männisalu, A.Markus, M.Min, T.Nõmmeots, E.Orasson, M.Pall, P.Paomets, M.Plakk, P.Pukk, R.Raidma, J.Raik, T.Rang, R.Raud, L.Raun, M.Saarepera, S.Storozhev, A.Sudnitsõn, T.Toome,

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A.Toomsalu, V.Tulit, K.Vainomaa, E.Vanamölder, A.Viilup, A.Voolaine, V.Zaugarov (49)

France. P.Amblard, D.Borrione, B.Courtois, R.Leveugle, J.Mermet, A.Morawiec, G.Saucier (7)

Germany: D.Bochmann, K.-H. Diener, G.Elst, M.Glesner, T.Hollstein, G.Knospe, T.Lorenz, A.Schneider, B.Straube, E.Thoma, H.-D.Wuttke (11)

Italy: A.Benso, P.Prinetto, M.Rebaudengo, M.Sonza Reorda (4)Norway: T-S. Lande (1)Poland: W.Kuzmicz, W.Pleskacz (2)Romania: P.Eles (1)Russia: B.Dobriza, V.Maslennikov, A.Seleznev (3)Slovakia: T.Cibakova, M.Fischerova, E.Gramatova, P.Miklos (4)Sweden: K.Kuchinski, Z.Peng (2)Ukraine: M.Blyzniuk, V.Hahanov, M.Lobur, I.Kazymyra, O.Skvortsova (5)

Kokku: 89 (sellest õpilasi 35)

Prof. Raimund UbarTallinn Technical University17.11.2002

Additional papers of the Laboratory:

20011. A.Schneider, P.Schneider, E.Gramatova, E.Ivask. Internet-basierter Systementwurf mit

MOSCITO. In “Entwurf Integrierter Schaltungen”, 10. E.I.S. Workshop, Dresden, April 3-5, 2001, pp. 295-296.

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