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Body biasing is a disruptive 22FDX® feature which enables the adaption of transistor threshold voltages after production during device operation. Racyics® dense 9T logic standard cells libraries and low power 8T standard cell libraries are fully enabled for the adaptive body biasingaware implementation and sign-off flow of the Racyics® ABX Platform solution. The libraries include adaptive body bias aware characterization (CCS, CCSN, LVF) to fully leverage the benefits of Racyics® ABX corner tightening at implementation and sign-off for improved PPA. Being able to operate down to 0.4 V, true minimum energy point (MEP) implementations are enabled. Í Contains >300 cells, various Vt and channel length options Í Robust power supply rails on M2, optimized M1 pin access with at least two on-track M2 access points Í DFM and variability optimized layouts and variation aware placement attributes for automated place&route Í Enabled for reliable ULV operation down to 0.4 V in combination with adaptive forward body bias Í Characterization corners for -40 °C to 125 °C temperature range for Racyics® ABX aware timing and power sign-off Í LVF characterization for non-gaussian random distributions Í Silicon validation for wide range of PVT conditions CHALLENGE KEY FACTS IP SPECIFICATION RACYICS® ABX SIGN-OFF IMPROVEMENTS Racyics® Standard Cell Libraries GLOBALFOUNDRIES® 22FDX® [email protected] +493514188720 www.racyics.com DESIGN VIEWS Í Verilog simulation models Í .lib/.db timing (NLDM, CCS, CCS noise, LVF) and power models Í .lef layout abstract views Í Milkyway database Í GDSII layouts Í LVS netlist IP Supplier Description VT options Gate Length Supply Voltages [V] ZBB (Zero Bias) ABX Ready for Evaluation Ready for Testchip Ready for Production rilib_gf22fdx_9t Racyics 104CPP 9T CNRX STD-cell library SLVT, LVT C20, C24, C28 0.40/0.45/ 0.50/0.60/ 0.80 yes yes, FBB now now now RVT, HVT, LLHVT C20, C24, C28 0.65/0.80/0.90 yes yes, RBB (Vt dependent) now now now rilib_gf22fdx_8t 116CPP 8T CNRX STD-cell library SLVT, LVT C20, C24, C28, C32, C36 0.40/0.45/ 0.50/0.60/ 0.80V yes yes, FBB now now now RVT, HVT, ULLHVT C20, C24, C28, C32, C36 0.65/0.80/0.90 yes yes, RBB (Vt dependent) now now now delay typical PVT fast PVT slow PVT ZBB Racyics® global local local delay ABX

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Page 1: Racyics® Standard Cell Libraries...Racyics® dense 9T logic standard cells libraries and low power 8T standard cell libraries are fully enabled for the adaptive body biasingaware

Body biasing is a disruptive 22FDX® feature which enables the adaption of transistor threshold voltages after production during device operation. Racyics® dense 9T logic standard cells libraries and low power 8T standard cell libraries are fully enabled for the adaptive body biasingaware implementation and sign-off flow of the Racyics® ABX Platform solution. The libraries include adaptive body bias aware characterization (CCS, CCSN, LVF) to fully leverage the benefits of Racyics® ABX corner tightening at implementation and sign-off for improved PPA. Being able to operate down to 0.4 V, true minimum energy point (MEP) implementations are enabled.

Í Contains >300 cells, various Vt and channel length options

Í Robust power supply rails on M2, optimized M1 pin access with at least two on-track M2 access points

Í DFM and variability optimized layouts and variation aware placement attributes for automated place&route

Í Enabled for reliable ULV operation down to 0.4 V in combination with adaptive forward body bias

Í Characterization corners for -40 °C to 125 °C temperature range for Racyics® ABX aware timing and power sign-off

Í LVF characterization for non-gaussian random distributions

Í Silicon validation for wide range of PVT conditions

CHALLENGE

KEY FACTS

IP SPECIFICATION

RACYICS® ABX SIGN-OFF IMPROVEMENTS

Racyics® Standard Cell LibrariesGLOBALFOUNDRIES® 22FDX®

[email protected] +493514188720www.racyics.com

DESIGN VIEWS Í Verilog simulation models

Í .lib/.db timing (NLDM, CCS, CCS noise, LVF) and power models

Í .lef layout abstract views

Í Milkyway database

Í GDSII layouts

Í LVS netlist

IP Supplier Description VT options

Gate Length

Supply Voltages [V]

ZBB (Zero Bias)

ABX Ready for Evaluation

Ready for Testchip

Ready for Production

rilib

_gf2

2fdx

_9t

Rac

yics

104CPP 9T CNRX STD-cell library

SLVT, LVTC20, C24,

C28

0.40/0.45/0.50/0.60/

0.80yes

yes,FBB

now now now

RVT, HVT, LLHVT

C20, C24, C28

0.65/0.80/0.90 yesyes,

RBB (Vt dependent)

now now now

rilib

_gf2

2fdx

_8t

116CPP 8T CNRX STD-cell library

SLVT, LVTC20, C24, C28, C32,

C36

0.40/0.45/0.50/0.60/

0.80Vyes

yes,FBB

now now now

RVT, HVT, ULLHVT

C20, C24, C28, C32,

C360.65/0.80/0.90 yes

yes,RBB (Vt

dependent)now now now

delaytypical PVTfast PVT slow PVT

ZBB

Racyics®ABB

global

local local

delay

ABX

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