r09-cpld & fpga architectures and applications

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  • 7/27/2019 r09-Cpld & Fpga Architectures and Applications

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    R09Code No: C6106, C0608, C7702, C6802, C5702

    JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

    M.Tech I Semester Examinations October/November-2011

    CPLD & FPGA ARCHITECTURES AND APPLICATIONS

    (COMMON TO COMMUNICATION SYSTEMS, DIGITAL SYSTEMS & COMPUTER ELECTRONICS,

    EMBEDDED SYSTEMS & VLSI DESIGN, VLSI & EMBEDDED SYSTEMS, VLSI SYSTEM DESIGN )Time: 3hours Max.Marks:60

    Answer any five questions

    All questions carry equal marks

    - - -

    1.a) Explain the Max 5000/7000 series architecture.

    b) Explain Pac with an example. [12]

    2. Explain lattice plats architecture 3000 series. [12]

    3.a) Explain the design aspects of AXC4000 FPGA.

    b) Explain the design flow for FPGA. [12]

    4. Explain one-hot state machine with an example. [12]

    5. Explain the extended petrinets for parallel controller. [12]

    6. Explain the front end design tools for fpgas and asics. [12]

    7. Explain the multiplexer design. [12]

    8. Write short notes on the following.

    i. Speed performance of actel

    ii. Speed performance in system programmabilityiii. Asic design flow. [12]

    * * * * * *

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