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*Thit k kin trc h thng Vit code RTL v m phng Cng on tng hp netlist

*Functional specification : L m t yu cu t pha ngi dng nh 1 bn cc chc nng yu cu tn hieu input v output ca 1 h thng hay l datasheet .Cn phi hiu r nguyn l hot ng ca ton b h thng, cc c im v cng ngh, tc x l, mc tiu th nng lng, cch b tr cc Pins, cc lc khi, cc iu kin vt l nh kch thc, nhit , in p...

*Define Architecture : M t chi tit chc nng tng khi La chn thut ton x l Xy dng v tr tng khi S dng ngun IP hay t pht trinChn la tool v ngn ng.

*Coding RTL :S dng ngn ng thit k phn cng (Verilog-HDL,VHDL, System-C...) hin thc cc chc nng logic ca thit k. Lc ny ta khng cn quan tm n cu to chi tit ca mch m ch ch trng vo chc nng ca mch da trn kt qu tnh ton cng nh s lun chuyn d liu gia cc thanh ghi .

*RTL Verification :Kim tra thit k logicLoi tr li t VHDL code M phng simulation bi tool chuyn dng

*Synthesis :Sau khi kim tra v m bo h thng chy ng chc nng, RTL code c dng tng hp to netlist .c h tr ca cc cng c chuyn dng nh Design Compiler (Synopsys), Synplify (Synplicity)H thng t ch c m t bng RTL s c chuyn sang mc cng, m t di dng text v c gi l netlist .

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*L giai on phn tch v mt thi gian ca thit k sau khi Synthesis, phn mm s dng l PrimeTime cho php phn tch tr hon qua cc ng truyn tn hiu trong thit k. Kt qu phn tch s l cc bo co, ngi thit k da vo cc bng bo co ny xem tc hot ng ca thit k c t yu cu hay khng. Trong thc t qu trnh STA c lp i lp li nhiu ln vi Synthesis cho n khi cc yu cu v thi gian ca thit k c p ng. STA gm hai giai on: pre-layout STA v post-layout STA. Giai on pre-layout STA m bo thit k tha mn cc yu cu v thi gian sau qu trnh Synthesis. Giai on post-layout STA m bo thit k vn tha v thi gian sau khi Back End thit t cc gi tr thc v R, C ca cc Cell v cc dy ni.

*C u vo l file netlist t Front EndKt thc s to ra file *.gds hay *.gds2

*Chc nng :To hnh cho linh kin transistor, in tr, t in, cun cm , dy dn Tun theo cc qui lut (design rules) m cng ngh ang s dng .

*FloorplanningPlace v Routing Tape-outBack End

*Cng c nhn cc file th vin vt l, th vin logic v file netlist lm c s to layout Floorplanning l qu trnh sp xp cc khi trong vng die hay bn trong cc khi khc v gia chng phi c nh ngha cc vng dng i dy. Qu trnh Floorplanning c nh hng rt ln n hiu sut v nh thi ca mchCht lng Floorplanning nh hng ng k n cht lng thit k ca chng ta.

*Qu trnh t cc Cell v kt ni dy da trn kt ni v mt Logic gia cc Cell trong Gate-level Netlist. Tip theo l kt ni dy s tin hnh giai on post-layout STA v post-layout simulation m bo Netlist vi cc gi tr thc v R, C ca cc Cell v dy ni vn tha chc nng v thi gian. Nu khng c li, xut d liu ra di dng file gds2. Nu c li, kim tra li vic t cc Cell v kt ni dy.

*Kim tra li tt c cc bo co sau qu trnh Place and Route trc khi a i sn xut.

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*Kim tra ,so snh gia schematic v layout c v c ph hp cha ?

*Mask l ci khun c vi mch ln tm Silicon. Cc b Mask s c to ra di dng data c bit. Mask data s c gi ti cc nh sn xut Mask nhn v mt b Mask kim loi phc v cho cng vic sn xut tip theo

*Cng ngh sn xut Mask hin i dng tia in t (EB - Electron Beam). Cc in t vi nng lng ln (vi chc keV) s c vut thnh chm v c chiu vo lp film Crom trn b mt tm thy tinh. Phn Cr khng b che bi Mask (artwork) s b ph hy, kt qu l phn Cr khng b chm electron chiu vo s tr thnh mask thc s.

*Chun b waferCc quy trnh x lKim tra ng gi-xut xng

*y l bc tinh ch ct(SiO2) thnh Silic nguyn cht .Silic nguyn cht s c pha thm tp cht l cc nguyn t nhm 3 hoc nhm 5.

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*Sau khi c c c ta c mt khi silicon n tinh th.Cn c gi l thi silicon(silicon Ingot) v c cc tnh cht c th sn xut transistor.

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*Cng on ny c gi l ingot slicingSau khi c ct lt chng ta co nhng wafer dng th.V chng s c nh bng cho n khi mt thng khng nhn thy nhng t vt na. Trc khi i in litho.

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*y l bc chun b to ra cc transistor.Tm wafer c bi du cc dung dch lngDch ny dng chn quang(photo resist)

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*Sau khi hnh thnh gia cc lp chn quang wafer s c phi sng trc cc tia t ngoi(UV).Trc khi chm vo b mt wafer cc tia t ngoi s phi lt qua cc khe c c sn trn tm mt n.

*T trn xung: UV -> mask -> len -> wafer

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*Lp chn quang b chuyn sang dng ha tan v s c ty sch bng mt dng dung mi ph hp.

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*Mu xm l phn silicon nnMu hng tm l lp vt liu cch inMu lc l phn silicon tinh th to ra ngun mng v knhMu vng l lp in mi (lp ny kh quan trng, ti s k vo dp khc)

*Mu lam nht l cc cngMu lam m nh lc trc l lp chn quang quen thuc. Mc ch ca vic cy ion l to ra cc ngun v cc mng.

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*Tm wafer c ngm vo dung dch CuSO4.Phn cn li ca wafer ni vo cc m (-) ca ngun in. Cc dng (+) l mt ming ng c ngm chm vo dung dch mui.

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*kim tra hiu nng chip trc khi tung ra th trng.

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FPGA Design AdvantagesASIC Design AdvantagesFaster time-to-market: no layout, masks or other manufacturing steps are needed.No upfront NRE (non recurring expenses):costs typically associated with an ASIC design.Simpler design cycle: due to software that handles much of routing, placement, and timing.Field reprogramability: a new bitstream can be upload remotelyFull custom capability: for design since device is manufactured to design specs.Lower unit costs: for very high volume designs.Smaller form factor: since device is manufactured to design specs.Higher raw internal clock speeds.

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Truyn thng: in thoi s, mng . My tnh: PC/Workstation, Chipset. Hng tiu dng: Game box, Camera s , TV .

*OMAP 4- Sn xut theo cng ngh 45n- Kch thc 12mm x 12mm x 0.4mm- Li ha POWER VR SGX540, h tr giao din 3D.- H tr mn hnh phn gii WSXGA.- Ng video HDMI.- Chy video 1080p HD hn 10h.- Ghi video 1080p HD hn 4h.- Nghe nhc cht lng CD 140h.- Tch hp cc cng ngh wireless tin tin nh WiLink, Wi-Fi, NaviLink GPS v BlueLink Bluetooth.- H tr chip qun l nng lng.- H tr my chiu siu nh.H tr my chiu siu nh

*NVIDIA Tegra 2- Sn xut theo cng ngh 40nm.- Tng thch cc HH: Windows CE, WinMo, Android, Chrome OS cho nn h tr tt cho cc thit b di ng.- Gm c 8 nhn x l c lp- Gii m tt hnh nh 3D.- Xem phim Full HD 1080p.- H tr my nh 12MP.- Tiu th in nng khong 500mW.

Mt board mch my tnh s dng Tegra 2

Qu trnh no ko s dng tool la system-level specification . Cc qu trnh cn lai u s dng Thy Hiu c hi phn bit behavior level v RT-level ?.Technology Mapping lm g ? S dng g ?..

Qui trnh thiet ke gom 2 cong doan :1.Front end : to ra file netlist cho phn back end 2.Back end : mc ch cuoi l to ra san pham chip

We define an SoC as an IC,designedbystitching together multiple stand-aloneVLSIdesignstoprovidefullfunctionalityforanapplication.ThisdefinitionofSoCclearlyemphasizespredesigned models of complex functions knownascores (termssuchasintellectualpropertyblock,virtualcomponents,andmacrosarealsoused)thatserveavarietyofapplications.

Mt h thng l mt s tp hp ca tt c cc loi thnh phn v/hoc cc h thng con (subsystems). Cc thnh phn ny c kt ni hp l thc hin cc chc nng c bit no cho ngi dng cui. V c bn, mt thit k SoC bao gm cc thnh phn: Vi x l lp trnh c. B nh on - chip. Cc n v chc nng gia tc (DSP). Giao tip ngoi vi. Phn mm nhng. Front End Giai on thit k lun l c chia thnh ba cng on nh: thit k kin trc h thng, vit code RTL v m phng v cng on tng hp netlist.

Define Architecture : Mo ta chi tiet tung khoi . Lua chn thuat ton x l , chn lua kien truc sap dat cac vi tri tung khoi , chi tiet ha cc khoi he thong con , su dung IP hay tu phat trien , su dung ngon ngu thiet ke .ngi thit k cn xy dng file m t kin trc cho h thng mc logic. La chn cc khi logic s thc thi cc chc nng. File ny c dng cho vit m t h thng bng RTL giai on sau.

Coding RTL :S dng ngn ng thit k phn cng (Verilog-HDL, VHDL, System-C...) hin thc cc chc nng logic ca thit k. Lc ny ta khng cn quan tm n cu to chi tit ca mch m ch ch trng vo chc nng ca mch da trn kt qu tnh ton cng nh s lun chuyn d liu gia cc thanh ghi (register). y l thit k mc chuyn thanh ghi (RTL Register Transfer Level). Sau thit k RTL s c m phng kim tra xem c tha tnh ng n ca mch hay khng Register Transfer Level (RTL) simulation and verification is one of the initial steps that was done. This step ensures that the design is logically correct and without major timing errors. It is advantageous to perform this step, especially in the early stages of the design, because long synthesis and place-and-route times can be avoided when an error is discovered at this stage. This step also eliminates all the syntax errors from your VHDL code. We used the Synopsys simulation tools to perform RTL verification. More specifically, vhdlan, or VHDL_analyzer was used. In addition, if the design contains LogiBloX components, (which is usually the case), the corresponding VHDL primitives generated by Xilinx tools along with Xilinx libraries have to be visible to the Synopsys tools. In the following I will describe the process of compiling/simulating a VHDL design that includes LogiBloX using VHDL_analyzer. An example of a test-bench VHDL file will be explained and simulated against the design. Finally, few debugging tips that we picked up along the way will be given.

Tip theo, thit k RTL c tng hp (synthesize) thnh cc cng (gate) c bn: NOT, NAND, XOR, MUX, Tng hp (Synthesis): Sau khi kim tra v m bo h thng chy ng chc nng, RTL code c dng tng hp to netlist. cng on ny, ngi thit k cn chun b thm constraints (file m t cc rng buc v mi trng v v timing tng tc vi phn mm) v th vin dng tng hp logic. Th vin l ni cha sn cc m t chc nng cho cc khi logic nh: NAND, OR, MUX, ... v cc thng tin v timing cho khi chc nng . Vi s h tr ca cc cng c chuyn dng nh Design Compiler (Synopsys), Synplify (Synplicity), XST (Xilinx), h thng t ch c m t bng RTL s c chuyn sang mc cng, m t di dng text v c gi l netlist. Kt qu ny khng phi l duy nht v n ph thuc vo cng c v th vin. Netlist thu c trong qua trnh thit k lun l c dng to layout cho chip. giai on ny cc linh kin (transistor, in tr, t in, cun cm) v cc lin kt gia chng s c to hnh (hnh dng thc t ca cc linh kin v dy dn trn wafer trong qu trnh sn xut). Vic thit k tun theo cc qui lut (design rules) m nh sn xut a ra. Cc qui lut ny ph thuc vo kh nng thi cng v cng ngh ca ca nh my sn xut. C hai loi qui lut thit k l: lamda () v qui lut tuyt i. Vi qui lut lamda th cc kch thc phi l bi s ca lamda, trong khi qui lut tuyt tuyt i s dng cc kch thc c nh. S dng qui lut lamda gip ta chuyn i thit k nhanh khi cng ngh thay i. Thit k s c h tr ln bi CADs, t vic s dng li th vin cc cells c bn cho n place and route t ng. Chip analog i hi cc thit k chnh xc v cc k thut chuyn bit m bo tng thch (matching) gia cc linh kin nhy cm, chng nhiu (noise) v p ng tn s. ton b qu trnh thit k vt l s c tapeout ra 1 file (*.gds hay *.gds2) v gi n nh my sn xut. Giai on thit k vt l bao gm 3 phn chnh: Floorplanning; Place & Routing v Verification. Floorplanning: cng c nhn cc file th vin vt l, th vin logic (dng trong lc to netlist) v file netlist lm c s to layout. Floorplanning l qu trnh sp xp cc khi trong vng die hay bn trong cc khi khc v gia chng phi c nh ngha cc vng dng i dy. Qu trnh Floorplanning c nh hng rt ln n hiu sut v nh thi ca mch, nht l i vi nhng thit k phc tp. Cht lng Floorplanning nh hng ng k n cht lng thit k ca chng ta. Place and Route: Place and Route l qu trnh t cc Cell v kt ni dy da trn kt ni v mt Logic gia cc Cell trong Gate-level Netlist. Sau khi hon tt vic t cc Cell v kt ni dy s tin hnh giai on post-layout STA v post-layout simulation m bo Netlist vi cc gi tr thc v R, C ca cc Cell v dy ni vn tha chc nng v thi gian. Nu khng c li, xut d liu ra di dng file gds2. Nu c li, kim tra li vic t cc Cell v kt ni dy. Tape-out: Kim tra li tt c cc bo co sau qu trnh Place and Route trc khi a i sn xut.

Mask l ci khun c vi mch ln tm Silicon. Cng ngh sn xut Mask hin i ch yu dng tia in t (EB - Electron Beam). Cc in t vi nng lng ln (vi chc keV) s c vut thnh chm v c chiu vo lp film Crom trn b mt tm thy tinh. Phn Cr khng b che bi Mask (artwork) s b ph hy, kt qu l phn Cr khng b chm electron chiu vo s tr thnh mask thc s. Mt chip cn khong 20 ti 30 masks. Gi thnh cc tm Mask ny cc t, c vi triu USD.

V d pha B s c wafer loi p, pha P s ra wafer loi n*Sillicon sau khi c tch ra nm trng trng thi nng chy v c lm ngui bng cc ging nh hinh trn

*Trn l hnh nh m silicon kt tinh li hay con goi l silicon n tinh th.v n co cc tnh cht c th ch to transistor*Trn thc t c rt nhiu bc khc trn l cc bc chnh m intel s dng hin nay*T cc thi silicon c ng knh khong 300mm.Mt li ca s tch chng thnh nhng tm silicon hay con gi l wafer*Chng ta vn cn thy nhng t vt trn b mt. V chng s c nh bng cho n khi mt thng khng nhn thy nhng t vt na. Trc khi i in litho.

*Chc nng cu dch ny l chiu trn thay cho lp silicon bn di v m bo vic chn quang c ng u tm wafer s quay u dch c th ph ton b wafer *T y vic pht tho s hnh nh ca con chp c tin hnh thng qua php in khun(stencil). thu nh kch thc gia mt n v wafer l mt thu knh hi (len)*Nhn gn hn cp 200nm . trn chng ta quan st l cp 300mm.chng ta s thy chi tit t bo ca mt con chip transistor*Kt thc tin trnh in litho ,wafer bc vo giai on khc acid*Tm wafer c ngm vo mi trng acid c tnh n mn silicon.Lp chn quang by gi cn c chc nng khng cho acid n vo cc v tr khng mong mun.*Thnh qu l chng ta thu c nhng tm wafer vi cc rnh in mong mun*Nhc qua mt cht 2 cc ca transistor (cn gi l ngun v mng)cng silicon tinh th nhng b pha tp bi mt s ion l 2 cc ny c kh nng dn in.bn thn knh gia hai cc ny n thun l silicon n tinh th nn khng dn in hoc lun dn in ty thuc vo transistor dng *Mc ch ca vic cy ion l to ra cc ngun v cc mng.

*Phn no khng c lp chn quang s b cc ion bn ph.*Sau khi bn pha v c bn th transistor c hon thnh.*Di tc dng ca dng in, ** t tm ng chuyn thnh cc ion ha tan v bi n bn cc m l b mt tm wafer. Cc cation nhn electron y v bm dnh ln b mt wafer, to thnh mt lp ng. Do vy qu trnh ny c gi l lng kim loi (tm wafer nm di y dung dch).*Thc t, mt con chip c ti vi chc tng lin kt vi nhau, ty theo tnh phc tp ca kin trc m n mang trong mnh.*Sx chip. Mt thit b kim tra trn ton wafer s check ng lot cc mu chip v cc hot ng c bn ca chic (die).*Sau mt my ct s phn l tm wafer mang y cc hon tt ra tng chic mt. *Nhng chic c kch thc vo khong vi centimeter. Di y l mt trong cc t chng ch mm.*Mt s ng dng: Truyn thng: in thoi t bo s, mng. My tnh: PC/Workstation, Chipset. Hng tiu dng: Game box, Camera s.