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Micorcontrollers 10ES42

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Question Bank Solutions

UNIT-1: MICROPROCESSOR AND MICROCONTROLLERS

1. What are the advantages of RISC and CISC processor architecture? (jan 08, july08)

CISC RISC

Emphasis on hardware Emphasis on software

Includes multi-clock

complex instructions

Single-clock,

reduced instruction only

Memory-to-memory:

"LOAD" and "STORE"

incorporated in instructions

Register to register:

"LOAD" and "STORE"

are independent instructions

Small code sizes,

high cycles per second

Low cycles per second,

large code sizes

Transistors used for storing

complex instructions

Spends more transistors

on memory registers

2. Distinguish between Harvard and Princeton architecture with diagram. (jan 08)

Princeton Architecture (Single memory interface)


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Harvard Architecture (Separate Program and Data Memory interfaces)

The same instruction (as shown under Princeton Architecture) would be executed as follows:

3. With a diagram list the specific features of 8051 ( jan08, july08, jan09, july09)

Features of 8051

The main features of 8051 microcontroller are:

RAM – 128 Bytes (Data memory)

ROM – 4Kbytes (ROM signify the on – chip program space)

Serial Port – Using UART makes it simpler to interface for serial communication.

Two 16 bit Timer/ Counter

Input/output Pins – 4 Ports of 8 bits each on a single chip.

6 Interrupt Sources

8 – bit ALU (Arithmetic Logic Unit)

Harvard Memory Architecture – It has 16 bit Address bus (each of RAM and ROM) and 8

bit Data Bus.

http://www.engineersgarage.com/tutorials/timers-8051-timer-programming-tutorial

http://www.engineersgarage.com/tutorials/interrupts-8051-interrupt-programming


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8051 can execute 1 million one-cycle instructions per second with a clock frequency of

12MHz.

This microcontroller is also called as “System on a chip” because it has all the features on a single

chip. The Block Diagram of 8051 Microcontroller is as shown in Figure 1.1

Figure 1.1 Block Diagram of 8051 Microcontroller

Memory Architecture

The 4 discrete types of memory in 8051 are:

Internal RAM – This memory is located from address 0 to 0xff. The memory

locations from 0x00 to 0x7F are accessed directly. The bytes from 0x20 to 0x2F are

bit-addressable. Loading R0 and R1 the memory location from 0x80 to 0xFF can

easily accessed.

Special Function Registers (SFR) – Located from address 0x80 to 0xFF of the

memory location. The same instructions used for lower half of Internal RAM can be

used to access SFR’s. The SFR’s are bit addressable too.


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Program Memory – This is read only memory which is located at address 0. With

the help of 16 bit Special Function Register DPTR, this memory can also save the

tables of constants.

External Data Memory – Located at address 0. The Instruction MOVX (Move

External) should be used to access the external data memory

4. Explain the oscillator circuit and timing diagram of 8051 microcontroller (jan08)

The heart of 8051 is the circuitry that generates the clock pulses by which all internal

operations are synchronized. Pins XTAL1 and XTAL2 are provided for connecting

resonator to form an oscillator. The crystal frequency is the basic internal frequency of the

microcontroller. 8051 is designed to operate between 1MHz to 16MHz and generally

operates with a crystal frequency 11.04962 MHz

The oscillator formed by the crystal, capacitor and an on-chip inverter generates a pulse

train at the frequency of the crystal. The clock frequency f establishes the smallest interval

to accomplish any simple instruction. The time taken to complete any instruction is called

as machine cycle or instruction cycle. In 8051 one instruction cycle consists of 6 states or

12 clock cycles, instruction cycle is also referred as Machine cycle.

5. Differentiate between microprocessor and microcontroller with respect to their

architecture and instructions (jan09, july09)

Microprocessor Microcontroller

Contains ALU, GPR, SP, PC, clock timing

& interrupt circuits

Contains circuitry of microprocessor

and in addition it has Rom RAM, I/O

devices, timers, Counters etc.

Has many instructions to move data

between memory and CPU

Has one or two instructions to move

data between memory and CPU

Has one or two bit handling instructions Has many bit handling instructions

Access time for memory & I/O devices is Access time for memory & I/O devices


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more is less

It has single memory for data and code Separate memory for data and code

Less no. of multifunctional pins More no. of multifunctional pins

6. Mention any two applications of 8051 microcontrollers ( jan09)

The 8051 has been in use in a wide number of devices, mainly because it is easy to integrate into

a project or build a device around. The following are the main areas of focus:

i. Energy Management: Efficient metering systems help in controlling energy usage in homes

and industrial applications. These metering systems are made capable by incorporating

microcontrollers.

ii. Touch screens: A high number of microcontroller providers incorporate touch-sensing

capabilities in their designs. Portable electronics such as cell phones, media players and gaming

devices are examples of microcontroller-based touch screens.

iii. Automobiles: The 8051 finds wide acceptance in providing automobile solutions. They are

widely used in hybrid vehicles to manage engine variants. Additionally, functions such as cruise

control and anti-brake system have been made more efficient with the use of microcontrollers.

iv. Medical Devices: Portable medical devices such as blood pressure and glucose monitors use

microcontrollers will to display data, thus providing higher reliability in providing medical results

7. Explain the memory organization in 8051. (june‟08, Dec‟11)

Internal RAM: The 128 bytes internal RAM is organized into 3 distinct areas.

1. 32 bytes from address 00h to 1fh that make up 32 working registers organized as 4

memory banks of 8 registers each. The 4 register banks are numbered 0 to 3 and are made

up of 8 registers named R0 to R7. Each register can be addressed by name or by its RAM

addresses. Thus R0 of bank3 is R0 (if bank3 is selected) or address 18h (where bank3 is

selected). Bits RS0 and RS1 in the PSW determine which bank of registers is currently in

use at any time when program is running. Register banks not selected can be used as

general purpose RAM. Bank0 is selected by default on reset.

2. A bit addressable area of 16 bytes occupies RAM byte addresses 20h to 2fh, forming total

of 128 bits. An addressable bit may be specified by its bit address of 00h to 7fh or 8 bits

may form any byte address from 20h to 2fh.For example bit address 4fh is also bit 7 of


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byte address 29h. Addressable bits are useful when the program need only remember a

binary event.

3. A general purpose RAM area above the bit area from 30h to 7f h, addressable as byte.

Internal ROM

8051 is organized so that data memory and program code memory can be two entirely

different physical memory entities. Each has the same address ranges. The internal

program ROM occupies code address space 000h to 0fffh. The PC is normally used to

address program code bytes from address 0000h to ffffh. Program addresses higher than

offfh which exceed the internal ROM capacity will cause the 8051 to automatically fetch

code bytes from external memory, addresses 00h to ffffh by connecting the external access

pin (EA) to ground.

UNIT 2: ADDRESSING MODES AND OPERATIONS


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1. Explain the following instructions with examples 1) MOVC (2) SJMP (3) JB

(4) DAA ( jan 08, jan‟10,dec‟11)

DA A Decimal adjustment of the accumulator according to BCD

code

MOVC

A,@A+DPTR

Moves the code byte relative to the DPTR to the

accumulator (address=A+DPTR)

JB bit,rel Jump if direct bit is set. Short jump.

SJMP rel Short jump (from –128 to +127 locations relative to the

following instruction)

2. Explain how stack is implemented in 8051 ( jan 08, jan 09)

The stack refers to an area of internal RAM that is used in conjunction with certain opcodes

to store and retrieve data quickly. The 8 bit Stack Pointer (SP) register is used by the 8051 to

hold internal RAM address that is called the top of the stack. The address in SP register is the

location in internal RAM where the last byte of the data was stored by stack operation.

When data is to be placed on to the stack, the SP increments before storing the data on the

stack so that the stack grows up as data is stored. Whenever data is retrieved from the stack,

the byte is read from the stack and then the SP decrements to point to the next available byte

of stored data.

Operation of the Stack and Stack Pointer: The SP is set to 07 when the 8051 is reset and

can be changed to any internal RAM address by the programmer. The stack is limited in

height to the size of internal RAM. The stack can overwrite valuable data in register banks, bit

addressable RAM and scratched pad RAM areas. It is programmer’s responsibility to make it

sure that the stack does not grow beyond predefined bounds. The stack is normally placed

high in the internal RAM by an appropriate choice of the number placed in SP register, to

avoid conflict with registers or RAM.

3. Explain the functions of the following pins of 8051 1) EA 2) ALE 3) RST (july 08)


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Pin 30: ALE Prior to reading from external memory, the microcontroller puts the lower

address byte (A0-A7) on P0 and activates the ALE output. After receiving signal from the

ALE pin, the external register (usually 74HCT373 or 74HCT375 add-on chip) memorizes

the state of P0 and uses it as a memory chip address. Immediately after that, the ALU pin

is returned its previous logic state and P0 is now used as a Data Bus. As seen, port data

multiplexing is performed by means of only one additional (and cheap) integrated circuit.

In other words, this port is used for both data and address transmission.

Pin 31: EA By applying logic zero to this pin, P2 and P3 are used for data and address

transmission with no regard to whether there is internal memory or not. It means that even

there is a program written to the microcontroller, it will not be executed. Instead, the

program written to external ROM will be executed. By applying logic one to the EA pin,

the microcontroller will use both memories, first internal then external (if exists).

Pin 9: RS logic one on this pin disables the microcontroller and clears the contents of

most registers. In other words, the positive voltage on this pin resets the microcontroller.

By applying logic zero to this pin, the program starts execution from the beginning.

4. Explain the different addressing modes of 8051. Give an example for each one of

them (july 08, jan 09)

(i) Immediate Addressing Mode

Ex: MOV A, #6AH

In general we can write MOV A, #data

This addressing mode is named as “immediate” because it transfers an 8-bit data immediately to

the accumulator (destination operand).


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The picture above describes the above instruction and its execution. The opcode for MOV A, #

data is 74H. The opcode is saved in program memory at 0202 address. The data 6AH is saved in

program memory 0203. (See, any part of the program memory can be used, this is just an

example) When the opcode 74H is read, the next step taken would be to transfer whatever data at

the next program memory address (here at 0203) to accumulator A (E0H is the address of

accumulator). This instruction is of two bytes and is executed in one cycle. So after the execution

of this instruction, program counter will add 2 and move to o204 of program memory.

Note: The „#‟ symbol before 6AH indicates that operand is a data (8 bit). If „#‟ is not present then

the hexadecimal number would be taken as address.

(ii) Direct Addressing Mode

This is another way of addressing an operand. Here the address of the data (source data ) is given

as operand..

MOV A, 04H

Here 04H is the address of register 4 of register bank#0. When this instruction is executed, what

ever data is stored in register 04H is moved to accumulator. In the picture below we can see,

register 04H holds the data 1FH. So the data 1FH is moved to accumulator.

http://www.circuitstoday.com/wp-content/uploads/2011/12/Immediate-Addressing-Mode.jpg


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As shown in picture above this is a 2 byte instruction which requires 1 cycle to complete.

Program counter will increment by 2 and stand in 0204. The opcode for instruction MOV A,

address is E5H. When the instruction at 0202 is executed (E5H), accumulator is made active and

ready to receive data. Then program control goes to next address that is 0203 and look up the

address of the location (04H) where the source data (to be transferred to accumulator) is located.

At 04H the control finds the data 1F and transfers it to accumulator and hence the execution is

completed.

(iii) Register Addressing Mode

In this addressing mode we use the register name directly (as source operand). An example is

shown below.

MOV A, R4

At a time registers can take value from R0,R1…to R7. You may already know there are 32 such

registers. So how you access 32 registers with just 8 variables to address registers? Here comes

the use of register banks. There are 4 register banks named 0, 1, 2 and 3. Each bank has 8

registers named from R0 to R7. At a time only one register bank can be selected. Selection of

register bank is made possible through a Special Function Register (SFR) named Processor Status

Word (PSW). PSW is an 8 bit SFR where each bit can be programmed. Bits are designated from

PSW.0 to PSW.7 Register banks are selected using PSW.3 and PSW.4 these two bits are known

as register bank select bits as they are used to select register banks. A picture below shows the

PSW register and the Register Bank Select bits with status.

http://www.circuitstoday.com/wp-content/uploads/2011/12/Direct-Addressing-Mode.jpg


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So in register direct addressing mode, data is transferred to accumulator from the register (based

on which register bank is selected).

So we see that opcode for MOV A, R4 is EC. The opcode is stored in program memory address

0202 and when it is executed the control goes directly to R4 of the respected register bank (that is

selected in PSW). If register bank #0 is selected then the data from R4 of register bank #0 will be

moved to accumulator. (Here it is 2F stored at 04 H). 04 H is the address of R4 of register bank

#0. Movement of data (2F) in this case is shown as bold line. Now please take a look at the dotted

line. Here 2F is getting transferred to accumulator from data memory location 0C H. Now

http://www.circuitstoday.com/wp-content/uploads/2011/12/Processor-Status-Word.jpg

http://www.circuitstoday.com/wp-content/uploads/2011/12/Register-Direct-Addressing-Mode.jpg


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understand that 0C H is the address location of Register 4 (R4) of register bank #1. Programmers

usually get confused with register bank selection. Also keep in mind that data at R4 of register

bank #0 and register bank #1 (or even other banks) will not be same. So wrong selection of

register banks will result in undesired output.

Also note that the instruction above is 1 byte and requires 1 cycle for complete execution. This

means using register direct addressing mode can save program memory.

(iv) Register Indirect Addressing Mode

So in this addressing mode, address of the data (source data to transfer) is given in the register

operand.

MOV A, @R0

Here the value inside R0 is considered as an address, which holds the data to be transferred to

accumulator.

Example: If R0 holds the value 20H, and we have a data 2F H stored at the address 20H, then the

value 2FH will get transferred to accumulator after executing this instruction. Got it? See the

picture below.

So the opcode for MOV A, @R0 is E6H. Assuming that register bank #0 is selected. So the R0

of register bank #0 holds the data 20H. Program control moves to 20H where it locates the data

2FH and it transfers 2FH to accumulator.

http://www.circuitstoday.com/wp-content/uploads/2011/12/Register-Indirect-Addressing-Mode.jpg


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This is a single byte instruction and the program counter increments 1 and moves to 0203 of

program memory.

Note: Only R0 and R1 are allowed to form a register indirect addressing instruction. In other

words programmer can must make any instruction either using @R0 or @R1. All register banks

are allowed.

(v) Indexed Addressing Mode

Well lets see two examples first.

MOVC A, @A+DPTR and MOVC A, @A+PC

where DPTR is data pointer and PC is program counter (both are 16 bit registers). Lets take the

first example.

MOVC A, @A+DPTR

The source operand is @A+DPTR and we know we will get the source data (to transfer) from this

location. It is nothing but adding contents of DPTR with present content of accumulator. This

addition will result a new data which is taken as the address of source data (to transfer). The data

at this address is then transferred to accumulator.

The opcode for the instruction is 93H. DPTR holds the value 01FE, where 01 is located in DPH

(higher 8 bits) and FE is located in DPL (lower 8 bits). Accumulator now has the value 02H. A 16

bit addition is performed and now 01FE H+02 H results in 0200 H. What ever data is in 0200 H

http://www.circuitstoday.com/wp-content/uploads/2011/12/Indexed-Addressing-Mode.jpg


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will get transferred to accumulator. The previous value inside accumulator (02H) will get replaced

with new data from 0200H. New data in the accumulator is shown in dotted line box.

This is a 1 byte instruction with 2 cycles needed for execution. The other example MOVC A,

@A+PC works the same way as above example. The only difference is, instead of adding DPTR

with accumulator, here data inside program counter (PC) is added with accumulator to obtain the

target address.

5. Mention the function of the following instructions of 8051 CPU: 1) MOVC

A,@A+DPTR 2)CJNE 3)MUL AB 4) DJNZ 5) A CALL (july 09)

MOVC

A,@A+DPTR

Moves the code byte relative to the DPTR to the accumulator

(address=A+DPTR)

CJNE

A,direct,rel

Compares direct byte to the accumulator and jumps if not

equal. Short jump.

MUL AB Multiplies A and B

ACALL

addr11 Absolute subroutine call

DJNZ Rn,rel Decrements register and jump if not 0. Short jump.

6. List out the different bit addressable SFR‟s available in 8051 ( july 09)

This memory area cannot be used as data memory, it is clear that if we write out of

control in the memory allocated to a special register, modify the behavior of the

microcontroller, resulting in unexpected results as the affected record. Although the

memory locations that are not assigned to a special register can be used to hold data, it is

not advisable to use, it has to bear in mind that these may be reserved and assigned to

special registers in other models or manufacturers of microcontrollers and our program

will conflict when changing model.


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The input and output ports also occupy a specific position or memory addresses. The

memory locations on the left side (80h, 88h, 90H ….) are reserved for routing bit so that

the concerned records may be accessed via this system.

The following table shows the layout of each record in 8051 and 8052 microcontroller.

F8H

FFH

F0H B *

F7H

E8

H EFH

E0h ACC *

E7H

D8

H DFH

D0

H PSW *

D7H

C8

H

T2CON

* #

RCAP2

L #

RCAP2

H #

TL2

#

TH

2 # CFH

C0h

C7H

B8

H IP *

BFH

B0h P3 *

B7H

A8h IE *

AFH

A0

H P2 *

A7H

98H SCON * SBUF

9FH

90H P1 *

97H

88h TCON

* TMOD TL0 TL1

TH

0

TH

1 8FH

80H P0 * SP DPL DPH

PCO

N 87H


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Registe

r Description

Addres

s Command bit or alternate function port

Reset

value

MSB

LS

B

ACC *

Accumulator

(Accumulato

r)

E0h E7 E6 E5 E4 E3 E2 E1 E0 00H

B * Register B

(Register B) F0H F7 F6 F5 F4 F3 F2 F1 F0 00H

DPTR:

Data Pointer

(Data

Pointer) (2

bytes)

DPH

High byte of

DPTR

(Data

pointer high)

83H

00H

DPL

Low byte of

DPTR

(Data

pointer low)

82H

00H

AF AE AD AC AB AA A9 A8

IE *

Enable

interrupts

(Interrupt

enable)

A8h EA - ET2 ES ET1 EX1 ET0 EX

0

0x000000

B

BF BE BD BC BB BA B9 B8

IP * Priority B8H - - PT2 PS PT1 PX1 PT0 PX0 0x000000


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interrupts

(Interrupt

priority)

B

87 86 85 84 83 82 81 80

P0 * Port 0 (Port

0) 80H AD7

AD

6

AD

5

AD

4 AD3 AD2 AD1

AD

0 FFH

97 96 95 94 93 92 91 90

P1 * Port 1 (Port

1) 90H - - - - - -

T2E

X T2 FFH

A7 A6 A5 A4 A3 A2 A1 A0

P2 * Port 2 (Port

2) A0H A15 A14 A13 A12 A11 A10 A9 A8 FFH

B7 B6 B5 B4 B3 B2 B1 B0

P3 * Port 3 (Port

3) B0h RD WR T1 T0 INT1

INT

0 TxD

Rx

D FFH

PCON1

Consumption

control

(Power

control)

87H SMOD - - - GF1 GF0 PD IDL 0xxxxxxx

B

D7 D6 D5 D4 D3 D2 D1 D0

PSW * Program

status D0H CY AC F0 RS1 RS0 OV - P 00H

7. Explain the different jump instruction in 8051. (June‟09)


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8. Mention the advantages of using subroutines.

(ii) Give the range of instructions SJMP, AJMP, LJMP.

(iii) Mention the differences between RET and RETI instructions (Dec'11)

Subroutine helps in executing a set of instructions repeatedly. The code size is reduced

SJMP: -128 to +127

AJMP: < 2K page

LJMP: within 64K

RET does not clear the flag bits, flag bits must be cleared manually whereas RETI clears

the flag bits.


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UNIT 3:8051 PROGRAMMING

1. How bit level XOR operations can be done in 8051 ( jan 08)

XRL A,Rn Exclusive OR register to accumulator

XRL A,direct Exclusive OR direct byte to accumulator

XRL A,@Ri Exclusive OR indirect RAM to accumulator

XRL A,#data Exclusive OR immediate data to accumulator

XRL direct,A Exclusive OR accumulator to direct byte

XORL

direct,#data Exclusive OR immediate data to direct byte

2. Write a subroutine to decrement the contents of DPTR ( jan 08)

mov a, dpl

dec a

mov dpl, a

3. Write a program to add 10 BCD numbers stored in successive memory locations

starting from 20H in internal RAM locations and store the result at address 40H and

41H (july08)

Mov r0, # 20h

Mov r1, #10

Mov a, r0

L1: Inc r0

Add a, @r0

DA A

Djnz r1, l1

Mov 40h, A


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4. write ALP for 8051 assume that register A has packed BCD, Write a program to

convert packed BCD to two ASCII n umbers and place them in R2 and R3 ( jan 09)

ORG 00H

SJMP 30h

ORG 30h

MOV R1, #50H

MOV A,@R1

MOV R2, A

ANL A, #0FH

ORL A, #30H

INC R1

MOV @R1, A

MOV A, R2

SWAP A

ANL A, #0FH

ORL A, #30H

INC R1

MOV @R1, A

HERE: SJMP HERE

END

5. Find the sum of values 79H, F5H, E2H put the sum in R0 and R5 (

jan 09)

Mov a, #79h

Addc a, #f5h

Addc a, #e2h

Mov r0, a

Mov r5, c


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6. Write an ALP to find square root of a numbers and store in R0

( july 09)

Mov r5, #n

Mov r0, #0

L1: Mov a, r0

Mov a,b

Inc r0

Mul ab

Cjne a,r5 , l1

Mov r0, b

UNIT 4: 8051 INTERFACING AND APPLICATIONS

1. Draw the block schematic of DAC 0808 interfaced to 8051 at port P1 and write an

8051 program to generate sine wave (june'08)

The digital inputs are converter to current Iout, and by connecting a resistor to the Iout pin, we can

convert the result to voltage. The total current Iout is a function of the binary numbers at the D0-

D7 inputs of the DAC0808 and the reference current Iref , and is as follows:

Usually reference current is 2mA. Ideally we connect the output pin to a resistor, convert this

current to voltage, and monitor the output on the scope. But this can cause inaccuracy; hence an

opamp is used to convert the output current to voltage. The 8051 connection to DAC0808 is as

shown in the figure below.


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Program:

ORG 0000H

AGAIN: MOV DPTR, #SINETABLE

MOV R3, #COUNT

UP: CLR A

MOVC A, @A+DPTR

MOV P1, A

INC DPTR

DJNZ R3, UP

SJMP AGAIN

ORG 0300H

SINETABLE DB 128, 192, 238, 255, 238, 192, 128, 64, 17, 0, 17, 64, 128

END

2. How to interface DC motor to 8051 using opto insulator? Write a C program to move

DC motor with 25% duty cycle pulse

(june'08)

The DC motor is another widely used device that translates electrical pulses into

mechanical movement. Motor has 2 leads +ve and – ve , connecting them to a DC voltage supply

moves the motor in one direction. On reversing the polarity rotates the motor in the reverse

direction. Basic difference between Stepper and DC motor is stepper motor moves in steps while

DC motor moves continuously. Another difference is with stepper motor the number of steps can

be counted while it is not possible in DC motor. Maximum speed of a DC motor is indicated in

rpm. The rpm is either with no load it is few thousands to tens of thousands or with load rpm

decreases with increase in load.

Voltage and current rating: Nominal voltage is the voltage for a motor under normal condition. It

ranges from 1V to 150V. As voltage increases, rpm goes up. Current rating is the current

consumption when the nominal voltage is applied with no load that is 25mA to a few amperes. As

load increases, rpm increases, unless voltage or current increases implies torque increases. With

fixed voltage, as load increases, power consumption of a DC motor is increased.

Unidirectional Control:

Figure 3 shows the rotation of the DC motor in clockwise and anticlockwise direction.

Figure 3: DC motor rotation


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Bidirectional Control:

(a) Motor not running (b) Clockwise direction

3. Show an interface of 8051 controller with a stepper motor drive circuit and explain

its principles of operation (Dec'08, June „09, June „11)

Step angle:

Step angle is defined as the minimum degree of rotation with a single step.

No of steps per revolution = 360° / step angle

Steps per second = (rpm x steps per revolution) / 60

Example: step angle = 2°

No of steps per revolution = 180

As discussed earlier the coils need to be energized for the rotation. This can be done by sending a

bits sequence to one end of the coil while the other end is commonly connected. The bit sequence

sent can make either one phase ON or two phase ON for a full step sequence or it can be a

combination of one and two phase ON for half step sequence. Both are tabulated below.

Full Step:

Two Phase ON

One Phase ON


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4. Explain the registers and pins of LCD and write an ALP to display message "YES"

as LCD displays (June‟09)


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ORG 0H

MOV A,#38H ;INIT. LCD 2 LINES, 5X7 MATRIX

ACALL COMNWRT ;call command subroutine

ACALL DELAY ;give LCD some time

MOV A,#0EH ;display on, cursor on



MOV A,#01 ;clear LCD



MOV A,#06H ;shift cursor right



MOV A,#86H ;cursor at line 1, pos. 6



MOV A,#’Y’ ;display letter Y

ACALL DATAWRT ;call display subroutine


MOV A,#’E’ ;display letter E



MOV A,#’S’ ;display letter S


AGAIN: SJMP AGAIN ;stay here

COMNWRT: ;send command to LCD

MOV P1,A ;copy reg A to port 1

CLR P2.0 ;RS=0 for command

CLR P2.1 ;R/W=0 for write

SETB P2.2 ;E=1 for high pulse


CLR P2.2 ;E=0 for H-to-L pulse

RET

DATAWRT: ;write data to LCD

MOV P1,A ;copy reg A to port 1

SETB P2.0 ;RS=1 for data

CLR P2.1 ;R/W=0 for write

SETB P2.2 ;E=1 for high pulse


CLR P2.2 ;E=0 for H-to-L pulse

RET

DELAY:

MOV R3,#50 ;50 or higher for fast CPUs

HERE2: MOV R4,#255 ;R4 = 255

HERE: DJNZ R4,HERE ;stay until R4 becomes 0


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DJNZ R3,HERE2

RET

END

5. Interface ADC 0804 to 8051 and write a program to read analog data and display the

converted data at port 2. (June‟11)

Steps to Program ADC0804

1. Select an analog channel by providing bits to A, B, and C addresses.

2. Activate the ALE pin. It needs an L-to-H pulse to latch in the address.

3. Activate SC (start conversion) by an H-to-L pulse to initiate conversion.

4. Monitor EOC (end of conversion) to see whether conversion is finished.

5. Activate OE (output enable) to read data out of the ADC chip. An H-to-L pulse to the OE pin

will bring digital data out of the chip.

6. Interface a 4x4 keys keyboard to 8051 and write an ALP to send the key code to port

P1 whenever a key pressed. (Dec'11)


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Algorithm for detection and identification of key activation goes through the following

stages:

1. To make sure that the preceding key has been released, 0s are output to all rows at once,

and the columns are read and checked repeatedly until all the columns are high

When all columns are found to be high, the program waits for a short amount of time

before it goes to the next stage of waiting for a key to be pressed

2. To see if any key is pressed, the columns are scanned over and over in an infinite loop

until one of them

has a 0 on it

Remember that the output latches connected to rows still have their initial zeros (provided

in stage 1), making them grounded

After the key press detection, it waits 20 ms for the bounce and then scans the columns

again

(a) It ensures that the first key press detection was not an erroneous one due a spike noise

(b) The key press. If after the 20-ms delay the key is still pressed, it goes back into the

loop to detect a real key press

3. To detect which row key press belongs to, it grounds one row at a time, reading the

columns each time.

If it finds that all columns are high, this means that the key press cannot belong to that

row. Therefore, it grounds the next row and continues until it finds the row the key press

belongs to

Upon finding the row that the key press belongs to, it sets up the starting address for the

look-up table holding the scan codes (or ASCII) for that row

9. To identify the key press, it rotates the column bits, one bit at a time, into the carry flag

and checks to see if it is low

Upon finding the zero, it pulls out the ASCII code for that key from the look-up table

otherwise, it increments the pointer to point to the next element of the look-up table


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UNIT 5: TIMER & COUNTER PROGRAMMING IN 8051

1. Find the value of TH1 if the timer1 is used in timer mode2 to generate a baud rate of

4800. Assume appropriate oscillator frequency. ( jan 08)

#include <reg51.h>

#include <stdio.h>

static unsigned long overflow_count = 0;

void timer0_ISR (void) interrupt 1

{

overflow_count++; /* Increment the overflow count */

}

void main (void)

{

TMOD = (TMOD & 0xF0) | 0x01; /* Set T/C0 Mode */

ET0 = 1; /* Enable Timer 0 Interrupts */

TR0 = 1; /* Start Timer 0 Running */

EA = 1; /* Global Interrupt Enable */

while (1)

{

}

}

2. Distinguish counting and timing requirements, explain the modes of operation of

timer/counter of 8051 with diagram. ( jan 08, july 08, july 09)

M1 M0 Mode Description

0 0 0 Use the THX register as an 8-bit counter and the TLX as a 5-bit counter.

0 1 1 Use the THX register as an 8-bit counter and the TLX as an 8-bit counter.

1 0 2 Use only the TLX register as an 8-bit counter.


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1 1 3 In modes 0 - 2, Timers 0 and 1 may be programmed independently.

In mode 3:

Timer 0 in mode 3 becomes two separate 8-bit counters.

Timer 1 in mode 3 may still be used, but will generate no interrupts.

3. Write a program to generate a symmetric square wave of frequency 2Khz if crystal

of frequency 11.0592MHz is used ( july 08)

Let initial, amplitude of the square wave be 2.5v (7F) and frequency count 100.

Output the values 00h (off) and 7fh (on) Values through P0.

If amplitude key is pressed then increase the voltage in steps of 0.15v (8).

If the frequency key is pressed increment the count in steps of 50. If the count exceeds

1000 reset it back to 100.

Every time amplitude and frequency changes output the value through P0 and note the

waveform on CRO.

4. Explain the timer structures of 8051 with TMOD register ( jan 09)

TMOD (89h) SFR

Bit Name Explanation of Function

7 GATE1

When this bit is set the timer will only run when INT1

(P3.3) is high. When this bit is clear the timer will run

regardless of the state of INT1.

6 C/T1

When this bit is set the timer will count events on T1

(P3.5). When this bit is clear the timer will be

incremented every machine cycle.

5 T1M1 Timer mode bit (see below)


3 GATE0 When this bit is set the timer will only run when INT0


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(P3.2) is high. When this bit is clear the timer will run

regardless of the state of INT0.

2 C/T0

When this bit is set the timer will count events on T0

(P3.4). When this bit is clear the timer will be

incremented every machine cycle.



The modes of operation are:

TxM1 TxM0 Timer Mode Description of Mode

0 0 0 13-bit Timer.

0 1 1 16-bit Timer

1 0 2 8-bit auto-reload

1 1 3 Split timer mode

5. Assume that XTAL=11.0592MHz. Write a program to generate a square wave of

2KHz on P1.5 (jan‟09)

COUNT=Delay/ 1.085µ

MOV TMOD, #01H

MOV TH0, # LSB COUNT

MOV TL0, #MSB COUNT

CPL P1.5

ACALL DELAY

SJMP NEXT

DELAY: SETB TR0

AGAIN: JNB TF0, AGAIN

CLR TF0

CLR TR0

RET


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6. Explain IE and IP register formats (june‟09)

Interrupt Enable Register

Interrupt Priority Register

IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0

- - PT2 PS PT1 PX1 PT0 PX0

- - - BC BB BA B9 B8

7. Compare polling and interrupts. What are the steps microcontroller performs upon

activation of interrupt (june‟11)

Polling is a process where the processor checks for the device status using Round robin

algorithm, whereas in the interrupt method, device informs the processor for the service

request.

1. The programmer enables interrupt circuit action by setting interrupt enable flag bit to 1.

The 8051 has a total of five interrupt sources of each of which may generate an interrupt

signal.

2. External or internal circuit action causes one of interrupt signals to be generated.

3. The CPU finishes the current instruction, pushes the PC on the stack, and replaces the

original PC contents with the address of the first instruction of the program code for the

particular source that caused the interrupt. All the other interrupting source enable bits are

temporarily disabled.

4. The interrupt program executes. While executing, the interrupt program must reset internal

flag that generated the interrupt signals.

5. At the end of the interrupt program, a RETI instruction resets all the interrupt-enable

circuitry and pops the original PC contents from the stack back into the PC. The CPU

resumes executing the interrupted program.

IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0

EA - ET2 ES ET1 EX1 ET0 EX0

AF AE AD AC AB AA A9 A8


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UNIT 6: SERIAL COMMUNICATION PROGRAMMING IN 8051

1. Explain the different steps to receive data serially using 8051 ( july 08)

2. Write a program for 8051 to transfer the message “GOOD LUCK” serially at baud

rate of 9600, 8bit data with 1 stop bit. Do this continuously ( jan09, july09)

ORG 0000H

MOV TMOD, #20H

MOV TH1, #0FDH (count for given baud rate)

MOV SCON, #50H

SETB TR1

MOV DPTR, #MESSG

NEXT: CLR A

MOVC A,@A+DPTR

JZ HERE

ACALL SEND

INC DPTR

SJMP NEXT

HERE: SJMP HERE

SEND : MOV SBUF, A

BACK: JNB TI, BACK

CLR TI

RET

END

MESSG:DB “GOOD LUCK”, 0


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3. What is serial communication? How is this achieved with 8051 using RS232

standards ( july 09)

To establish a serial communication link between the PC and the 8051. Serial communication is

often used either to control or to receive data from an embedded microprocessor. Serial

communication is forms of I/O in which the bits of a byte begin transferred appear one after the

other in a timed sequence on a single wire. Serial communication has become the standard for

intercomputer communication. In this lab, we'll try to build a serial link between 8051 and PC

using RS232.

RS232C:

The example serial waveforms in Fig 1 show the waveform on a single conductor to transmit a

byte (0x41) serially. The upper waveform is the TTL-level waveform seen at the transmit pin of

8051. The lower waveform shows the same waveform converted to RS232C levels.

As shown in Fig 1, each byte is preceded by a start bit and followed by one stop bit. The start and

stop bits are used to synchronize the serial receivers. The data byte is always transmitted least-

significant-bit first. The bits are transmitted at specific time intervals determined by the baud

rate of the serial signal. Error-free serial communication requires that the baud rate, number of

data bits, number of stop bits, and presence or absence of a parity bit be the same at the

transmitter and at the receiver.

Fig 1. Serial Waveforms

Using the Serial Port:

8051 provides a transmit channel and a receive channel of serial communication. The transmit

data pin (TXD) is specified at P3.1, and the receive data pin (RXD) is at P3.0. The serial signals


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provided on these pins are TTL signal levels and must be boosted and inverted through a suitable

converter(LT1130CN is used in this lab) to comply with RS232 standard.

All modes are controlled through SCON, the Serial CONtrol register. The SCON bits are defined

as SM0, SM1, SM2, REN, TB8, RB8, TI, RI from MSB to LSB. The timers are controlled using

TMOD, the Timer MOD register, and TCON, the Timer CONtrol register.

4. Explain the format of SCON register in details ( july 09)

SM1 and SM0 determine the framing of data.

SCON.6 (SM1) and SCON.7 (SM0)

Only mode 1 is compatible with COM port of PC.

SM1 SM0 Mode Operating Mode Baud Rate

0 0 0 Shift register Fosc./12

0 1 1 8-bit UART Variable by Tmer1

1 0 2 9-bit UART Fosc./64 or Fosc./32

1 1 3 9-bit UART Variable

SM2: used for multiprocessor communication.

REN: set or cleared by software to enable/disable reception.

TB8: Transmitted bit 8, not widely used.

RB8: Received bit 8.

TI: Transmit interrupt flag –set by the hardware at the beginning of the stop bit in

mode 1, must be cleared by software.

RI: Receive interrupt flag –set by the hardware halfway through the stop bit time in

mode1, must be cleared by software.

5. Explain the function of RS232C pins of DB-9 connector (dec‟11)

DTR (data terminal ready):- When terminal is turned on, it sends out signal DTR to indicate

that it is ready for Communication DSR (data set ready).When DCE is turned on and has gone

through the self-test, it assert DSR to indicate that it is ready to communicate

RTS (request to send):- When the DTE device has byte to transmit, it assert RTS to signal

the modem that it has a byte of data to transmit


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CTS (clear to send):- When the modem has room for storing the data it is to receive, it sends out

signal CTS to DTE to indicate that it can receive the data now

DCD (data carrier detect):- The modem asserts signal DCD to inform the DTE that a valid

carrier has been detected and that contact between it and the other modem is established

RI (ring indicator):- An output from the modem and an input to a PC indicates that the telephone

is ringing. It goes on and off in synchronous with the ringing sound.

6. List the advantages of serial communication over parallel communication. (june‟08)

Computers transfer data in two ways, namely: Parallel and serial

Parallel Communication

Often 8 or more lines (wire conductors) are used to transfer data to a device that is only a few feet

away

Serial Communication

To transfer to a device located many meters away, the serial method is used

The data is sent one bit at a time


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UNIT 7: MOTIVATION FOR MSP430MICROCONTROLLERS

1. With a neat block diagram explain the features of MSP430 microcontroller

(june‟12)

Low power consumption:

0.1 microA for RAM data retention;

0.8 microA for real time clock mode operation;

250 microA/MIPS at active operation.

Low operation voltage (from 1.8 V to 3.6 V).

< 1 micros clock start-up.

< 50 nA port leakage.

Zero-power Brown-Out Reset (BOR).

On-chip analogue devices:

10/12/16-bit Analogue-to-Digital Converter (ADC);

12-bit dual Digital-to-Analogue Converter (DAC);

Comparator-gated timers;

Operational Amplifiers (OP Amps);

Supply Voltage Supervisor (SVS).

16 bit RISC CPU:

Instructions processing on either bits, bytes or words;

Compact core design reduces power consumption and cost;

Compiler efficient;

27 core instructions;

7 addressing modes;

Extensive vectored-interrupt capability.

Flexibility:

Up to 256 kB In-System Programmable (ISP) Flash;

Up to 100 pin options;

USART, I2C, Timers;

LCD driver;

Embedded emulation.


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2. Explain the clock system of MSP430 (june‟12)

The MSP430 devices have a clock system that allows the CPU and the peripherals to operate

from different clock sources. The system clocks depend on the particular device in the MSP430

family:

MSP430x2xx: The Basic Clock Module+ (BCM+) is composed of one or two

oscillators (depending on the device) and is able to work with external crystals or

resonators, in addition to the internal

digitally controlled oscillator (DCO). It allows a working frequency up to 16 MHz, lower power

consumption and lower internal oscillator start up time.

MSP430x4xx: The system clock is defined by the Frequency Locked Loop (FLL+).

This system is composed of one or two oscillators (depending on the device), and is

able to work with external crystals or resonators, as well as the internal Digitally

Controlled Oscillator (DCO). The DCO is adjusted and controlled by hardware,

providing multiple working frequencies from an external

low frequency oscillator. The clock sources from these oscillators can be selected to generate


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a range of different clock signals: Master clock (MCLK), Sub-system main clock (SMCLK) and

auxiliary clock (ACLK). Each of these clock signals can be internally divided by 1, 2, 4 or 8,

before being made available to the CPU and peripheral devices:

MCLK: Can be generated by the DCO (but can also be fed by the crystal oscillator),

which can be activated and reach stability in less than 6 microsec. It can be used by the

CPU and high-speed peripherals;

SMCLK: Used as alternative clock source for peripherals;

ACLK: Background real-time clock with self wake-up function for low power modes

(32.768 kHz watch crystal). It is always fed by the crystal oscillator.

UNIT 8: ON-CHIP PERIPHERALS

1. Explain the working of watch dog timer in MSP430. (june‟12)

The 16-bit watchdog timer (WDT) module can be used as a:

Processor supervisor: In supervision mode, the main function of the WDT is to

supervise the correct operation of the application software. If a problem occurs with

the software application that

causes the software to hang or enter an infinite loop, the selected time interval in the

watchdog timer is exceeded and the WDT performs a system reset: Power Up Clear

(PUC). The procedure in this mode consists of performing an interrupt request on

counter overflows. Under normal operating conditions, the watchdog timer would be

reset by program code before its timer expires and would

Therefore inhibit the PUC operation.

Interval timer: This module can be configured as an independent interval timer, to

perform a “standard” periodic interrupt on counter overflow, for example, to drive an

event scheduler (a low-cost operating system). The 16-bit upper counter (WDTCNT)

is not directly accessible by software. Its control and the interval time are selected

through Watchdog Timer Control Register (WDTCTL). This counter can use the clock

signal from ACLK or SMCLK, by defining the appropriate WDTSSEL bit. The WDT

mode is selected by the WDTTMSEL bit in the WDTCTL register. After a PUC

condition, the WDT module is configured in supervision mode with approximately 32


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msec initial time interval, using DCOCLK. The user should define, stop or clear the

WDT before the time interval expires, to prevent a new PUC.

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