quasi floating-gate mos transistor -...
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CHAPTER 3
QUASI FLOATING-GATE MOS TRANSISTOR
3.1 Introduction
The Floating–Gate MOSFET (FGMOS) has been extensively used for low voltage
analog applications by virtue of its unique feature of lowering the effective threshold
voltage from its conventional value with the application of a bias voltage [43]. This
voltage is applied at one of its multi-input terminals through a large capacitance keeping
other inputs for signal application. However, the need of large capacitance for threshold
voltage programmability increases the silicon area requirement, reduces the effective
transconductance and gain-bandwidth (GB) product besides degrading the frequency
response of the resultant circuits [34, 43]. Moreover, FGMOS structure has a tendency
to trap a significant amount of charge during fabrication process which may lead to dc
offset problem. Such shortcomings of FGMOS based structures go off with a slight
modification in its structure resulting into a new device known as quasi floating-gate
MOSFET (QFGMOS) [97-103]. This new device for low voltage analog circuits was
introduced by Carlos Urquidi et al. as reported in the year 2002 [106].
In QFGMOS, the floating-gate is weekly connected to the appropriate supply
rail through a large value resistor which can be implemented by a reverse biased diode
connected MOSFET, thus, eliminating the need of large valued capacitance as required
in FGMOS. As a result, the required chip area reduces and frequency response also
improves in QFGMOS. Further, the connection of large valued resistor at the gate of
QFGMOS to either of the supply rails eliminates the problem of trapped charge on
floating gate and simultaneously, minimizing the supply voltage requirements [97].
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Since its inception, QFGMOS has been extensively used in number of
applications, replacing FGMOS in many low voltage analog circuits. The experimental
validation of QFGMOS was done by designing a CMOS mixer with 0.7 V input signal
swing operating at a supply voltage of 0.8 V [106]. The theoretical foundation and
practical aspects of QFG transistors were discussed by Jaime Ramirez Angulo et al. in
reference [97] where it has been applied in the design of very low voltage feed forward
topologies like analog switches, mixers programmable gain amplifiers track and hold
circuits and D/A converters. Ultra low voltage operational amplifier based on QFG
transistors was designed by Le-ning Ren et al. with open loop gain of 76.5 dB and gain
band width of 2.98 MHz [99]. Besides its applications in voltage mode circuits, QFG
transistor has also been found useful in current mode circuits like current conveyor, and
differential voltage current conveyor (DVCC) [107-109]. The implementation of QFG
transistors has been done by providing a weak electrical connection between the
floating-gate in FGMOS and power supply rails through a large or quasi-infinite
resistance (QIR). Several ways have been proposed to implement the required QIRs
[100].
A QFGMOS transistor biased in triode region was recently used to implement a
programmable resistor and it showed better linearity when compared to the
conventional fixed gate voltage MOS transistor [102]. The theoretical analysis of
QFGMOS linear resistors has also been presented [103]. Besides being employed in the
implementation of programmable linear resistors, QFGMOS biased in triode region was
also used in the design of tunable transconductors [104-105].
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3.2 Quasi Floating-Gate MOSFET
The equivalent circuit of the N-input N-type QFGMOS is shown in Fig. 3.1.
Fig. 3.1 Equivalent circuit of QFGMOS
The structure of QFGMOS is very much similar to that of FGMOS where signal
inputs are also capacitively coupled to the floating gate. In QFGMOS we do not require
a large biasing capacitor meant for threshold voltage tuning as required in FGMOS.
Instead, we connect the floating gate through a very large resistance to either of the
supply rails. For practical purposes, the quasi floating-gate (QFG) of NMOS transistor
is tied to VDD through a reverse-biased diode-connected PMOS transistor which acts as a
large value resistor whereas the QFG of PMOS transistor is tied to VSS through a
reverse-biased diode-connected NMOS transistor [37]. This pull-up (pull-down) resistor
sets the dc voltage at QFG to either power rails, thus, eliminating the problem due to
accumulated charge on floating gate during fabrication process and also reduces the
supply voltage requirements. Further, the use of large resistance makes the QFG
effectively floating for low frequency signals, thus, unaffecting the ac operation for
signals of this frequency range. Moreover, the limitations of FGMOS get eliminated as
there is no need of large biasing capacitor resulting in small chip area and improved
frequency response [97-98].
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3.2.1 Large-Signal Model
The large-signal model of QFGMOS can be obtained by modifying the equations that
describe the operation of the conventional MOSFET.
The expression for voltage at the gate of QFGMOS ( GV ) can be obtained by
modifying the corresponding equation [2.2] of FGMOS and is given by:
( ) ( ) ( ) ( ) 01
=−+−+−+−∑=
FGBGBGDGDGSGsGin
N
i
i VVCVVCVVCVVC (3.1)
where iC represent the capacitance between the gate of QFGMOS and multiple-input
gates and iV represent the voltages applied on the input gates. GBGDGS CCC &, denote the
capacitances from gate to source, drain and bulk respectively whereas BDS VVV &,
represent the voltages on the source, drain and bulk respectively.
The voltage at the gate of QFGMOS (VG) in Fig.3.1 can be expressed as
TotalLeak
TotalLeak
inGCsR
CsRVV
+=
1 (3.2)
where
'
1
GDGBGDGS
N
i
iTotal CCCCCC ++++=∑=
(3.3)
and
+++= ∑
=
N
i
BGBDGDSGSii
Total
in VCVCVCVCC
V1
1 (3.4)
Now Eq. (3.2) becomes
+
+++= ∑
= TotalLeak
TotalLeakN
i
BGBDGDSGSii
Total
GCsR
CsRVCVCVCVC
CV
1
1
1
(3.5)
We observe that for the input signals QFGMOS acts as high-pass filter whose cut-off
frequency ( ) 12
−
TotalLeakCRπ becomes very low. Therefore, for very low frequencies,
Eq. (3.5) becomes a weighted average of the ac input voltages determined by
capacitance ratios plus some parasitic terms. The pull-up resistor (RLeak) sets the gate to
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a dc voltage equal to the positive rail to which an ac voltage given by Eq. (3.5) is
superimposed. Hence, the gate voltage can become larger than VDD. Similarly, for a P-
type QFGMOS, a pull-down resistor sets the dc gate voltage to VSS, which is
implemented by a reverse-biased p-n junction of a NMOS transistor in cut-off region
[37].
In a two-input QFGMOS, we apply signal voltage (V1) to one gate termed as the signal
gate and supply voltage (VDD) through a large value resistor to another gate. Now, the
voltage on gate of QFGMOS for a two-input QFGMOS with 0== BS VV is given as:
D
Total
GDDD
Total
GD
Total
G VC
CV
C
CV
C
CV ++=
'1
1 (3.6)
The drain current (ID) of the QFGMOS in ohmic region is obtained by substituting
Eq. (3.6) for GV as:
( ) DSDS
TGSD VV
VVI
−−=
2β
DS
DS
TDS
Total
GD
DD
Total
GD
Total
D VV
VVC
CV
C
CV
C
CI
−
−
++=
2
'1
1β
(3.7)
where
=
L
WCOXnµβ
is the transconductance parameter.
Similarly, the drain current of the QFGMOS in saturation region is given by substituting
Eq. (3.6) for GV as:
( )2
2TFGD VVI −=
β
2
11 '
2
−
+= TDD
Total
GD
Total
D VVC
CV
C
CI
β
(3.8)
2
1
21
2
12
−−=
K
VKVVK DDTβ
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[ ]2
1
2
12
TeffVVK −=β
(3.9)
where
1
2
K
VKVV DDT
Teff
−=
, TotalC
CK 1
1 =
, Total
GD
C
CK
'2 =
(3.10)
Eq. (3.10) reveals that the effective threshold voltage of QFGMOS is lower than the
threshold voltage (VT) of the conventional MOSFET.
3.2.2 Small-Signal Model
The equations (3.7 & 3.8) form the large signal model of QFGMOS. Such a model
proves essential in analysing circuits in which the input signal significantly disturbs the
operating point, particularly if non-linear effects are of concern. But if the perturbation
in operating point is small, a small signal model may be used.
The small-signal (high frequency) model of QFGMOS is obtained by adding the
parasitic capacitances to the dc model. The small-signal model, so derived for two-input
QFGMOS is shown in Fig. 3.2.
Fig. 3.2 High frequency model of QFGMOS
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It can be further simplified by assuming VBS = 0 which eliminates CSB, CGB and CDB as
shown in Fig. 3.3. However, at low frequencies, the equivalent model will become
similar to that of a conventional MOSFET.
Fig. 3.3 Simplified high frequency model of QFGMOS
The effective transconductance of QFGMOS )( .,effmg is given by:
m
Total
effm gC
Cg
= 1
., (3.11)
where mg is the transconductance seen from QFG. The mg of QFGMOS )( .,effmg is more
than that of FGMOS because of less value of )( .TotalC but less than conventional
MOSFET by a factor of ( )TotalCC1 , resulting in low gain circuits.
The transition frequency of a two-input QFGMOS ( .,effTf ) is given as [8]:
−+
= ..
1
1
1
2.,2
5.1effTD
GD
Total
n
effT VVC
CV
C
C
Lf
π
µ (3.12)
3.2.3 PSpice Simulation Model
The circuit simulators like PSpice may also be used to verify the behavior of QFGMOS
structures. The PSpice simulation model of QFGMOS can be obtained by introducing
some electrical components to the standard MOS models as was done for FGMOS so as
to emulate the QFGMOS behavior.
The equivalent circuit of QFGMOS as shown in Fig. 3.1 contains many
capacitors between its various terminals. All these capacitors need to be bypassed by
G
C1 DCGD
gmVG
goCGS+C,GD
QFG
S
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very high valued resistors to avoid the problem of floating nodes during simulation. The
values of resistors and capacitors are chosen in such a way that the corresponding time
constants become the same [1-2, 17]. Now, the final model of multi-input QFGMOS
suitable for PSpice simulations is shown in Fig. 3.4.
Fig. 3.4 Model of multi-input QFGMOS
The simulation model of QFGMOS of Fig. 3.4 has been used to simulate the
characteristics of QFGMOS transistor shown in Fig. 3.5.
Fig. 3.5 QFGMOS transistor
For simulation of characteristics, we have choosen C1 = 0.1 pF, R1 = 200 MΩ, and W/L
of M1 = 39 µm/0.13 µm and W/L of M2 = 1.3 µm/0.13 µm at supply voltage of ± 0.5 V.
C1
C2
CN
C’GD
CGS
CGB
CGD
RLeakV1
VDD
V2
S
VN
D
QFG
R1
R2
RN
RGD
RGB
RGS
B
VDD VD
VS
M1
M2C1
R1
Vin
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The drain characteristics of QFGMOS for different values of input signal are shown in
Fig. 3.6.The output resistance of QFGMOS varies from 0.5 kΩ at Vin of 0.5 V to 11 kΩ
at Vin of -0.1 V.
Fig. 3.6 Drain characteristics of QFGMOS
The comparative transfer characteristics of QFGMOS, FGMOS and conventional MOS
are shown in Fig. and 3.7.
Fig. 3.7 Transfer characteristics of QFGMOS
As evident from the figure, the threshold voltage in a QFGMOS transistor is less than
the threshold voltage of conventional MOSFET. It is because of the fact that at same
value of input voltage say 400 mV QFGMOS conducts more current (109 µA) as
compared to conventional MOS (106 µA). Further, the threshold voltage of QFGMOS
transistor is more than the threshold voltage of FGMOS because of the presence of bias
voltage (Vbias) the gate of FGMOS.
0
2
4
6
8
10
12
14
-0.5 -0.3 -0.1 0.1 0.3 0.5
Ou
tpu
t cu
rrent , m
A
Output voltage, V
Vin = 0.5V
Vin = 0.3V
Vin = 0.1V
Vin = -0.1V
0
2
4
6
8
-0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
Ou
tpu
t cu
rrent,
mA
Input voltage, V
ConventionalMOS
QFGMOS
FGMOS
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3.3 Conclusion
In this chapter, we have presented the quantitative analysis of quasi floating-gate
MOSFET showing its advantages and suitability for low voltage applications vis-a-vis
its FGMOS counterpart. The large signal and small signal model of QFGMOS is
derived based on the conventional MOSFET. PSpice simulation model of QFGMOS
has been presented to simulate the drain characteristics of QFGMOS which are found to
be similar to the drain characteristics of conventional MOSFET and FGMOS. The
transfer characteristics of QFGMOS are also compared with that of conventional
MOSFET and FGMOS. It is found that the threshold voltage in a QFGMOS transistor is
less than the threshold voltage of conventional MOS but more than the threshold
voltage in FGMOS.