qualification of pcb fabricators / standard loss tangent laminates

IBM PCB Symposium

April 20 & 21, 2005

Fishkill Research ParkBldg 600

Hopewell Jct., NY

IBM PCB Symposium April 20 & 21, 2005

Day 1

Adjourn & other activities

05:00 - 06:30Poster

03:25-05:00Franz Gisin, Sanmina-SCIGeorge Katopis, DE, IBM-STGSteve Rosser, EITodd Takken, IBM, Yorktown ResearchEd Sayre, North East Systems AssociatesLei Shan, IBM, Yorktown ResearchKen Willis, CadenceKen Taylor, Polar Instruments

Panel discussionThe purpose of this panel is to discuss the best designpractices and tradeoffs for implementing these interfacesand which PCB technology developments give the mostleverage for maximizing the frequencies or minimizingthe bit error rate these interfaces can attain.

03:10-03:25Dale Becker, IBM-STGAttenuation sources, Attenuation reductionand wiring challenges

Dale BeckerChairperson & Moderator02:50-03:10Break

02:20-02:50Moises Cases, IBM- xSeriesImpact of Embedded Passive onPerformance and Signal Integrity

01:50-02:20Sidney Clouser, GouldNon Classical conductor losses due tocopper foil roughness and treatment

01:20-01:50Voya Markovich, EIPCB Technology Challenges & ApproachesBruce ChamberlinSession Chairperson

12:20-01:20Lunch

11:50-12:20Alina Deutsch, IBM-YKT ResearchTime-Domain Characterization of PrintedCircuit Boards for Multi-GHz Operation

11:20-11:50Gisbert Thomke, IBM- zSeriesPD Challenges for high speed

10:50-11:20Ed Sayre, NESAGigabit Dielectric Material Studies - LowLoss Material Comparisons andPerformance Rankings

10:30-10:50Break10:00-10:30Jack Fisher, IPCIPC Technology Roadmap09:30-10:00Bruce Chamberlin, IBM-ISCTechnology Requirements09:00-09:30Cas DeCusatis, IBM-STGServer System Overview08:30-09:00Katharine Frase, VP Key note speaker

Jim MayerleSession Chairperson08:15-08:30Ahmad KatnaniAdmin, logistic remarks08:00-08:30Registration

TimePresenterTopic


IBM Systems & Technology Group

© 2004 IBM Corporation

IBM PCB SymposiumKeynote Address

Dr. Katharine Frase Vice President, Worldwide Packaging and TestApril 20, 2005

1 04/15/05


© 2004 IBM Corporation04/20/2005

EnvironmentalProduct Trends

Scale UP

Scale OUTGames RuleThe Great Convergence of Everything IT Theory

The technology cosmos

Power Supply

Co-designfor performancefor cost

Chip Carrier trends

Power Management

Product QualityReliabilityQual methodsQuality mgmt

PbFree

ConnectorsOptical?Fine pitch

Panel trends

Moore's law: slowing but not deadFaster devices

finer lithothinner oxides, low K, etcVt lowerLeakage higher

Cost per circuit decreasesInnovation to compensate slowdown

System on chip / System in packageIO speed / bandwidthMultiple voltages

Semiconductor Technology Trends

2 04/15/05



Interdependency of Components

Semiconductor Technology

Ceramic Substrates

Organic Substrates Customer

Test, Inspection &Measurement

Thermal Management

Environmental Concerns

Modeling, Simulation & Design

Assembly Processes & MaterialsProduct Lifecyle

RF Components & Subsystems

Passive Components

Connectors

Sensors

Packaging Optoelectonics

Board Design Board Assembly

gratefully borrowed from iNEMI

3 04/15/05



Steam Iron5W/cm2

Steam Iron5W/cm2

Thermal Concerns

4 04/15/05



Chip (C4) footprintPower/Ground/Signal layout optimization

vs pkg wireability & power distributionOptimization across different package technologiesI/O bound on die vs carrier C4 pitch

SCM or MCM chip carrierDegree of chip integration (see example)wiring on-chip (thin/close) vs off-chip (thick/long) architecture (processor / cache interaction)system level granularity ("x-way" processor capability)

2nd level I/Ochip carrier I/O density vs. card technologydegree of integration on chip carrierhigher number of chips drives increased carrier sizenature of 2nd level I/O (pluggable vs hard connect)

Power density & thermal managementimpacts all levels of packaging

Interaction Examples - Historical

5 04/15/05



LGA Components: Regatta

ATC3.8Sylgard 577Seal

EngagementPost

Die Substrate

Board

LGA Connector

Steel Stiffener

Heat sink

MC

M M

odul

e

- Processor MCM Module - IMD- L3 Cache Module - Hitachi- Passthru Card - IMD

6 04/15/05



Systems Trends: How the world looked

7 04/15/05



Systems Trends: Performance and Volume H

igh

Perf

orm

ance High Performance trends:

LARGE TIGHTLY COUPLED SMP SYSTEMSOn Module Frequency / Speed / IntegrationReliability: up to 10yr life, fault tolerant Performance > Cost (but important)

DRIVES:

Custom Chip / Package / MCM IntegrationTotal power up to 900 W per MCM (cooling)Power supply/regulation (card complexity, design)

High Volume

High Volume trends:

SMALL LOOSELY COUPLED SYSTEMSCost & TTM > Performance (still important)Lower aggregate BW (narrow busses, increasing frequency)Standard IO interfaces

DRIVES:

Organic carriers, simplified card cross-sectionsIndustry enabled ecosystemCard/ Board / System interconnect speedSystem power budgets / energy star (cooling)Lead free transition

8 04/15/05



Systems Trends: How the world looks

Chip(2 processors)

Compute Card(2 chips, 2x1x1)

Node Board(32 chips, 4x4x2)

16 Compute Cards

System(64 cabinets, 64x32x32)

Cabinet(32 Node boards, 8x8x16)

2.8/5.6 GF/s4 MB

5.6/11.2 GF/s0.5 GB DDR

90/180 GF/s8 GB DDR

2.9/5.7 TF/s256 GB DDR

180/360 TF/s16 TB DDR

9 04/15/05


© 2004 IBM Corporation04/20/2005Source: Saire, Nguyen, Krueger

Cost Buildup Comparison: Cost Buildup Comparison: 2 Blades of comparable performance2 Blades of comparable performance

Blade 1 Blade 2

FulfillmentCommoditiesPackaging/Cooling

Other Nest/Elec/PwerIO BridgePower

Serv ProcRaw CardProcessor$2,186

10 04/15/05



Today

Cos

t

Organic SCM

Ceramic SCM

Ceramic MCM

•Air cooled•1X TIM•200um pitch C4•1mm pitch BGA/CGA

•Air cooled•1X TIM•200um pitch C4•1mm pitch BGA/CGA

•Air cooled•1X TIM•200um pitch C4•LGA

Packaging Solution Roadmap

2010

High Density Carrier

Coreless Organic Carrier

•Water cooled•10X TIM•50um pitch C4, stud, copper core, etc.•Low force LGA/BGA/compliant

•Air cooled•4X TIM•100um pitch C4•low force LGA

Ultra high performance/Ultra low cost organic

Silicon Carrier

Current Coreless concerns:Impact on 1st level assembly and Thermal Solutions

2008 2009

Ceramic MCM

Organic MCM

•Air cooled•4X TIM•150um pitch C4•Low force LGA

•Air cooled•2X TIM•150um pitch C4•BGA, low force LGA

Low cost/high performanceOrganic carrier

Current FC-PBGA concerns:Loss of Design Flexibility of Ceramic

Add/Remove LayersEscape of inner signals

Current FC-PBGA drivers:Reduced InducatanceImproved DC IR DropImproved Coupling

11 04/15/05



Electrical Requirements for High Performance / High EndParameter 2005 2007 2009

Data Rate (Highest Speed Bus)

1.82Gb/s 3.47Gb/s 6-8Gb/s

Eye Opening (on MCM net)

310ps for +/- 150mv 200ps for +/- 50mv 40-45% of Z6

Receiver Noise (effect on eye opening)

80ps 60ps 50% of Z6

Impedance - Line (nominal)

Single Ended: 50 ohm Differential: 100 ohm

Single Ended: 50 ohm Differential: 100 ohm t

Single Ended: 50 ohm Differential: 100 ohm

Impedance - Via (nominal)

48.5 ohm 48.5 ohm Single Ended: 47.5-52.5 ohmsDifferential: 95-105 ohms

C4 Max - Current Density

310 mA per C4Ottawa 350um int. with 4mil C4

250 mA per C4Full dense 201.6um with 4mil C4

8A per mm squared

CP Power 85W 275 W 250-300 W

Power Density 65W/ sq Cm 60-80 W / sq Cm 80-100 W / sq Cm

Hot Spot 105 C 110 C 120 C

CAPCAP CAPCAP

12 04/15/05



The technology cosmos revisited

Semiconductor Technology Trends

EnvironmentalProduct Trends

Power Supply

Co-designfor performancefor cost

Chip Carrier trends

Power Management

Product QualityReliabilityQual methodsQuality mgmt

PbFree

Moore's law: slowing but not deadFaster devices

finer lithothinner oxides, low K, etcVt lowerLeakage higher

Cost per circuit decreasesInnovation to compensate slowdown

System on chip / System in packageIO speed / bandwidthMultiple voltages

Scale UP

Scale OUTGames RuleThe Great Convergence of Everything IT Theory

ConnectorsOptical?Fine pitch

Panel trends

13 04/15/05

IBM Systems Group


IBM eSystem Roadmaps: Technical Challenges and Environmental Compliance

C. DeCusatis & J. QuickIBM STG, Poughkeepsie, NYPresented at the 2005 Printed Circuit Board SymposiumEast Fishkill, NY, April 20-21, 2005

IBM Systems Group


Server & StorageVirtualization

Partitioning

Core on demand Technologies

Linux open standards

Grid Computing

Autonomic Computing

Capacity on Demand

Systems Consolidation

POWER™Architecture

Mainframe Servers

Core Products

Blade ServersDisk Storage

StorageNetworking

Tape and Optical Systems

Intel processor-based Servers

AMD processor-based Servers

Midrange Servers

Unix Servers

ClustersStorageSoftware

TotalStorage

IBM eServer

CoreTechnologiesOperating Systems

Processors

Server & StorageVirtualization

Partitioning

Core on demand Technologies

Linux open standards

Grid Computing

Autonomic Computing

Capacity on Demand

Systems Consolidation

POWER™Architecture

Mainframe Servers

Core Products

Blade ServersDisk Storage

StorageNetworking

Tape and Optical Systems

Intel processor-based Servers

AMD processor-based Servers

Midrange Servers

Unix Servers

ClustersStorageSoftware

TotalStorage

IBM eServer


Processors


Processors

IBM innovation and computing technologies provide choice

IBM Systems Group


Flexible Growth with IBM eServer and Total StorageProviding choice in acquiring the right technology as customer business and application needs evolve

Helping to deliver:

• Investment protection with documented roadmaps

• Continued performance leadership

• Confidence in the reliability and performance

• Low operational and systems management costs

Helping to deliver:

• Investment protection with documented roadmaps

• Continued performance leadership

• Confidence in the reliability and performance

• Low operational and systems management costs

Clients require:

• Streamlined integration of servers, storage, networks and applications

• Maximize utilization of computing resources

• Ability to rapidly respond to changes in technology and business needs

• Maintain control over the cost of computing

Clients require:

• Streamlined integration of servers, storage, networks and applications

• Maximize utilization of computing resources

• Ability to rapidly respond to changes in technology and business needs

• Maintain control over the cost of computing

IBM provides:

• Flexible packaging of technologies

• Shared technology leadership with Blade Servers, Enterprise X-Architecture™ POWER™

Technology andMCM/CMOS

• Advanced virtualization, grid and autonomic capabilities

• Full Linux enablement

IBM provides:

• Flexible packaging of technologies

• Shared technology leadership with Blade Servers, Enterprise X-Architecture™ POWER™

Technology andMCM/CMOS

• Advanced virtualization, grid and autonomic capabilities

• Full Linux enablement

IBM Systems Group


IBM eServer and TotalStorage:Systems that take the customer where they want to go

IBM eServer BladeCenterTM

iSeries 890 / pSeries 690 / zSeries 990

Clusters andVirtualizationIBM TotalStorage

Enterprise Storage Server®

xSeries 455

High Density Rack Mount

FAStT Storage

Linux or Powerbased clusters

Large SMP

IBM eServer e325 IBM eServer BladeCenterTMIBM eServer BladeCenterTM

iSeries 890 / pSeries 690 / zSeries 990

Clusters andVirtualizationIBM TotalStorage

Enterprise Storage Server®

xSeries 455

High Density Rack Mount

FAStT Storage

Linux or Powerbased clusters

Large SMP

IBM eServer e325

IBM eServer e325

IBM Systems Group


IBM ^ Product Family

iSeriesMost flexible, high performance integrated business serversCapacity upgrade on demand

pSeriesMost powerful, technologically advanced UNIX serversClassic RAS (reliability, availability, serviceability / scalability)

zSeriesEnterprise servers for e-business99.999 % availability(<5 min/year)over 30 % MIPS growth annually

xSeriesAffordable, Linux and NT-ready servers with mainframe- inspired reliabilityBlade and rack mount solutions

Storage"Shark" provides over 3.6 TBytes storageLocal storage subsystem partitioningMetro/Global Mirroring options

Linux support across all platformsInterlocked with Storage and Service Offerings

IBM Systems Group


zSeries Enterprise Servers - (z990 full configuration)

RearFront

IBM Systems Group


z990 Processor Nest

CEC Books, Cooling and Cables

Front

Rear

DCA's, Osc, ETR features and Cables

Typical zSeries Packaging

IBM Systems Group


z990 I/O Nest

I/O cards and Cable (front)

Many Types of I/O Protocols

I/O cards and Cable (Rear)

IBM Systems Group


IBM eServers - pSeries p5 Solutions

p5 575 Supercomputer building block

IBM Systems Group


EXTREME COMPUTING ! - p5-575 design innovations

Distinctive, high efficiency,intelligent DC power conversion and distributionsubsystem

Power Distribution Module (DCA)

Single core POWER5 chips support high memory bandwidthPackaging designed to accommodate dual core technology

CPU/Memory Module

High capacity 400 CFM impellersHigh efficiency motors with intelligent control

Cooling ModuleVersatile I/O and service processorDesigned to easily supportchanges in I/O options

I/O Module

IBM Systems Group


IBM pSeries 690 enterprise server clusteringBrand GA pSeries Configuration 8, 16, 24, 32-way Standard 16, 24,32-way Turbo

Software Release AIX 5.1B 32/64-bit KernelLPAR Support

PackagingCEC Tower

24" Rack12 External RIO Ports 366/433MHzNative IO

I/O Drawer 8 RIO Drawers 24" Racks

Processor POWER4 1.1 / 1.3GHzPartitioning (16 StaticPartitions) --> Dynamic 10/02CUoD Dynamic 10/02

Service Processor New features / functionsDRAM and Flash increased to 16MFastBoot Ctl

MemoryMin: 8GB Max: 256GB8GB/32GB CardsCUoD Dynamic 09/02

RIO& Storage RIO Drawer4 EIA, 20 PCI slots / Drawer160 PCI slots total /SystemBlind Swap PCICD-ROM (std) via Media DrawerFCAL, Ultra SCSI DASD18, 36, & 72GB (Internal Drives)

IBM Systems Group


CEC Technology / Components (examples)

Base Power Assembly

p690 Backplane

4 MCM Sites (8-Way MCM)16 L3 Sites (32 MB each)

8 Memory Card Slots8 X 4 GB - 8 X 32 GB

Dual Fans

24'' CEC Cage

Multi Chip Module (air-cooled)4 8-Ways

4 GB - 32 GB Memory8 - 32 DIMMS

512 MB - 1 GB DIMM (DDR)

IBM Systems Group


IBM eServers - iSeries i5 Business Solutions

SmallBusiness

First POWER5Processor Server

Designed for unique Infrastructures

For medium to large enterprises

For medium to large enterprises Largest iSeries server

IBM Systems Group


eServer Blade Center Chassis

IBM ® BladeCenterTM offers a broad range of networking options integrated into the chassis to simplify infrastructure complexity and manageability while lowering total cost of ownership.

Scales-out DataCenters by interconnecting blades and chassis together with InfiniBand as the interconnect• Leverages high bandwidth and low latency characteristics of the InfiniBand standard with Remote Direct Memory Access (RDMA) • Enables consolidation of LAN and SAN connectivity for an entire data cluster to a centralized location • Virtualizes, and shares I/O and storage across an entire BladeCenter or collection of BladeCenters for cost savings and high availability.

Example: Infiniband Switch

With 14 server bays, this enclosure allows up to 84 two-way servers into an industry-standard rack.

IBM Systems Group


xSeries Rack-Mounted Servers & BladeCenter

IBM Systems Group


IBM TotalStorage Family

Midrange Disk (DS4000)ƒExcellent price performanceƒLeading management softwareƒAttaches to pSeries, xSeries,

Windows, UNIX, Linux

Storage Networking/SolutionsƒLeading vendors: Brocade, McDATA, CNT, Cisco –

SAN ConnectivityƒNAS Gateway 500 – Attaches FC Storage to I/PƒDR550 – Lifecycle management

Enterprise Tape (3494/3592)ƒHigh reliability/performanceƒA single tape drive for all

enterprise workloads; fast access and high capacity

ƒStart/stop and streaming performance

ƒAttaches to zSeries, pSeries, xSeries, iSeries, Linux

ƒ300 GB per cartridgeƒWorm Functionality and MediaƒVirtual Tape Server with Peer-to-

Peer Remote Copy for D/R

Midrange Tape (LTO)ƒIndustry momentum behind LTO

format standardƒDrives and libraries attach to

xSeries, pSeries,iSeries, UNIX, and Windows

ƒStreaming performanceƒ200 GB per cartridge

Enterprise Disk(DS8000, DS6000and ESS)ƒEnterprise class reliability,

performance, and scalabilityƒDS8000 has exceptional

performance scalability and LPAR option

ƒDS6000 has midrange packaging/price

ƒAttaches to pSeries, zSeries, xSeries, iSeries, Sun, HP, Windows, Linux and many others

ƒLeading, high-performance Disaster Recovery and Copy solutions

Storage Software ƒSAN Volume Controller - virtualizes storage for one interface

to multiple vendor SAN storage ƒSAN File System - single file system, improve data access &

managementƒTivoli Storage Manager for Data Retention, Tivoli Storage

Manager for Space Management, Tivoli Storage Manager –Hierarchical storage management and Archive Management

ƒIBM TotalStorage Productivity Center:– storage management

IBM Systems Group


IBM eServer Ecosystem: Fibre Channel Directors

Cisco MDS family

McData family, including Intrepid 10K

Brocade Silkworm IBM Offers Solutions

IBM Systems Group


zSeries WDM Ecosystem

Cisco ONS 155XX(GDPS Qualified)Primary IBM Development Partner

Lucent Metropolis EON(GDPS Qualified)

Nortel OPTera Metro(GDPS Qualified)Primary IBM Development Partner

IBM Systems Group


THE ENVIRONMENTAL CHALLENGE:European Union Environmental Directives

Restriction of Hazardous Substances Directive (RoHS)The Restriction of Hazardous Substances (RoHS) Directive restricts the use of lead, mercury, cadmium, hexavalent chromium, and certain flame retardants in electrical and electronic products. This Directive applies to all electrical and electronic products placed on the EU market after July 1, 2006, with various exemptions, including an exemption for lead solder in network infrastructure equipment.

Waste Electrical and Electronic Equipment Directive (WEEE)The Waste Electrical and Electronic Equipment (WEEE) Directive mandates the necessary treatment of such equipment when it becomes end-of-life. It specifically identifies requirements for recycling, reuse, and disposal.

Energy-Using Products Directive (draft) (EuP)The Energy-Using Products (EuP) Directive is still in a draft format and is expected to be enacted in 2005. It establishes guidance for the integration of environmental aspects in the design and development of new energy-using products to ensure minimal environmental impact.

IBM Systems Group


IBM is actively collaborating with Suppliers, Contract Manufacturers, Industry Consortiums, and other Supply Chain Partners in order to achieve compliance with the Directives. IBM is also participating in consultations with the European Union and the Technical Adaptation Committee in an effort to ensure that the final implementation requirements of the Directives consider the ultimate long term reliability and quality of public and private computing infrastructures. IBM remains dedicated to maintain its reputation in respect of environmental matters and is therefore supportive of the European Union environmental objectives as well as other similar initiatives currently under review in many other countries around the world. IBM internal targets for RoHS compliance exceed those of the industry standard (4Q05)

Proactive Cooperation

IBM Systems Group


RoHS Timeline and IBM Approach

1Q

2Q

3Q

4Q

1Q

2Q

3Q

4Q

1Q

2Q

3Q

4Q

1Q

2Q

3Q

4Q

1Q

2Q

3Q

4Q

2003 2004 2005 2006 2007

Server Lead (Pb) in solder exemption until Jan 2010

IBM, OEMs

Industry Leaders: Japanese, Celestica, Solectron, Intel

Must comply by July 1, 2006

RoHS = Removal of Hazardous Substances

WEEE = Waste from Electrical and Electronic Equipment (must comply by August 13, 2005)

Achieve RoHS compliance before July 1, 2006

Move with the industry - Avoid cost increases of conversion

Mitigate Risk: balance availability, process readiness, cost, technical risk

lead (Pb)-free solder exemption available to S&TG

Transition new IBM Products in 2005

Industry Standardization

Extensive new PNs, ECs

EU AdoptionJan. 27, 2003

IBM Systems Group


Product and Raw Carrier ChallengesEuropean Union Directives (RoHS and WEEE)

Designing and packaging of electronic products more difficult than ever.Increased performance and functional demand increase while maintaining product machine floor footprintIncreased product power and cooling demandsDensity of components and component-to-component interconnection Raw Carrier Design Parameters

Electrical characteristicsMaterial Selection and lamination Impedance control and conductor characteristicsSmall hole technology / imagingElectrical Testing

Design Tools / Design Analysis / Technical data transfer Quality Control (coupons)Surface finish / Solder Mask and LegendsAssembly processes (increased temperatures)

These challenges will be discussed throughout the symposium

IBM Systems Group


IBM Design and Industry Standard OEM ProtocolsCommon I/O Platform

Industry Standard Protocal Board 1

Industry Standard Protocal Board 2

IBM Systems Group


PCI-based adapters: RoSH supply chain impact

Let’s Compare

JNI

Qlogic

Emulex

IBM Systems Group


The Future is optics "InfiniBand" example

1. Connectorized Version

2. Active Cable

IBM Systems Group


Design of Fiber Optic TransceiversThe RoHS Challange

IBM Systems Group


Conclusions

IBM Environmential compliance roadmaps are on track for 2005IBM servers and storage productsSupply chain for ComponentsSupply chain for I/O cablesEcosystem of OEM products

Future card roadmap issuesInfiniBand copper and optical links, including switchesActive cable "dongles" for channel extension 8-10 Gbit/s links and follow-onsIncreased performance / Loss materialsHigher Component density and decreased featuresMoving from copper to optical interconnects RoHS (Totally Lead Free / no exemptions ) product Assembly

IBM Systems Group


The IBM Server Value Proposition

- Deliver Real Value to the Customer - Customers expect that our products will not fail. Raw Carriers are the "Foundation" which eServer depends on to ensure high product reliability.We need your help to achieve customers expectations.

IBM Systems Group


END - LAST SLIDE

IBM PCB TechnologyIBM PCB TechnologyChallengesChallenges

Bruce Chamberlin Bruce Chamberlin -- [email protected]@us.ibm.comIBM Corp. IBM Corp. -- Integrated Supply ChainIntegrated Supply Chain

Procurement EngineeringProcurement Engineering

April 13, 2005April 13, 2005

PCB Technology Drivers

$ Cost $

Environmental Legislation

Current Density

Reliability

Speed / Operating Frequency

Form factor

ConnectorTechnology

First Level Packages

Thermal management

IBM eServer™


o Power4 Uses 2:1 Chip-to-Board Frequencyo Important Threshold Reached in 2006: Dielectric Losses > Resistive Losses in PCB at 30 Inches

Data from the Internation Technology Roadmap for Semiconductors

Server Trends

02 03 04 05 06 07 08 09Year

0

2

4

6

8

10

12

Ope

ratio

nal F

requ

ency

in G

Hz

Max GHz

Min GHz

Operating Frequency Projections

10

Driver: Signal Integrity

Low Transmission Line Attenuation

o Limits Progression towards Finer Line Widths/Spaces (3 mils -> 4 mils)o Driving Toward 1 Ounce Signal Lineso Low Loss Dielectric in Limited Use Today; Very Low Loss Required by 2007o Potentially Further Copper Roughness and Copper Resistivity Control

Impedance Measurements: Accuracy and Tolerance

o Measurement Technique per IBM Specificationo Line Geometry and Dielectric Thickness Control Critical

• Coupon-to-Functional Net Correlation and Variation across Functional Nets


Balanced Triplates Generally Required (Power-Signal-Power-Signal...)o Signal – Signal Core Usage Restricted due to Signal Coupling

Tighter Control of Design Modification by Suppliers

o Unused Lands o Signal Line Manipulation (e.g., for Addition of Signal Flares),o Dimensional Modification (PTH Diameters, Line Width, etc)


Minimize Signal Reflection Due to PTH Stubso Stub reduction technology usage 2005 and beyond

o Backdrillingo Subcomposites

• With composite through holes • With z Interconnect

o Blind viaso Microviaso etc.

Driver: I/O and ConnectorsDetermines Number of Layers and Card Thickness

o Maximum Layer Count to Continue in mid-30'so Maximum Composite Thickness to Continue at Approx. 200-240 milso Aspect Ratio 15:1 and Risingo Demands the Use of Thinner Cores

Rigidity, Electrical Integrity, and Impedance Control

Connector Technology Impact

o Forced Design Rules (Pad Stack Requirements)

Past: Pitch and Finished Hole Size SpecifiedPresent: Past + Drilled Hole Size and Plating Thickness SpecifiedFuture: Power Clearance and Internal Lands also Specified

o Registration Budget

IBM eServer™


PTH Aspect Ratio

Driver: I/O and Connectors2nd-Level Attach Challenges

Pb-Free Compliant Pin Connectors (2005)

o Actuation Load and Board Damageo Retention Forceo Interaction with New Pb-Free Laminate Materials (Laminate Cracks)

Surface Mount Connectors

o Pb-Free Attach (2006)o Reflow Profiles for 5000+ Contact Connectorso Connectors and Board Planarity

Driver: I/O and Connectors

BGA / CGA Modules

o SCM / DCM 1.0 mm Pitch with I/O to 2500o SCM Pitch 0.8 mm Going to 0.75 with I/O to 400

Land Grid Array: MCM Attach Method for High End Systems

o Up to 7300 I/Oo 1.0 mm Pitch: No Projections to Decreaseo PCB Challenges

• Plating Methodology• Planarity and Cleanliness

IBM eServer™


Driver: Increasing Current Density

Driver: Increasing Current Density

Increased Board Power Dissipation

o Resulting in Higher Global and Local Board Operating Temperatureso Being Assessed using Special Thermal Test Boards

Voltage Drop Challenge

o Increased by Multiple Voltage Sense Points o "Swiss Cheese" Effect of High I/O, Tight Pitch Modules

Example: 1 mm Array with 32 mil Clearance Holes Leaves only 7 mil Web

Mitigation: Increased Copper Content in Boards

o Impact on Processability and Reliability

Driver: Real Estate and Form Factor

Buried Resistors and Capacitors

o Real Estate and Performance Main Driverso Not Justified Solely by Cost o Tolerance and Reliability Need to be Addressed

Panel Size

o Peaking at 24” x 28”, with Push to Stay within 19.5" x 24"o No Known Requirement for Larger Boards but Could be an Opportunityo Complexity and High Density of Smaller Packages Expanding to Large Boards

PCB Thickness Constraintso Applications such as Blade Servers Restrict PCB Thickness

• Driving Thin Cores, Denser Wiring, Smaller Vias, etc.

Driver: Environmental Factors

Environmental Legislation: RoHS

o Lead-free Assembly Compatibility (Mixed Assembly Now)

Raw Cards must be Capable of Withstanding Higher Assembly TemperaturesStandard Loss (2006) and Low Loss Materials (2007) RequiredWill Affect Subsequent Processes, Surface Finishes, and Reliability Tests

Environmental Friendliness: Green Laminate

o Market Driving Low End --------- Identify New Materialo Not Required for Server or Storage Applications

RoHSRoHS ChallengeChallenge

Increased Peak Board Temperature during SMT Solder ReflowIncreased Peak Board Temperature during SMT Solder Reflow

oo Tin Tin -- Silver Silver -- Copper (SAC) SolderCopper (SAC) Solder

TTmpmp = 217= 217TminTmin Reflow Reflow = 230 = 230 –– 235235Maximum Board Temperature = 260Maximum Board Temperature = 260SolderabilitySolderability a Critical Parametera Critical Parameter

oo PCB Distortion will Increase with Higher Reflow TemperaturesPCB Distortion will Increase with Higher Reflow Temperatures

Copper Dissolution During PIH Rework Copper Dissolution During PIH Rework

oo No PTH Thermal Breaks will Increase Board Exposure and TemperatuNo PTH Thermal Breaks will Increase Board Exposure and Temperaturere

PbPb--Free TemperatureFree Temperature--Compatible PCB Compatible PCB SolderabilitySolderability Finishes RequiredFinishes Required

Driver: Cost / Reliability

Reduce Cost while Maintaining High Reliability

Front End Collaboration to Achieve

o Design for Reliability and Manufacturabilityo Optimize Component Placement and Panel Utilizationo Bill of Material

Test Strategy

o Early Warnings to Minimize Cost of Scrapo Enhance Yield through Continuous Improvemento Potential Need for High Rel Tests (Near Opens, Near Shorts, HiPot)

What do the Technology Roadmaps Say?

Jack FisherInterconnect Technology Analysis Inc.

04 -20 -05

Interconnect Technology Analysis Inc.

Roadmapping Overview


National Technology Roadmaps

SemiconductorIndustry

PCB & EMSIndustry

ElectronicsIndustry


Japanese Jisso RoadmapInterconnect Technology Analysis Inc.

IPC

1993

1994

1995

1997

2001-2002

2002-2003

2004-2005

NEMI

1994

1996

1998

2000

2002

2004

NTRS/ITRS

1992

1994

1997

1999

2001

2003

2005 In progress

Jisso

1999

2001

2003

2005 In progress

Electronics Industry Roadmapping History

I t t T h l A l i I

Roadmaps have a focus or a purpose and an individuality…

If you understand the focus and individuality of a roadmap you can then understand why three

roadmaps can all report a different value for the same parameter and all of them will be correct


Market PullMarket PullTechnology Push

Style

>1%4- 5 %< 10%Industry R&D Invest

ManufacturingProcess Develop.

ProductManagers

Manufacturing Researchers

Team Skills/Experience

FewSomeHighGovernment and Academia

Participation

We BelieveWe NeedWe ExpectThesis

Prepare Industry for Next

Generation

Members info.R & D priorityRoadmap Purpose

Senior Techs.•Mgmt•Eng.



TeamMakeup

IPCNEMIITRS


Business Issues


Maturing Electronics Industry• Product segments entering the commodity

phase of the life cycle. • Break-through technology may no longer be

sufficient to insure business success. • Customers are demanding the right solution at

the right cost Business behavior quite different from the past.

Supply Chain Management becoming very important Environmental regulations providing significant challenges and increasing investments.

ROADMAP IDENTIFIED BUSINESS ISSUES

Interconnect Technology Analysis Inc

Electronics industry is re-structuring• Manufacturing competence moving from OEMs

to EMS and ODMs• Significant shifts in roles and responsibilities

across the supply chain. • Dramatic movement of manufacturing to China

from North America, Europe, and other Asian countries

The increasing scope of outsourced operations requires loosely coupled business processes spanning multiple companies.

ROADMAP IDENTIFIED BUSINESS ISSUES

I t t T h l A l i I

Regulatory Issues


Two EU Directives, RoHS (Restriction on use of certain Hazardous Substances) and WEEE (Waste from Electrical and Electronic Equipment), which govern the material content and end-of-life management of electronic products must be implemented by July 1, 2006 and August 13, 2005 respectively.

REGULATORY ISSUES


Legislation impacting the design and recycling of electronic products is being enacted throughout the world including China.

Requires the electronics industry to share detailed material content data of their products and components.

• To meet regional legislative requirements, manufacturers must remove environmental “Materials of Concern,” such as lead. • The electronics industry is facing end-of-life or producer responsibility legislation.

REGULATORY ISSUES


Market Issues


MARKET ISSUES

•Sales of electronics products has recovered.•Boundaries between computers, communications and entertainment products are blurring. •Large, flat panel displays are experiencing rapid growth. •Wireless products particularly WiFi and Bluetooth are nowwidely used, and digital cameras are merging into cellularphones.•Home and office functionality is being added to automotiveproducts. •Radio Frequency Identification (RFID) systems are beingused for security and increased efficiency of commerce. •Telecommunication and data communication infrastructureare converging


• Worldwide production of computers and office equipment is expected to grow at an average rate of 6.2% per year to reach $483Bn in 2008. This is the largest segment of the electronics industry, accounting for about 37% of overall production.

• Global production of netcom equipment is expected to be 18% of the electronics industry. Driven primarily by Internet use, this segment is expected to increase at an average rate of 6.3% per year to reach $230Bn in 2008.

• Portable and consumer electronics production are expected to increase at an average rate of 5.1% per year to reach $223Bn by 2008.

MARKET ISSUES


Technology Issues


One size doesn’t fit all

High electrical & thermal conductivity materials

High pin counts and finer pitch packages

Lower Package Profile Heights

Lowest Cost Solutions

Packaging Implications


Vision of the Evolution of SiP

SiP -- System in a Package

• System in Package (SiP) has emerged as the fastest growing packaging technology although still representing a relatively small percentage of the unit volume. In 2004, 1.89Bn SiPs are expected to be assembled. By 2008, this number is expected to reach 3.25Bn, growing at an average rate of about 12% per year.

• SiP applications have become the technology driver for small components, packaging, assembly processes and for high density substrates.


SiP -- System in a Package

SiP is changing the dynamics of the supply chain. The development of functional, modular components allows for rapid introduction of complex, multifunctional products to address the converging markets.. This paradigm shift in the design approach increases the flexibility and shortens the design cycle, and places the test burden on the producers of the modules.


TECHNOLOGY ISSUES

SiP is a main stream technology

Chip scale packaging is rapidly replacing olderlead frame technology

Wafer level packaging is taking off

EMS and Packaging Assembly and Test are overlapping


• The anticipated end to semiconductor scaling c. 2015 will create a major technology shift in the industry:

• Implementation of advanced, non-classical CMOS device with enhanced drive current

• Identification, selection, and implementation of advanced devices (beyond-CMOS)

• Innovative packaging for giga-function system in package (SiP)


TECHNOLOGY ISSUES

LCD and plasma displays are starting to encroach on the CRT market, while OLED (Organic LED) has the promise of providing thin, lightweight – even roll-up – display technology that could compete with LCDs.

TECHNOLOGY ISSUES


Use of embedded passives

Sip roadmap0201 today01005 in 2006not showing EP

CPU roadmapEmbedded passives needed now

Where are we headed in materials for packaging??


Paradigm Shifts / Potential Disruptions


Paradigm Shifts

• Convergence of broadband communications and digital technology has increased product opportunities while creating uncertainty in marketing.

• System in Package functional modules are speeding the design of new portable and office system products and reducing risk to the OEM. Product examples:– Bluetooth – WiFi (802.11b,a,g) – GSM (Global System for Mobile Communication )


• Rapid introduction of complex, multifunctional new products to address converging markets favors development of functional, modular components (e.g. SiP)

– Increases flexibility & shortens product design cycle & places test burden on module producers

– This architecture allows for MEMS device construction with a variety of new applications in fuel cells & life sciences (DNA/blood testing)

Potential Disruptive Technology


• Wireless applications are an important driver for semiconductor products & technologies and may stimulate disruptive solutions

• Nanotechnology has the potential to be a very disruptive technology during the period covered by the roadmap

• New energy technologies that may cause disruptive opportunities include fuel cells and high power batteries for hybrid electric vehicles.

Potential Disruptive Technology


Disruptive Technology Pointers

• Many key technologies will be developed outside our traditional supplier base“Key competency” considerations or lack of resources will hamper many traditional suppliers

• We need to identify the key technologies on the radar screen and highlight them to members and the supply chain– Encourage NSF, DoD, DoE, university links and

input to them– Emerging technology conferences (Innovation

Committee)


Strategic Concerns

• Given flow of technology & manufacturing between countries, many key component industries are looking for alternative business strategies to maintain leadership

• Innovative approaches to Enterprise IT & supply chain management which increase ROI in a predictable way

• EMSs are being asked to provide R&D leadership while keeping overhead low – this may not be a viable business strategy


Strategic Concerns

• The materials supply base does not have adequate demand (at high enough margins) to drive many of the needed new materials

• Impact of Environmental Compliance on financials, reliability, & IT infrastructure

• Reliability of less mature material systems ?


• Application of MEMS technology is making new capabilities feasible in a number of old and new markets such as displays; servo control for mass data storage, optical and RF switches.

• At some point, circa 2010-2015, the limits of electrical transmission in high performance systems may be reached. Optical systems are likely to provide part of the solution, particularly if Optical ICs are developed

TECHNOLOGY

I t t T h l A l i I

Needs


DESIGN TECHNOLOGIES

Design and simulation tools are the main roadblocks to more rapid introduction of new technologies in a number of rapidly developing areas:

• Mechanics and Reliability Modeling • Thermal and Thermo-fluid Simulation • Improved design tools for emerging technologies like embedded passives and optoelectronic PCB’s

TECHNOLOGY NEEDS


MANUFACTURING TECHNOLOGIES

With research and development (R&D) responsibility shifting from OEMs to the EMS companies, government, academia and industry consortia need to formulate new ways to adopt and develop emerging technologies (such as nanotechnology) into the manufacturing process.

TECHNOLOGY NEEDS


TECHNOLOGY NEEDS

• Implementation of advanced, non-classical CMOS device • An effective Optical electronic circuit board (OECB) technology is needed to eliminate fiber handling cost • Higher thermally conductive materials such as carbon nanotubes, carbon fiber, aluminum nitride, and even diamond to cool optical and electronic devices. • In-circuit test technologies that can be incorporated into the build process. • Cost and performance models that help highlight the benefits of embedded passives and optoelectronics

COMPONENT/SUBSYSTEM TECHNOLOGIES


MEMs


Current MEMs packaging technology utilizes retrofitted traditional packaging designs.

There are few standards which can impede progress

Some specific MEMs packaging designs are appearing, but it is to early to determine if this is a trend.

General overall perspective from all roadmaps….

Although a popular topic these days in almost all technology circles, nanotechnology has not yet matured to a sufficient extent for us to comment on the use, trends, andl benefits or risks involved in material selection. Thus, we will continue to watch this growing area and evaluate its applicability to the future.

• Nanotechnology (sub-100 nm) era.


• A number of important disruptive technologies (nanotechnology, micro-fluidics, distributed sensing, advanced micro-optics) are poised to have substantial impact on the commercial marketplace for sensors.

• From all the perspectives, it appears that for most sectors, the critical years in the roadmap would be 2004-2005, except for the newly emerging areas Nanotechnology and optoelectronics where the criticality is expected to appear after 2005, in the 2005-2007 range.

NANOTECHNOLOGY


Substrates are not just a space transformer to change from device pitch to component pitch. Today substrates are an integral part of the circuit


SUBSTRATES

Limitation of Fine Line/Space Width• Conventional Technology Limitation at <20micron

Line/Space and Via Hole Diameter• Increasing Additive Process and/or

Semiconductor-like Process RequirementsAdoption for Signal Integrity

• Shortage of Electronics Engineers in PWB Industry

• Increasing Capital Investment for Embedded Components

• Modeling & Simulation are necessary for Embedded Components and SiP


PCB Specific

Adoption for Interconnection Reliability• Modeling & Simulation for Total Package

Structure, especially for Low k & Cu Device• Integration into Packaging Substrate to release

Mother board density & Cost• PWB products began to differentiate in two

categories of complexity such as SiP, EAD and cost oriented type– Buildup Motherboard, FPC and packaging

substrate is growing area– Conventional Motherboard production shift from

Japan to Asian countries

PCB Specific


• An active component embedded printed wiring board has significant potential to SiP

• Maintenance of the design database and a modeling & simulation environment are necessary for EP, Opto and Embedded actives

PCB Specific


http://www.nesa.com

Gigabit PCB Dielectric Studies Slide 104/20/05

bExperts in High-Performance Engineering & Design © 2004, 2005sm

North East Systems Associates, Inc.http://www.nesa.com

Tel: 978 392-8787 v Fax: 978 392-8686

by:by:

Dr. Edward P. Sayre, P.E.Dr. Edward P. Sayre, P.E.Mr. Michael A. BaxterMr. Michael A. Baxter

Dr. Edward P. Sayre, IIIDr. Edward P. Sayre, III

20 April 2005

v

IBM PCB ConferenceIBM PCB Conference

Gigabit Dielectric Material StudiesGigabit Dielectric Material Studies

Low Loss Material Comparisons and Performance RankingLow Loss Material Comparisons and Performance Ranking

http://www.nesa.com



Introduction & Summary

ØØ Primary Goal:Primary Goal: Show a clear “ranking” of backplane suitable PCB material loss performance in both the time and frequency domains. (NESA)

1. Based on a variety of Electromagnetic and SPICE circuit simulations, and 2. Confirmatory measurements based on test articles specifically designed to match

the simulated physical designs.

ØØ Material Choices:Material Choices: Three board materials were chosen based on simulation and market judgments: Rogers (RO4350B®/RO4450B®), Taconic (TacPregTM /TacLamTM), and Park/Nelco (N4000-13SITM)

Ø Major Conclusions:Major Conclusions: The major experimental based conclusions were unexpected:

1. Rogers RO4350B® performed better than the other two materials, but not by a great deal.

2. N4000-13SITM with low loss glass performed better than expected.3. The dielectric losses were larger for Rogers and Taconic than those indicated by

the dissipation factor (DF) numbers called out on the respective material vendor data sheets.

4. Skin effect roughness and/or a feature size based dielectric loss model is proposed to account for the differences in the various PCB data.

http://www.nesa.com



Program Objectives

ØØ Objectives:Objectives: In order to achieve the the stated goal to show a clear “ranking” of backplane suitable PCB material loss performance in both the time and frequency domains, the following three objectives had to be reached:

1. Phase I - Point-to-Point 100 Ω differential lossy transmission models were built using the material vendor dielectric material data sheets, 2-D and 3-D Electromagnetic field solvers and HSPICE .W models derived from the field solvers and other tools.

2. Phase II - The creation of Physical Test Vehicles, designed to evaluate the dielectric transmission and loss properties of three commercially available PCB materials - Rogers (RO4350B®/RO4450B®), Taconic (TacPregTM /TacLamTM), and Park/Nelco (N4000-13SITM). The designs were designed and constructed to common manufacturing trace sizes and controlled impedance standards.

3. Phase III - Correlation of Signal Integrity measurements conducted on the fabricated test articles against theory, H-SPICE simulations and the manufacturers’ published dielectric PCB were compared against the tiem and frequency domain measurement results.

http://www.nesa.com



Phase I – Signal Integrity Simulation and Test Vehicle Design Rule Development

ØØ SI Simulations:SI Simulations: The design parameters for the Test Vehicle were developed during Phase I :

1. Using PCB material manufacturer supplied data sheet values and various stack-up designs developed with 2-D field solvers, H-SPICE .W models were developed and run to provide:

ü TDR Impedance, Time Domain Transmission (TDT), ü Gigabit eye-diagrams (2.5Gbps, 5Gbps & 10Gbps) and ü Frequency domain Return Loss and Transmission S-Parameters over the frequency

range of 1 MHz thru 10 GHz.

2. These models were updated post-measurement to account for actual PCB cross-section geometries impedance and SMA launch characteristics. The latter were most visible at ~ (9 –10) GHz.

http://www.nesa.com



Phase II – Physical Test Vehicle

ØØ Test Articles:Test Articles: The Physical Test Vehicle design parameters were:

1. Controlled impedance 100 Ω differential interconnects with both edge coupled as well as broad-side coupled trace designs.

2. Traces were ½ Oz thick copper, trace width = 4 mil and 8 mil representing current industry practice. The boards were designed using commonly available material core and pre-preg thicknesses. The designs resulted in 10 layer PCB test articles.

3. The experiments emulated the Phase 1-A trace simulations in length and trace parameters. Traces between 1/6 [~6”] of a meter through 1 meter were designed into the experimental test vehicles in the two indicated trace widths.

4. The measurement transition from the SMA measurement interface to experiment traces had to have bandwidth > 6 GHz which is equivalent to a 12 Gbps data stream.

http://www.nesa.com



Typical Differential Cross-section(from 2D field solver*)

*ApSimRLGC

Sample dimensions from cross-sections (mils):Material W1 W2 S D1 D2 D3Rogers 7.9 7.6 5.7 12 13.2 12Taconic 8.3 8.5 4.6 8 13.3 8Nelco 8.1 8.2 5.4 13.7 12.1 13.7

Copper thicknesses in 0.6-0.7mil range

W1 W2S

D2

D1

D3

http://www.nesa.com



Phase III - Correlation Program

Correlation Between Simulations and Measurements:Correlation Between Simulations and Measurements:

Ø The 8mil wide edge-coupled trace pairs were found to be a more reliable environment in which to conduct the dielectric property correlation work. Focus was concentrated on the 8 mil results, especially for the longer trace lengths of 0.5m and 1m. The 8-mil simulation models were revised post-measurement using the extracted cross-sectioned layer and trace stackup dimensions (e.g. trace widths, copper thickness, trace spacing and dielectric dimensions).

Ø A damped ringing response SMA launch resonance at ~ 9.5 GHz. was observed in the TDR measurements. An accurate circuit model was developed for the launch response and modified the Phase 1 simulations. A new SMA launch model was added to the simulation models to include the high frequency parasitic effects observed in the ~(9 – 10) GHz region.

Ø The detailed cross-sections using a scanning electron microscope (SEM) permitted accurate extractions of the geometrical cross-section of the copper traces for impedance verification and skin effect perimeter length validation.

http://www.nesa.com



Physical Test Vehicle

http://www.nesa.com



TDR Impedance Profile – Rogers RO4350/RO4450

Impe

danc

e (O

hms)

Impe

danc

e (O

hms)

simulated

measured

1m long pair

simulated

measured

0.5m long pairRinging due to SMA/launch

SMA at far end Rogers paths are well

controlled given the long lengths involved

Good match between simulation models and measured results

http://www.nesa.com



Further Correlation Measurements

TDT and TDT and EyEy--diagram Correlation Between Simulation and Measurements:diagram Correlation Between Simulation and Measurements:

Ø Time Domain Transmission (TDT) simulations and measurements were compared. The high frequency effects of increasing the DF of each material were subtle and not readily observed in the results.

Ø Eye-diagrams at digital data rates of 2.5, 5.0 and 10 Gbps were also measured. The eye-mask corresponding to serial 10 Gigabit 4-channel Ethernet XAUI was used as the pass-fail eye test. The eyes for 1 meter long 8 mil traces at 10 Gbps were closed. Transmission over that distance would probably require single bit pre-emphasis and spectral shaping to correct for deterministic jitter I.e., low frequency de-emphasis or high frequency boost.

Ø With the proper technology, it is possible to create accurate simulations of multi-gigabit performance that match the results of high-quality laboratory instrumentation. (Such as NESA’s “Passive Signal Integrity™” approach.)

http://www.nesa.com



TDT Step Response Profile – Rogers RO4350/RO4450 (datasheet DF)

Am

plitu

de G

ain

(%)

simulated reference (unnormalized)measured reference (normalized)simulated TDT out (0.5m)measured TDT out (0.5m)simulated TDT out (1m)measured TDT out (1m)

High-frequency losses show up as rounding off of edge

With specified DF from datasheet, we get what appears to be a good match, although high-frequency losses are off a bit.

Increasing DF gets us much closer as shown in the next slide.

http://www.nesa.com



TDT Step Response Profile – Rogers RO4350/RO4450 (revised DF)

Am

plitu

de G

ain

(%)

simulated reference (unnormalized)measured reference (normalized)simulated TDT out (0.5m)measured TDT out (0.5m)simulated TDT out (1m)measured TDT out (1m)

Increasing DF x2, we get a better high-frequency match.

This result is much more evident in the insertion loss plots in next section.

Better match with DF x2

http://www.nesa.com



Eye Pattern Measurement Set-upAdvantest D3186 12Gbps Pulse Pattern Generator

Agilent Infinium DCA 86100A + HP54751A 20GHz Module

test boards & coupons

Test Articles

Measurement Cables

http://www.nesa.com



Data Rate = 5Gbps Plots

XAUI Rx Eye Mask Scaled for 5Gbps Data

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.00E+00 5.00E-02 1.00E-01 1.50E-01 2.00E-01 2.50E-01 3.00E-01 3.50E-01 4.00E-01

Time (ns)

Diff

. Am

pl. (

V)

1UI = 1 bit width = 0.2ns

min. opening.35UI (70ps)

Note: Plots are scaled for two bit widths, as are the eye plots included in this summary.

Sample Receiver Eye Mask – XAUI Specification

Data Rate = 10Gbps Plots

XAUI Rx Eye Mask Scaled for 10Gbps Data

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.00E+00 5.00E-02 1.00E-01 1.50E-01 2.00E-01

Time (ns)

Diff

. Am

pl. (

V)

1UI = 1 bit width = 0.1ns

min. opening.35UI (35ps)

http://www.nesa.com



Sample 10Gbps Measured Eye Pattern Plots8mil wide lines, edge-coupled, 0. 5m Taconic: board T-01

Jitter(p-p): 48psEye width: 52psEye height: 214mV

Rogers: board R-01Jitter(p-p): 33psEye width: 66psEye height: 354mV

Nelco: board N-04Jitter(p-p): 39psEye width: 60psEye height: 298mV

Ranking Results, 10Gbps 0.5m:

Rogers has edge over Nelco with Taconic performance behind (today’s receivers typically require 100mV opening or less – standards typically specify 200mV)

Note: no materials had measurable eye openings for 1m lengths @10Gbps; and only the Rogers material had a small eye opening at 0.75m length.

http://www.nesa.com



Sample 5Gbps Measured Eye Pattern Plots8mil wide lines, edge-coupled, 1.0m Taconic: board T-01

Jitter(p-p): 98psEye width: 103psEye height: 186mV

Rogers: board R-01Jitter(p-p): 65psEye width: 135psEye height: 302mV

Nelco: board N-04Jitter(p-p): 79psEye width: 119psEye height: 226mV

Ranking Results, 5Gbps 1.0m:

Same ranking with Rogers’ having a more pronounced advantage over Nelco; Taconic remains behind. A bit worse than 0.5m at 10Gbps, but still valid data.

http://www.nesa.com



Further Correlation Measurements

The Correlation Process between Simulation and Measurements:The Correlation Process between Simulation and Measurements:

Ø Frequency domain S-parameter tests were also conducted using an Anritsu Differential Vector Network Analyzer (DVNA).

Ø The S-Parameters measurements were inputted into the HSPICE simulation environment to permit a direct comparison of the simulated and measured results.

Ø This comparison allowed the dielectric properties of the material to be adjusted to match the S-Parameter measured results.

http://www.nesa.com



Physical Test Article Set-up for Differential Four-Port S-Parameter Measurement

High-frequency SI test board

Anritsu MS4624D 4-Port Vector Network Measurement System

http://www.nesa.com



-3

Rogers, 0.5mNelco, 0.5mTaconic, 0.5m

Rogers, 1mNelco, 1mTaconic, 1m

http://www.nesa.com



With specified DF from datasheet, we see a much more pronounced mismatch between simulation and measurement results than is apparent in the time domain.

Again, increasing DF gets us much closer as shown in the next slide.

http://www.nesa.com



For the Rogers material, increasing DF x2, we get a better high-frequency match.

Final DF = 0.008 @10GHz

http://www.nesa.com



For the Taconic material, also by increasing DF x2, we get a better high-frequency match.


http://www.nesa.com



For the Nelco material, only a slight increase of DF by 10% gives us a good high-frequency match.


http://www.nesa.com



Summary of Phase III Observations and ResultsCorrelation Between Simulations and Measurements:Correlation Between Simulations and Measurements:

Ø PCB parameter correlation programs require that the simulation phase be updated based on actual cross-sectional data, launch circuit parameters and extraneous measurement effects.

Ø The updated simulation data for the Nelco material matched the time and frequency data quite closely. A nominal increase in DF by 10%, from .010 to .011 was the only adjustment in the dielectric properties required to achieve excellent simulation-experimental correlation.

Ø The losses were observed to be much larger for the Teflon based Rogers and Taconic materials than those predicted by the manufacturers’ dissipation factor (DF) numbers.

Ø Increasing the dielectric loss appropriately gave much better simulation/measurement correlation in both the time and frequency domain results with the following changes:

• Rogers: increase DF by a factor of two, from .004 to .008

• Taconic: increase DF by a factor of two, from .006 to .012

http://www.nesa.com



Problems with Phase III Observations and ResultsProblems with the Interpretation of Measurements:Problems with the Interpretation of Measurements:

Ø Although the correlations were excellent by increasing the loss tangent (DF), NESA views these 200% corrections to the dielectric loss tangent to be too large and alternate explanations for the losses should be considered. Two mechanisms come to mind:

Øü Skin effect loss increase due to induced surface roughness; so called “Tooth”

ü The cross-section results show that the feature size of the trace parameters has about the same periodicity as the glass reinforcement fibers and the surrounding dielectric matrix. If the trace is over a more lossy component in the material (DF of 1080 E-glass = tan δ= .0066, Er=6.6), the effective loss tangent will be higher than that measured in a dielectrometer or with a wide trace(250 mil) transmission dielectrometer 1.

Ø “Tooth’d” Skin Effects: On the cross-sections of both Rogers and Tac-Preg, the presence of much larger “tooth” was observed on the copper. It is believed that this is due to the necessity of a rough surface to enhance the adherence of the copper to the dielectric substrate.

Ø Non-homogeneous Dielectric Loss: Feature size dependent non-homogeneous dielectric loss effects due to higher losses in the glass vs. the Teflon dielectric are causing higher losses in traces which have field distributions which mostly encompass the higher loss material.

1. “New Developments in High Frequency Measurements of PWB Materials, Part II Applications of the Bereskin Method to PWB Materials”, Ivan Aratingi and Randy Hoard, AlliedSignal Laminate Systems, LaCrosse, WIwww.isola-usa.com/images/uploaded/DielectricMeasurement99.pdf

http://www.nesa.com



NELCO 4000NELCO 4000--13 Edge13 Edge--Coupled Traces Coupled Traces Trace Width = 200Trace Width = 200µµ [7.8[7.88 mil], Thickness = 13.9 8 mil], Thickness = 13.9 µµ [0.0547 mil][0.0547 mil]

133 u133 u 200 u200 u200 u200 u

~37~37oo13.9 u13.9 u

Glass FiberReinforcement

Resin

Copper Traces

For TeflonCu tooth increasedon surfaces

http://www.nesa.com



Simplified Surface Roughness TheorySurface RoughnessSurface Roughness

Ø It is now believed that surface roughness plays a bigger role in the loss budget (i.e. skin effects) than was previously thought; this is particular true of “toothed” copper used in low loss dielectric where the adhesion must be enhanced. The longer effective surface developed by a rough surface can be thought of as a higher skin effect resistance, although it still increases as:

Ø Using simplified rough surface theory, one can show that the surface length increases approximately by:

f

peaks between period w roughness peak to peak mean h :where

1 wh for

wh4

wh16 1

==

>

⋅≈

⋅+

2

http://www.nesa.com



Typical Differential Cross-section – Field Distributions(from 3D field solver*)

*CST MicroWave Studio 5.0

E-field distribution

Higher dielectric losses ifE-field is concentrated inthe more lossy glass fibers

http://www.nesa.com



Alternate Loss Theories

Ø The frequency at which the rough surface skin effect losses equal the dielectric losses can be seen to be:

Ø The higher the frequency at which the dielectric losses = the skin losses, the less the dielectric losses affect the total loss budget.

Ø The alternate explanation revolves around questions of non-homogeneous losses and trace feature size vs. the size of the lossy component, e.g., the glass fibers. In that case, the effective shunt conductance Gd increases in direct proportion to the loss tangent:

Ø Intel and others are applying resources to sort this out both wi th regard to skew within a pair as well as increased losses.

⋅+⋅

⋅==

22

2 1611wh

ZGR

od

ssmooth

lossesdielskinf

)tan(2)tan( δπδω ⋅⋅⋅⋅=⋅⋅= CfCG d

http://www.nesa.com



Calculated Insertion Loss FR-4 8 mil [0.195mm] Line Width, tan(δ) = 0.021, ½ oz. Cu [15.9µ], h/w=0

Dif ferent ia l FR-4 PCB DC, Sk in Ef fect , D ie lect r ic and Tota l Loss vs . Frequency(Trace Impedance = 100 ohms, Avg . t race wid th ~ 8 .0mi ls [2 .55mm] , 0 .5 Oz Copper ) , h /w =0

0 .0

5 .0

1 0 . 0

1 5 . 0

2 0 . 0

2 5 . 0

3 0 . 0

3 5 . 0

4 0 . 0

4 5 . 0

5 0 . 00.001 0 .010 0.100 1 .000 10.000

Frequency [GHz]

Loss

es [d

B/m

]

D C L o s sSk in E f fec t LossDie lect r ic LossTota l Loss

http://www.nesa.com



Calculated Insertion Loss FR-4 8 mil [0.195mm] Line Width, tan(δ) = 0.021, ½ oz. Cu [15.9µ], h/w= 0.2

Differential FR-4 PCB DC, Skin Effect, Dielectric and Total Loss vs. Frequency(Trace Impedance = 100 ohms, Avg. trace width ~ 8.0mils [2.55mm], 0.5 Oz Copper), h/w = 0.2

0.0

5.0

10.0

15.0

20.0

25.0

30.0

35.0

40.0

45.0

50.00.001 0.010 0.100 1.000 10.000

Frequency [GHz]

Loss

es [d

B/m

]

DC LossSkin Effect LossDielectric LossTotal Loss

http://www.nesa.com



Calculated Insertion Loss Rogers 8 mil [0.195mm], Tan (δ) = 0.004, Line Width, ½ oz. Thick Cu [15.9µ], h/w = 0

Differential Rogers PCB DC, Skin Effect, Dielectric and Total Loss vs. Frequency(Trace Impedance = 100 ohms, Avg. trace width ~ 8.0mils [2.55mm], 0.5 Oz Copper), h/w = 0

0.0

5.0

10.0

15.0

20.0

25.0

30.00.001 0.010 0.100 1.000 10.000

Frequency [GHz]

Loss

es [d

B/m

]


http://www.nesa.com



Calculated Insertion Loss Rogers 8 mil [0.195mm], Tan (δ) = 0.008, Line Width, ½ oz. Thick Cu [15.9µ], h/w = 0

Differential Rogers PCB DC, Skin Effect, Dielectric and Total Loss vs. Frequency(Trace Impedance = 100 ohms, Avg. trace width ~ 8.0mils [2.55mm], 0.5 Oz Copper), h/w = 0

0.0

5.0

10.0

15.0

20.0

25.0

30.00.001 0.010 0.100 1.000 10.000

Frequency [GHz]

Loss

es [d

B/m

]


http://www.nesa.com



Calculated Insertion Loss Rogers 8 mil [0.195mm], Tan (δ) = 0.008, Line Width, ½ oz. Thick Cu [15.9µ], h/w = 0.4

Differential Rogers PCB DC, Skin Effect, Dielectric and Total Loss vs. Frequency(Trace Impedance = 100 ohms, Avg. trace width ~ 8.0mils [2.55mm], 0.5 Oz Copper), h/w = 0.4

0.0

5.0

10.0

15.0

20.0

25.0

30.00.001 0.010 0.100 1.000 10.000

Frequency [GHz]

Loss

es [d

B/m

]


http://www.nesa.com



SummaryØ Both time- and frequency-domain experimental and updated simulation results show

the following material performance close ranking:1. Rogers RO4350B®/RO4450B®

2. Park/Nelco N4000-13SITM

3. Taconic TacPregTM /TacLamTM

Ø The loss budget for low loss materials shows that the series resistive losses become more important as the dielectric losses are reduced.

Ø The approximate rough skin effect loss formulation shows that for h/w ~ 0.5, the transition from predominately skin effects to dielectric losses occurs at approximately 2.24 times the frequency for smooth copper and will raise the overall losses, especially for low loss materials.

Ø The roughness theory can easily be applied to present lossy line ”W” simulation models. The skin effect loss term can be estimated from the surface statistics and the dielectric properties of the materials.

Ø The feature size of the constituent dielectric materials vs. the conductor size and the field distribution will determine whether there are asymmetrical skew and loss terms for each trace in a differential trace pair.

Physical Design of High Speed PCB's

Gisbert ThomkePackaging Development

IBM Lab Boeblingen, GermanyApril 2005

1

© Copyright 20Gisbert ThomkIBM Boeblinge

Design tools usedConstraints that can be handledCost of constraintsRouting the designsSystematic length errorsElectrical preferred structuresDesign for manufacturing

Overview:

2


Cadence software for all PCB layoutConcept HDL for logic entryAllegro for PCB layoutNetRules & Constraint Manager for electrical & physical constraints

Valor software for manufacturing checksMechanical dataFlare setting

Design Tools used

3


Net lengths (delays): min, max, matchedWire widthsWire spacingsMax parallel lengthsDifferential pairs (on one layer)Layer rules (manually)

Constraints that can be handled

4


Factor for TAT: Definition, routing, checkingNet lengths: 2.0 .. 3.0Layer restrictions: 2.0 .. 3.0Wire widths: 1.2Spacing rules: 1.5 .. 2.0Diffpairs: 2.0Shielding clocks etc.: 1.5 .. 3.0

Costs of constraints

The factors here describe the extra effort needed for a specific constraint. For exampleif unconstrained wiring takes 1 week, then wiring with net lengths needs 2 .. 3 weeks. This isin addition to constraint generation by electrical design!

5


Determine a routing strategy, prioritize buses and netsAssign a wiring rule to EVERY netIterate for every priority

Automatic / manual routingCheck wiringModify constraintsModify component placement

Can handle all kinds of vias:Thru, blind, buried, subcomposite

Routing the designs

6


Length errors for some wire structures

Systematic length errors

7


Completely manually wiredCenter line length is different to copper lengthOnly structure without DRCNet must be fixed, this causes trouble outside of the fanout wiringOnly manual/visual inspection

Other comments to this structure

==> Nice solution, but not applicable for morethan a couple nets

8


Problems with unsymmetric component pins

Different min spacing valuesManageable with temporary pin increase (circle in red), necessaryfor autorouting

9


Autorouter uses accordion or trombone pattern for length adjustmentsPreferrences can be setUnpredictable results

Electrical preferred structures

10


Optimize wiring for flaresGeneration of mfg data

Large components exceed IPC356 netlist capabilities, e.g. 5 char pin names

Check mfg data with Valor Enterprise 3000Improve release data quality

Design for manufacturing

Red circles are flare positions

11

IBM Research

Time-Domain Characterization of Printed-Circuit Boards for Multi-GHz Operation



Alina DeutschIBM T. J. Watson Research Center, Yorktown Heights, NY [email protected]

IBM Research

Time-Domain Characterization of Printed-Circuit-Boards for Multi-GHz Operation © 2005 IBM Corporation

Time-Domain Characterization of Printed-Circuit-Boards for Multi-GHz Operation

MotivationLimitations of Present MethodologiesTime-Domain Extraction TechniqueIllustrative Results

2

IBM Research


Present Challenges

Increase in data-rates transmitted on printed-circuit-boards requires:o more accurate and causal transmission-line models for predicting

system performanceo non-causal models can cause inaccurate timing prediction and simulator

convergence problemIn order to generate broadband causal models (DC to ~50 GHz) we need: o higher accuracy and higher-bandwidth measurements of εr(f) and tanδ(f)o single value εr and tanδ supplied by vendors cannot generate causal

models

Higher-performance systems need the development of lower loss materialsfor printed circuit boards:o new materials need to be analyzed in representative laminated structures

New concerns need to be considered:o losses due to roughness could become significant – 5-50% @ 5 GHzo moisture absorption of new materialso lead-free compatibility impact on characteristics

3

IBM Research


Total Loss InformationResistive and dielectric losses need to be accurately known:

• significant error in performance prediction can occur

Freq. Width=2.9 Width=4.29 Width=8 miltanδ(f) tanδ=0 tanδ(f) tanδ=0 tanδ(f) tanδ=0

(GHz) (dB/cm) (dB/cm) (dB/cm)1.50 0.1168 0.1021 0.0769 0.0617 0.0498 0.03453.00 0.1953 0.1443 0.1388 0.0872 0.1007 0.04886.00 0.3762 0.2046 0.2959 0.1233 0.2420 0.069210.0 0.5619 0.2645 0.4585 0.1595 0.3894 0.0895

Width (mil) Length (cm)w. tanδ(f) w. tanδ=0 Delta

2.90 22.0 28.0 21%4.29 29.0 48.0 40%8.00 37.0 82.0 55%

2.9mil

22cm

4.29mil9cm 8mil

37cm 4.29mil48cmtanδ=0

8mil82cmtanδ=0

4

IBM Research


Broadband Complex Permittivity ε(ω)

Why we need broadband material characterization:• single value εr or tanδ give erroneous results

Skin-effect + εr(f) + tanδ(f)Skin effect + εr = ct, tanδ = 0Skin-effect + εr = ct, tanδ = 0.0133

Skin-effect + εr(f) + tanδ(f)Skin-effect + εr = ct, tanδ = 0Skin-effect + εr =ct, tanδ=0.0133

5

IBM Research


Effect of Roughness and Surface Treatment

High resistancesurfacetreatment

6

IBM Research


Effect of Roughness and Surface Treatment

Loss Delta Due to Roughness

5 GHz 10 GHz---------------------------A 49.8% 53.4%B 20.3% 23.6% C 5.5% 10.6%---------------------------

Error in extracted tanδ dueto roughness not being modeled as part of the resistiveloss

7

IBM Research


Needed Parameters for Predictive Modeling

Transmission-line parameters need to be fully known:

))(Cj)(G))((Lj)(R()( ωωωωωωωΓ ++= )()( ωβωα j+

=

=

Zo (ω) = Γ(ω) / (G(ω) + jωC(ω))

R(ω), L(ω), C(ω), G(ω) need to be causally related over entire frequencyrange (ω = 2πf):• ε(ω) = ε’ (ω) – j ε” (ω)

• ε’r = Re ε , tanδ = - Im ε / Re ε

• tanδ(ω) = G(ω) / ω C(ω)

Eye-diagrams need broadband models due to variable data-pattern:

8

IBM Research


Needed Parameters

Designers need material parameters to generate predictive models for range of dimensions and operating frequencies:

ρ and complex ε (ω)

Vendors provide: ρ but not the surface treatment characteristicsεr and tanδ at single frequencyΖο from TDR but not broadband Zo(ω)Attenuation α at a few frequencies and a specific cross section

=

9

IBM Research


New Approach is Needed

Present Network-Analyzer Based Measurements are Unable to Extract Broadband Material Characteristics Due to Large End-Effects of Vias, Pads, Antipads, Probes:• Can obtain α(ω) and β(ω) mostly at high frequencies• Zo(ω) has not been obtained yet on realistic structures• new de-embedding techniques need to be developed

Measurements are Complex, Costly, and Not Consistent Across Suppliers

Time-domain technique combined with signal processing and iterative fitting and modeling has been shown successful over the range 10 KHz to 50 GHz

=

10

IBM Research


Extraction Procedure

Special Representative Test Vehicle with Small Interface DiscontinuitiesHigh-Bandwidth Time-Domain Instrumentation and Accessories (70 GHz)Signal Processing for Translation from Time-Domain to Frequency-DomainIterative Modeling Based on Causally-Enforced Field Solverand Debye Model (L-R, C-G) Extension to Low-Frequency Using Embedded Parallel-Plate Measurement of C and tanδ in 10KHz - 1 MHz range

11

IBM Research


Short-Pulse Propagation Technique – Gamma-Z

21

21

2

1

21

)()()()(ln1)()()(

llffj

fAfA

llfjff

−Φ−Φ

+−

=+=Γ βα

Short pulse (20 ps width) is launched on identical lines l1 and l2Signal processing of digitized, detected pulses:

• rectangular time windowing with smooth ends to eliminate end effects• Fourier transformed and ratioed thus no de-embedding needed

Att = 20log10 eReΓ(ω) β(ω) = ΙmΓ(ω)

))(Cj)(G))((Lj)(R()( ωωωωωωωΓ ++=

extracted frommeasurement

12

α β

IBM Research


Short-Pulse Propagation Technique – Gamma-Z

Calculate R(ω), L(ω) from dimensions and C(ω), G(ω) by using a starting set of values for tan δ (ω) = ε”

r / ε’r with a Debye model to interpolate that guarantees causal ε (ω):

Extrapolate using parallel-plate low-frequency C and tanδ:

Iterate by comparing measured total loss

G(ω) = ω C(ω) tanδ(ω)

ε’r (ω) = (C(ω) /C1MHz ) x ε’

1MHz Zo (ω) = Γ(ω) / (G(ω) + jωC(ω))tanδ(ω) = G(ω) / ω C(ω)

∑ ++= ∞

i i

i

j1)(

ωτε

εωε

))(Cj)(G))((Lj)(R()( ωωωωωωωΓ ++=

calculatedwith fieldsolver

Final results

measured w. LCR

13

tanδ(ω) @ low freq.ε’r1MHzC1MHz

IBM Research


Short-Pulse Measurement Set-up

Agilent 86100B/86118A 70 GHz SamplingOscilloscope

Picoseconds Pulse Labs 4022 TDT SourcePulse Enhancer and Differentiator 5206tr = 11ps

67A GHz GGB Coaxial Probes

14

IBM Research


Modeling Using CZ2D Field Solver

∑ ++= ∞

i i

i

j1)(

ωτε

εωε

L(ω)-R(ω) guaranteed causal through automatic gridding

C(ω)-G(ω) guaranteed causal through use of Debye model:

ε(ω) = ε’ (ω) – j ε” (ω) ε’r = Re εtanδ = - Im ε / Re εtanδ(ω) = G(ω) / ω C(ω)

15

IBM Research


Special Representative Stripline Test Vehicle

Test Pads16 mil pitch

13x14mil

Parallel-platesε’

r = 3.75 @ 1 MHztanδ @ 10 KHz – 1 MHzwith LCR

8-mil via

Cmeasured: 1.41 pF/cmCcalculated: 1.45 pF/cm +2.8%

@ 1MHz with LCRHP 4275A

φ = 500 mil

16

IBM Research


Screening for Uniformity Using TDR

17

IBM Research


Propagate and Digitize Short Pulses

Pulse widths: 20-40ps 18

IBM Research


Signal Processing

=

19

IBM Research


Iterative Modeling of Γ(ω)

Bandwidth: 2.2 – 38 GHzAtt = 20log10 eReΓ(ω) β(ω) = ImΓ(ω).

))(Cj)(G))((Lj)(R()( ωωωωωωωΓ ++=20

IBM Research


Broadband Zo(ω) Extraction

Zo (ω) = Γ(ω) / (G(ω) + jωC(ω))

21

IBM Research


Extracted Dielectric Constant and Dielectric Loss

f(GHz) ε’r

0.00001 3.8136 ---------2.15444 3.6346 26.0000 3.5383 50.0000 3.5119 -7.9%

Debye model is justified byslowly varying dielectric properties

22

IBM Research


Iterative Modeling for Extraction of Dielectric Constant and Dielectric Loss

Freq. ε’r tan δ tan δ

(GHz) 0.00001 3.8136 0.00128 0.00500.00010 3.7914 0.00520 0.00600.00100 3.7500 0.00700 0.00700.01000 3.7119 0.007000.10000 3.6742 0.007001.00000 3.6354 0.00700 0.00702.15444 3.6346 0.00702 0.00703.17000 3.6325 0.01073 0.01004.64160 3.6186 0.01500 0.015010.0000 3.5777 0.01750 0.015021.5444 3.5458 0.01750 0.015026.0000 3.5383 0.0175046.4160 3.5148 0.01750 0.015050.0000 3.5119 0.01750Infinite 3.3412

Calculated Initial Values

∑ ++= ∞

i i

i

j1)(

ωτε

εωε

ε’r (ω) = (C(ω) /C1MHz ) x ε’

1MHz

tanδ(ω) = G(ω) / ω C(ω)

Plate Meas. withLCR

23

IBM Research


Validation of Technique

l = 5 cm

l = 5 cm

l = 8 cm

l = 20 cm

24

IBM Research


Strengths and Limitations of MethodologyLimitations

High-frequency range limited by losses in the lines, spectral content of source pulses reaching the lines, large signal-to-noise ratio in broadband time-domain detectors (70 GHz has been shown feasible with short lines and fast sources), uncertainty due to roughness, and manufacturing capabilities

Low-frequency range limited by large interface reflections that cannot be eliminated by windowing or ratioing and limit window extent, needs augmentation with parallel-plate data

Accuracy is limited by amplitude resolution of broadband detector, line non-uniformities, skin-effect dominance at low frequencies over tanδ

Resolution in tanδ is ~10% below 2 GHz, ~5% above 4 GHz, reproducibility of loss ~6%

Requires a combination of measurement, modeling and cross sectioning

25

IBM Research


Strengths and Limitations of Methodology

StrengthsRequires very simple time-domain measurement (TDR, TDT)

Self-consistent extraction of ε’r(ω) and tanδ(ω) over 2-40 GHz range based on Debye model that is justified by slowly varying properties

Produces fully-causal, broadband transmission-line models (Γ(ω) and Zo(ω)) that can be used for predicting system performance, 10 KHz to 50 GHz is adequate for spectral content of representative digital signals

Measurement can be performed on in-situ representative structures that incorporate all critical processing steps

26

IBM Research


References

A. Deutsch, G. Arjavalingam, G. V. Kopcsay, “Characterization of resistive transmission lines by short-pulse propagation”, IEEE Microwave and Guided Wave Letters, vol. 2, no. 1, pp. 25-27, Jan. 1992A. Deutsch, M. R. Scheuermann, G. Arjavalingam, L. Kneller, J. K. Tam, C. W. Surovic, “Characterization of resistive transmission lines to 70 GHz with ultrafastoptoelectronics”, IEEE Microwav. Guided Wave Lett., vol. 3, no. 3, pp.75-77, March 1993.A. Deutsch, T-M. Winkel, G. V. Kopcsay, C. W. Surovic, B. J. Rubin, G. A. Katopis, B. J. Chamberlin, R. S. Krabbenhoft, “Extraction of εr(f) and tanδ(f) for Printed Circuit Board Insulators Up to 30 GHz Using the Short-Pulse Propagation Technique”, IEEE Transactions on Advanced Packaging, vol. 28, no. 1, pp.4-9, Feb. 2005.

PCB Technology Challenges and Approaches

Voya MarkovichEI, April/05

Today’s Packaging Trends in Market Place Drive Technology Progress, Cost & Reliability

Performance Density

Signal propagation Power Distribution

Environmental Concerns

New Materials & Process

HalogenFree

PbFree

ToxicityExposure

WasteTreatment

Higher frequency for servers / telecom

Low loss materialsWider lines

Better shieldingLow Cu roughness

Stub reductionZ interconnection

Optical interconnect

Higher power dissipationHeavier copper

New materials for thermal conduction& thermal interface materials

Embedded coolingThermal//mechanical material stability

Robust interconnect

Higher densityFiner lines/spaces

Smaller holesZ interconnection

Integration of embedded:

resistors, capacitors,inductors & actives

Assembly Test Reliability

Microelectronics Advanced Interconnections Semiconductors versus Package

Smallest features: “parallel paths” for how long?

IC scaling

Laser via / thin film / z-interconnect based interconnect technology needed to reduce the IC to PWB interconnect gap

HyperBGA is a registered trademark of Endicott Interconnect Technologies, Inc.

Time

PWB

PWB w/ buildup layers& Laser vias

Reduced Interconnect

Gap

HyperBGA® Interconnecttechnology

1990’s

Z-interconnect technology

Meso

Micro

Nano

2000’s 2010’s

InterconnectGap

$F ilte rs A n te n n a s

H

SOPSource:

adapted after Shipley

Present Packaging Technologies

MLC

MLCHyper-ZEI

HDB-Z

HDB -Z

Source: Tessera

Source: IBM

HSB-HDIHyperBGA

Thin Film Pkg

CORE EasEI SLCHDB (Back drilling)

Source: IBM

PCB’s fabrication parameters to meet system performance:

Line width and spaces – Needs wide/wide lines and spacing - hierarchicalwiring

Line Thickness – Skin Effect ( thicker line reduces skin effect )

Copper roughness – The roughness of the copper in both the signal lines as well as the reference planes will have an effect on attenuation due to skin effects.

PTH stub length reduction – Elimination or limitation of the length of a PTH that is not actually used to complete a circuit.

PWB Cross section – Provide shielding to signals and to provide for proper power/ground distribution.

Subcomposite – This type of construction allows for variable lengthConstruction PTHs in the cross section.

Dielectric material – The material surrounding the circuit traces. The choice of material will have an impact on the performance on the overall system.

Connector footprint –The PTH pattern defined by a card connector which may require compliant pin or SMT attach.

PWB OFFERINGS2004/5

Z Interconnect PWB

2005/06

Dielectric

Conductive Paste

Flush Surface

BGA Pad

Technology Evolution

10+ GB/s10 Gb/s

HDB Full Z PCBStructure is the sameas for HyperZei 1.0-0.8-0.65 - 0.5 mmBGA gridMix dielectricPTH ELIMINATED2L/C-4L/C-6L/C-8L/CAs many layers as needed

Optical Interconnect

Embedded Passives

HPC 2 PCBBuried/Blind vias3 mil via/6mil pad

4L/C in 1.0mm BGA pitchRedistribution Layer

if needed

2.5 -5Gb/s

HDB PCBw/ laser blind /buried vias

stacked viasPTH LENGTHMINIMIZED

w or w/o backdrillingw or w/o Z interconnect

6.25-10.0 Gb/s

HDB Z PCB1.0/0.8mm BGA grid

Red. layer as TSM/BSMPTH LENGTH

FURTHER MINIMIZED2-3-4 subcomposites joined

Mixed dielectricsBackdrilling if needed

Stub Reduction Options

Subcomposite 1

Subcomposite 2

Subcomposite 3

Mixed Power and Signal

Power Planes


Component 3

Component 1

Component 2

SS

S

S

Subcomposites w/buried vias and build up layersBuried vias, w/ or w/o build up

Component 3

S

STUB

STUB

STUB

Component 1

Component 2

STUB

Component 3

Component 1

S

Component 2

STUB

STUB

STUB

S

STUB

STUB

S

Typical 'Full Stub' Board

Full Z Interconnect

Component 3

Component 1 Component 2

Subcomposites and limited Z-Interconnect

Subcomposite 1

Subcomposite 2

Subcomposite 3


Power Planes


Component 1

Component 2

Component 3

S

S

S S

Z Interconnect

D i f f e r e n t ia l In s e r t io n L o s s o f 5 0 c m L in k

- 5 0

- 4 5

- 4 0

- 3 5

- 3 0

- 2 5

- 2 0

- 15

- 10

- 5

0

0 1 2 3 4 5 6 7 8 9 10

F r e q u e n c y ( G H z )

Loss

(dB

)

N o n - b a c k d r i l le d B a c k d r i l le d E I B o a r d

Comparison of Backdrilled board and a Subcomposite build board

System Attenuation Study - Vias

Technology / Construction Copper Trace ViaTotal Loss@ 1.5 GHz

Board Board (dB)

Board 1+3 = Standard 1 oz Low Profile 3 / 5 3 / 17 3.9 180 4 1.2 5.1

Board 2 = Standard 1 oz Low Profile 5 12 2.3 180 2 0.6 2.9 8.0

4.3

2.6

<4.1

<2.4

Board 1+3 = HPC / 3 Subs

Board 2 = Standard / 2 Subs

Board 1+3 = Z-interconnect

Board 2 = Z-interconnect

LW (mils)

Length (in)

Loss (dB)

Stub Length (mils)

# ViasTotal Loss (dB)

System (dB)

1 oz Low Profile 3 / 5 3 / 17 3.9 60 4 0.4

0.3

<0.2

<0.1

1 oz Low Profile 5 12 2.3 90 2 6.9

1 oz Low Profile 3 / 5+ 3 / 17 <3.9 0 4

1 oz Low Profile 5+ 12 <2.3 0 2 <6.5

* 3 Board System, Total 80 cm net length, 6 Vias / net

The Passing of the Traditional PTHNew Interconnect Techniques

DDiStacked microvia

PanasonicMatsushita

ALIVH

IbidenSSP

KyoceraS-HDBU & CPCore

traditional PTH

EI Interconnect Technology

Conventional PTHsBlock Wiring Channels

Controlled-Depth ViasIncrease Wiring Density

150 µm via pitch40 to 65 µm laser-drilled vias

Critical Questions Concerning Packaging

What comes after Si - CMOS ?- Will define packaging

What will be the impact of Nano technology / materials ?- Micro electronics going to Nano electronics ?

Will the entire system be integrated on a chip ? OR will chip and package be integrated into a system ?- SOC or Integrated System – NEMS* ?

*NEMS or nano electrical mechanical system

Mechanical

OpticalElectricalOrganic

Packaging

Applications of nanocomposite materials

Thermal

• Embedded Passives• Z-interconnects• Low Dk & Df• Embedded actives• Lead-free solder

Thin film/layer• Wave Guides• Photo Imageable • Lasers

• Controlled CTE• Compliance• Thermal Conductivity

D0

MCR

120 & 10 nm particles

Embedded Passives

Z-interconnects

Wave guides

Advanced LCC

Source: PRCNano capacitors

Material Needs for 2005 ~ 2008+Pb-free solder processOpto-mechanical compatibility for packagingThermal-mechanical analysis and modeling of packaging structuresHeat tolerant & compliant organic packaging

New materials for integrated packagingPredictive molecular modeling of physical properties of materials and composites

Electrical (Dk & Df), mechanical, optical and thermalNew thermal interface materials for chip assemblyEnvironmentally benign materials/processLow modulus dielectrics with moderate/controlled CTE

Conductive materials for Z-interconnectionMaterials with ease of manufacturability / processing

Embedded Passives• Why:

– Passive usage continues to grow; Passive to Active ratio can exceed 30:1; Free up surface real estate

– Reduced parasitics, improved performance over discretes– Can reduce system cost

• Challenges:– Infrastructure

• Limited Design systems• Limited Electrical Test capability

– Technical• High capacitance (>100nF/cm2), good breakdown dielectrics• Broader range of materials (R’s from 1 – 100Mohms, C’s from 1 pF – 1 uF) • Material and process capability to provide <5% tolerance• Rework / Repair / EC’s

– Market Acceptance• Cost / Perceived Cost• Materials availability

HDB with Z Interconnect 2004/5

HDB Technology 2002/3

Strategic Packaging LCC/BDs 2005-2006

HDB Extention 2003/4

Tactical Technology Roadmap LCC/PWB

HDB ZEI PCB9 x 2S/1P- 3 subs comps/0.8mm BGA grid

Redistribution layer as TSM/BSM

PWB

LCC

Z Interconnect Via pitch 150 umLS/LW 25/25 um ;Pad 75 um

10.0+ Gb/s

HDB/ PCBBuried vias

Low Er and DkVia pitch 200 umLW/LS 28/33 umPad 125/114 umstacked vias7 layers/PTFENo Lead BGA's

12.5 Gb/s

2.5 Gb/s

20.0 Gb/s10.0 Gb/s

20.0+ Gb/s


Embedded Passives

HSB-PCB w/ laser blind /buried vias2/3 LS/LW ;stacked vias embedded capacitance

Core Via pitch -199 um25/25 LS/LW;75 um PadBuried Vias 50 umLaser core and BU viasRCC/Cu - Tg 150-200 CUp to 2-4-2No lead BGA’s

6.25-10.0 Gb/s

SIP/SOP MCM-L / Boards Optical transmission for each of building blocks. Embedded Passives and Embedded Actives

2006-2010 2010-2015 2004-2006

RF Test Process/Tools150 pitch process/tools Laser Test Technology(no test heads)Embedded passives testPWB/LCC process/tools

LGA connector for LCCLCC embedded passives assembly compatibilityLead-free compatibilityLead-free Flip Chip

Align Reliability w/ productenvironment/operating conditionsEmbedded passives rel. requirements.Acceleration factors for new materials,e.g. Lead-free

System/Package testOptical Interconnect Test /Optical coupling testEmbedded Active components test

Integrated Logic/MemoryIntegrated Carbon nano tubesMulti Integrated Optical connection."Assembly in line"

New Reliability Standardsfor organic transistors andpackaging interactions."Burn - in" test"Known Package Test"

REL

IAB

ILIT

Y

A

SSEM

BLY

TES

T

System test after AssemblyTest strategy to complementassembly and product operating conditions.

New Assembly processes (Opto and Electrical assembly)Embedded active and passivecomponents compatibility with new assembly processes

New Reliability Standards foroptical integrated productsNano/Non reinforced materialreliability requirements Embedded Active components/reliabilitystandards.

TEST / ASSEMBLY / RELIABILITY ROADMAP

SOP

Stacked Thin Dies

Wafer Level packaging

Source: AMKOR

Source: EI/PRC

Vertical Organic Interconnect

NANO PACKAGING SYSTEM

HBGAZei

Will chip and package be integrated into a system ?

Source EI

Source :PRC

2005/6 2005/6

Source EI

20152004 2005/6 2006/2010

Func

tion,

Den

sity

Data Rate Gb s-15 20+10+ 40

Embedded Actives

Electrical Interconnect


Embedded Passives

Integrated Package Technology Evolution/Revolution

IntegratedOptical, PassivesHyperBGA HyperZei

Filters Antennas

Integrated PackageSystem

HPC HPCZei

Flexible substrates

Integrated

NANO INTEGRATEDPACKAGING SYSTEM

organic memory stack

optical connection layer(s)

electrical connection vias

logic

memory

embedded passives layer(s)

embedded actives layer(s)

electrical interconnect layer(s)

(conventional)

logic or uproc chip

RF waveguideselectrical connection vias

Embedded cooling

logic

April 20, 2005 IBM PCB Technology Symposium Pg. 1

Non-Classical Conductor Losses Due to Copper Foil Roughness

Sid ClouserGould Electronics


Analysis Objectives• Quantify the high frequency signal loss differences from various

copper foil types.• Determine a first order approximation for modeling copper loss

versus frequency due to copper roughness.• Verify the non-classical copper skin effect losses due to roughness.

µπρδ∗∗

=fs

Skin Depth in Copper

0

5

10

15

20

0.01 0.1 1 10 100Frequency (GHz)

Skin

Dep

th (µ

m)

0.5 oz Commercial Foil Average Roughness, Ra (µm)


Why Copper Foil is Roughened• Adhesion

– High speed, low loss resins are apolar with low affinity for copper bonding.

• Peel strength test, elastic theory.

Foil after peel from Low Dk laminate

Low Dk laminate after foil peelGlass/Resin Substrate

Foil

Adhesive

90° peel test

σN

¾¼

δ0.38 P ¼N oy

YE⎟⎟⎠

⎞⎜⎜⎝

⎛= σ

Elastic deformation


Copper Surface Morphology, Heavy Nodules


Copper Surface Morphology, Fine & Medium Nodule

AMFN treatment absorbs too much light to image optically.


Copper Surface Morphology, No Nodule Treatment


Copper Foil Types and Properties

Resistance

Descriptionµohm*cmRtRaRtmRaSample

7.9

4.5

Roughnessafter laminationVeecoProfilometer

Without nodular bond treatment1.710.253.20.39RolledResistor layer matte profile, no nodule bond treat1.766.60.654.50.50TCRShiny side, nodule bond treatment1.820.623.60.45RTCVery low profile, fine nodule bond treat1.90black3.80.48AMFNShiny side, heavy nodule bond treat1.857.90.695.10.60RTCHPHigh profile, heavy nodule bond treat1.8810.91.316.30.75JTCSHP

Profilometer roughness measured by IPC-TM-650, Method 2.2.17aResistance measured in strip form by IPC-TM-650, Method 2.5.14


Roughness Distribution:0.5 oz Foils Produced Globally and This Study

Roughness Distribution, ½ oz Reverse and Matte Treat

0

0.5

1

1.5

2

2.5

3

0 2 4 6 8 10Roughness Rz (µm)

Dis

trib

utio

n

RTC 1 RTC 2 VLP Grade 3, 1 Grade 3, 2Grade 3, 3 Grade 3, 4 Grade 1, 1 Grade 1, 2

Measured with profilometer.Roughness is varied to meet adhesion demands in the local markets served.

JTCSHP

Rolled

AMFNRTC

TCRRTCHP


Test Coupon Construction and Measurement• 0.5 oz/ft2 (17 µm) Copper Foils

– 6 types, roughest (HPJTC) to smoothest (nodule-free Rolled) foil.

• 5 mil dielectric– Nelco N4000-13 laminated at Gould.

• RLGC Coupons– Designed by Intel, fabricated by Proto

Circuit.– µ-strip construction, 4.5 mil pressed

dielectric thickness.– Contains cross-section areas and

calibration structures on ends.– 2-sided coupons with µ-via to ground on all

pads (345/coupon)– Contains 3 set of different line widths: 5mil,

10mil, 18mil.– Immersion silver finish, no soldermask.

• VNA Measurement– GGB pico-probes are 250 µm pitch GSG

(Ground-Signal-Ground) probes. – Agilent 8722ES Vector Network Analyzer.

5 mil trace

5 mil pad to trace spacing

5 mil µvia in pad

20 mil x 20 mil pad

35 mil centers

GSG probe launch for 5 mil traces.

5 mil trace at end

15 mil trace

5 mil pad to trace spacing

5 mil µvia in pad

20 mil x 20 mil pad

35 mil centers

GSG probe launch for 15 mil traces.


Physical Measurements on Samples

2.213.63.64.9Rolled2.114.24.24.8TCR2.114.24.24.9RTC2.114.34.34.8AMFN2.114.14.14.8RTCHP2.114.34.34.7JTCHP

Trace Thickness (mil)

15 mil trace width (mil)

5 mil trace width (mil)

Dielectric Thickness (mil)

Copper Type

Impedance by copper type


Total Line Loss by Copper Type

• Rougher copper has higher transmission line loss.• Very low profile RTC, AMFN, and TCR perform close to rolled.• Simulation indicates loss for rolled should be lower with same line width as other types.


JTCSHPRTCHPAMFNRTC

TCRRolled

JTCSHPRTCHPAMFNRTC, TCRRolled

0.22

0.11

0.00

Low Frequency by Copper Type- Power Factor Model

• Skin effect conductor loss adjusted to higher than classical √f dependence.• Lower roughness gives closer to classical square root frequency dependence.• Issue with this method power parameter varies with copper type and line width. • 5” surrounding traces removed.


• Foil roughness modeled as an effective increase in dielectric loss (Tand).• Removing classical copper loss results in linear line loss versus frequency.

– Minimum Tand = ~0.009 for rolled.– Maximum Tand = 0.017 for JTCSHP copper foil

• Model requires different values based on line width for a given foil roughness.• Same results across 1”, 3”, and 5” line lengths for each width.

, Ra

Losses vs. Copper Type- Effective Tand Model


Modified Hammerstad Jensen Model Losses- Causal Model

0 2 4 6 8 10 12 14 16 18 20Frequency (GHz)

Transmission Line Loss(5 mil RTCHP)

1.33

1.11

0.88

0.66

0.44

0.22

0.00

Loss

(dB/

in.)

• Hammerstad-Jensen model adjusted for frequency dependence of Tand.

• Provides best fit across entire frequency range. ⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎠⎞

⎜⎝⎛ ∆+=

24.1arctan2)sgn(1δπ

wKsr


Modeling Errors at Low Frequency

0 1 2Frequency (GHz)

0.03

0.02

0.01

0

-0.01

-0.02

Mea

sure

d –

Mod

eled

(db/

inch

)Low Frequency Modeling Results

(measured – modeled)

Causal Model

Classic Model

Tand Technique

Copper PowerTechniqueRoughness withConstant Tand

• Hammersted model good fit at low frequency.• Adjusting Tand underestimates losses at low frequency.• Adjusting copper power technique overestimates losses at low frequency.


Modeling Errors at High Frequency

0 5 10 15 20Frequency (GHz)

Mea

sure

d –

Mod

eled

(db/

inch

)

0.20

0.15

0.10

0.05

0

-0.05

Causal Model

Classic Model

Tand Technique

Copper PowerTechniqueRoughness withConstant Tand

High Frequency Modeling Results(measured – modeled)

• Hammersted causal model good fit at high frequency.• Non-causal model overestimates losses at high frequency.


Conclusions – Nonclassical Copper Losses• Loss contribution of roughness is linear versus frequency.

– Loss can be modeled as a shift in tand.– Results in > 0.5 power of classical copper loss model; but power fit is frequency

dependant.• Copper roughness significantly increases microstrip tranmission line

losses.– Lower roughness results in less signal loss at high frequency.– Roughness variation among copper types can be significant and controlled.

• NiCr resistive layer 100 Å thick did not increase loss.• Hammerstad-Jensen approach forced to be causal by using the

frequency dependence of Tand provides best result across entire frequency range.

• These stripline loss magnitudes not seen in real life with rough copper.

– Future tests with foils of various roughness begun with microstrip configuration.


Acknowledgement• M. Sakamoto, R. Wiechmann, and J. Wang for copper foils used

in this test and roughness data.• D. Williams of Proto Circuit (now Cortec) for board fabrication.• G. Brist of Intel for high frequency measurements.

Advanced Technology Workshop on Passive Integration

PCB Technology Symposium April 2005 © 2005 IBM

Embedded Passives for Digital System Applications

M. Cases, N. Pham, D. N. deAraujo, P. Patel, B. ArchambeaultIBM CorporationSystem and Technology Group


© 2005 IBM2 PCB Technology Symposium 2005

Outline

Digital system trends

Impact on design parameters

Role of embedded passives

Embedded passive benefits

Application examples for digital systems

Design issues and challenges

Conclusions



Digital system trends: Core and I/O frequency trends

Clock Frequency

0

1

2

3

4

5

6

7

1989 1991 1993 1995 1997 1999 2001 2003 2005

Year

Freq

uenc

y (G

Hz

or G

bps)

CoreBus(SDR)-SEBus(DDR)-SEBus(DDR)-DIFFBus(HSS)-CDR



Digital system trends: CMOS technology

91 93 95 97 99 01Year

0

0.5

1

1.5

2

2.5

3M

pitc

h/Le

ff (u

m),

Tox(

nm/1

0)Leff(um) Tox(nm) Mpitch(um)

Device Parameters

5.0v

3.3v2.5v

1.8v1.5v 1.2v

Source: SIA Tech. Roadmap, 1999



Impact on design parameters

Careful design of power and signal distribution systems including EMI effectsSignal distribution parameters– Clock and signal jitter– Signal attenuation and crosstalk– Inter-symbol interference

Power distribution parameters– Impedance profile– Decoupling requirements

Need integration of power and signal distribution design



Role of embedded passives

Increased performance

Increased functionality

Reduced EMI

Increased packaging density

Potential for decreased cost

But, we need to address:

Design and implementation issues

Manufacturing yield

Total cost competitiveness



Embedded passive benefits

Improved signal quality– Lower ESLReduced power supply noise– Lower ESR, ESLLower EMI generationEliminates discrete components from assemblyLower board assembly defectsLower board size potential– Increased wiring channels– Improved component densityImproved board reliability



Buried inductor construction

Curved trace to a viaStacked on adjacent planes to increase valueFeasible to build 8 nH per data bitIncreased edge rate

via



Buried resistor construction

Resistor paste/foil available for various resistivities– 25, 50, 100, 250, 1000 Ω/

– Can be mixed to fine-tune the target resistance value

– Resistor value proportional to L/W ratio

Size of structure determines current carrying capability



Annular buried resistor construction

Via

Trace

Outer copper ring

Inner copper pad

Resist ink

Tighter tolerance than linear resistorWider structure than linear resistorWell suited for capacitor ESR control

AVP technique



Buried capacitor construction

Courtesy of Netlist Inc.



Application examples for digital systems

Decoupling capacitors– Core and I/Os

– PCBs

– Substrates

Memory DIMMs– Resistors and capacitors

HSS links– AC coupling



Embedded decoupling capacitors for PCBs

Test board vehicle:– 10” x 12” board with split planes

– Two identical test boards• Standard FR4 board

– 35 mil gap between power/ground plane pair– Populated with 99 0.1uF SMT capacitors

• Embedded capacitance board– 16 micron gap between power/ground plane pair– Relative dielectric constant = 16– No discrete capacitors installed on board



Test board definition

‘Traditional board' (FR4, 35 mil thickness):

section #1 capacitance = 1,706 pF


‘Buried capacitor board' (Er = 16, 16 micron thickness):

section #1 capacitance =352,750 pF




S21 (port-port) measurements for section 1



S21 (port-port) measurements for section 2



Embedded decoupling capacitors for substrates

Test vehicle:– Existing design in laminate substrate with IDC caps

– Redesign substrate using 6+2 laminate technology• With and without embedded capacitor layer

– Embedded capacitor structures used only for I/O voltage decoupling• Core voltage decoupling required higher capacitor value



3MTM embedded capacitor material key properties

94V-0Flammability Rating

Epoxy, ceramic fillerResin systemMeets X7RFreq., Voltage, Temperature~130V/umDielectric Strength>100V**Breakdown Voltage35 umCopper Thickness

0.03Dielectric loss @ 1GHz16Dielectric Constant

5.5 nF/in2*Capacitance /areaValueAttribute

* For 16 um dielectric thickness. Thinner dielectrics in development** Higher breakdown voltages in development Courtesy of 3M Corporation



Substrate cross section (6+2 laminate)

L4 - Gnd/Pwr PlaneL5 - Gnd/Pwr Plane

L3 – Signal LayerL2 – Power PlaneL1 - Pad Layer

L7 – Power PlaneL6 - Signal Layer

C4 Bump Side

BGA SideL8 – Pad Layer

Buried ViaBlind Via

30µm ADM 8µm C-Ply Corew /18 µm copper planes

8µm copper signal layer metallization

Courtesy of 3M Corporation



ASIC component description

Die size: 15.6mmx15.6mm

Package: 42.5mmx42.5mm

Total pin: 1680

– 1207 IOs, 233 GNDs, 240 PWRs

– 6 power supply voltages + gnd

Power: 46 W

Critical I/Fs: FSB, IB, SP, MEM

VDD VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD VD2

VD3

VD2VD2

VD3 VD3

VD3

VDD VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD VD2

VD3

VD2VD2

VD3 VD3

VD3

Package Top View



Actual substrate design cross section

FSBVD2

MEMVD3

TopVDDS1GND

PWRS2GND

BottomIO Power Planes

IBVD5

PCIXVD4



S21 measurement for an I/O voltage island

C=9.86nFC=1.33nF

S21

-90

-80

-70

-60

-50

-40

-30

-20

-10

010 100 1000 10000

Frequency (MHz)

S21

Mag

nitu

re (d

B)

EmbeddedNone

1200 mΩ

162 mΩ

630mm2



Memory DIMM embedded passive attributes

Saves board surface area for more DRAMs capacity

Reduces board height to meet mechanical constraints

Reduces placed parts count

Increases reliability

Improves signal integrity

0.72”




BladeCenterTM applicationReduces amount of board space required for memory subsystemFour 25 deg angled DIMM sockets: 21 sq. in.Four vertical VLP DIMM sockets: 8 sq. in.

DIMM 1DIMM 2DIMM 3DIMM 4



DIMM comparison: with and without embedded passives

Using embedded resistors

Using embedded resistors Using

embedded resistors

UsingSMT

resistors4 mm

keepout



Example of DIMM design improvements

CKCK#

CKCK#

RT

4RT

DQ DQRS

RS

RS

DRAMs DRAMs



Memory address line eye diagram simulationJEDEC: 4.49 ns window @ 333 MHz

NETLIST: 4.65 ns window @ 333 MHz




Signal integrity comparison for address and data lines

Address lines: Embedded vs. discrete resistors Data lines: Embedded vs. discrete resistors




HSS link applications

Provides increased bandwidth per channel and extended link lengths and data rates– Terminated differential signaling network– CDR techniques, channel equalization, AC coupling

AC coupling increases link length and reduces link losses– Either capacitor or inductor coupling– Today’s industry standard is capacitive coupling

Typical capacitor value is 5 nF per signal line– Discrete capacitor parasitic introduces signal jitter/skew– Requires high capacitance density embedded structures– Requires high bandwidth singulated capacitor structures



Typical HSS link configuration (single line)

Driver

C_chip C_module

ConnectorPkg Card

StandardCable

Connector

C_chip C_module C_conn

Card

Receiver

Pkg

C_conn

Card

AC Coupling

Device



Design issues and challenges

Slew rate

Voltage

LayerTime

PowerFreq

Years

Increasing

Reduc

e tim

ing m

argin

Low freq. n

oise

High freq. n

oise

Noise margin

Simulation

Components



Design issues

Resistors– Tolerance, uniformity, stability, voltage rating, TCR, STOL,

reliability

Capacitors– Tolerance, leakage, breakdown voltage, frequency dependency,

TCC, reliability, stability, aging

Modeling– Electrical, mechanical, etc.– Must include effects of wave propagation in the specimen section

CAD tools– Methodology and integrated tool suite– Efficiency, checking, extraction



Manufacturing and test issuesYield and tolerance controlWide spread of resistor and capacitor valuesDesign parameter control– Film thickness, etching, etc.– Laser trimming cost trade off

Test structures for manufacturing control– Correlation to actual design structures

Test parameters and test methods– ρ, Ζ, κ, tan(δ) over frequency range– High frequency test methods and fixtures required

Devices are no longer lumped elements but distributed networks



Conclusions

Presented several advantageous digital system applicationsEmbedded passives can offer significant benefits for high-density high-frequency digital applications– Size, cost, performance, design margin, reliability

Design, test and manufacturing issues need to be addressed efficiently for rapid adoption– CAD methodology and tools for design, modeling and

verification– Test methodology and standards for broadband testing– Design parameter control and manufacturing yield

containment

Attenuation sources, Attenuation reduction and wiring challenges

Panel DiscussionDale Becker, Chairperson

April 20, 2005

High-Speed is here

• Choosing the right interconnect

Rick Merritt EE Times (04/11/2005 9:00 AM EDT) A gigabit per year. That's the speed at which designers are accelerating, our recent Web survey of 243 backplane and chip-to-chip interconnect developers found.

Panel Discussion

• The purpose of this panel is to discuss the best design practices and tradeoffs for implementing these interfaces and which PCB technology developments give the most leverage for maximizing the frequencies or minimizing the bit error rate these interfaces can attain.

Achieving reliable high-frequency• Interface Specifications• Technology Options

– Low Loss, Stubless Vias, Matched Impedance• System bandwidth requirements

– Signal technology• System tradeoffs

– Bandwidth, density and distance• Design tools as an enabler

– Low Noise, routing constraints, constraint verification• Modeling challenges

– Frequency dependence, Time and frequency domain• Measurement verification

– Eye, Jitter– Impedance, discontinuity

Panel Members

• Franz Gisin, Sanmina-SCI• George Katopis, DE, IBM-STG• Steve Rosser, Endicott Interconnect• Todd Takken, IBM, Yorktown Research• Ed Sayre, North East Systems Associates• Lei Shan, IBM, Yorktown Research• Ken Taylor, Polar Instruments• Ken Willis, Cadence

Key Note

Katharine Frase, VPIBM Corp.

STG

In every generation, the electrical and mechanical requirements on chip packaging, boards and assembliesincrease. Over the past decade, these requirements have largely been in the areas of interconnect density (tosupport the transition to surface mount packages) and higher speed signal trace integrity. Historically,packaging technology has been defined to meet the high performance needs and ‘trickled down’ to otherapplications. However, high volume applications can no longer be satisfied by such an approach. In addition,trends are emerging in both areas to complicate our roadmaps. Several of these trends (lead-free assembly,increased power density, reduced drive voltages, and three dimensional mechanical interactions) will bediscussed in the context of chip carriers, packaging and board requirements.


IBM eSystem Roadmaps: Technical Challenges and Environmental Compliance

C. DeCusatis and J. QuickIBM Poughkeepsie, New York

The European Union has recently adopted a series of environmental directives which affect computersystems, high speed printed circuit boards, and other products. These regulations include the Restriction ofHazardous Substances (RoHaS) Directive, which restricts the use of lead, mercury, cadmium, hexa-valentchromium, and certain flame retardants in electrical and electronic products. This Directive applies to allelectrical and electronic products placed on the European Union market after July 1, 2006, although there area few exemptions related to the use of lead solder in network infrastructure equipment. Similarly, the WasteElectrical and Electronic Equipment Directive (WEEE) Directive mandates the necessary treatment ofelectronic product disposal, reuse, and recycling. Finally, the Energy-Using Products (EuP) Directive,although still in draft format, is expected to be enacted in 2005 and establishes guidance for the integration ofenvironmentally friendly aspects in the design and development of new electronic products. While thesedirectives have broad implications, they particularly impact server and storage computer products andinput/output (I/O) interfaces for high speed digital communication. Applications which rely on fiber opticcomponents, transceivers, and cable assemblies face unique challenges in both adapting current card designsand insuring that future product roadmaps comply with these directives. In addition, emerging technologiessuch as high speed optical backplanes and interconnects will face unique fabrication requirements.

IBM is committed to full compliance with these directives, and has been participating in consultations withthe European Union and the Technical Adaptation Committee in an effort to ensure that the finalimplementation requirements of the Directives consider the ultimate long term reliability and quality of publicand private computing infrastructures. IBM has also been actively collaborating with suppliers, contractmanufacturers, industry consortiums, and other supply chain partners in order to achieve compliance withthese directives. In this paper, we will provide an overview of IBM’s leading I/O connectivity products andsolutions which are impacted by these directives, and discuss new design methods being adopted to insurecompliance. Technical issues related to high speed (1 - 10 Gbit/s) fiber optic links, including opticaltransceivers, cables, and sub-floor cabling systems, will be discussed. Both serial and parallel optical linkswill be considered. Extension of these approaches across the entire networking ecosystem, including opticalswitches, directors, and channel extenders, will also be presented.


IBM PCB Technology Requirements

Bruce ChamberlinIBM Corp

ISC- Procurement Engineering

PCB technology is being pushed in several, sometimes opposing, directions by the various technology drivers.By looking at all of the system and PCB requirements, it becomes clear that extrapolation from previous PCBtechnology roadmaps is no longer valid. We have reached a point where some requirements, such as signalattenuation limits, will significantly change the direction of the PCB roadmaps. This presentation will layoutthe key PCB technology drivers, from IBM's perspective, for the foreseeable future. Technology driversrelated to system performance, environmental legislation, and business will be discussed. Specific IBMdesign points will be used to illustrate the currents trends, future challenges, and to point out where newtechnologies may be required or beneficial.


IPC PCB Roadmap

Jack FisherInterconnect Technology Analysis

Austin, TX

In 2004 – 2005 several new electronics industry roadmaps will appear. NEMI released their roadmap inFebruary of 2005, IPC’s roadmap will appear in April and the next ITRS will be available late in 2005. Thispresentation is titled “What do the roadmaps say”, and will look at the business, regulatory, market andtechnology issues that the roadmaps perceive as having an influence on the printed circuit board industry forthe near term and long term periods.


Gigabit Dielectric Material Studies - Low Loss Material Comparisons andPerformance Rankings

Dr. Edward P. Sayre, P.E.Mr. Michael A. Baxter

North East Systems Associates, Inc.235 Littleton Raod, Suite 2

Westford, MA 01886www.nwsa.com

The primary goal of this program was to show a clear “” of backplane suitable PCB material lossperformance in both the time and frequency domains based on a variety of Electromagnetic and SPICEcircuit simulations, and confirmatory measurements based on test articles specifically designed to matchthe simulated physical designs.The phased program considered a number of dielectric materials in use in the PCB and backplaneindustry including two (2) non-commercial low-loss materials.1. In Phase 1-A, Point-to-Point 100 Ω differential lossy transmission models were built from thedielectric material data sheets. The materials were evaluated using Electromagnetic fieldssolvers and H-SPICE for TDR Impedance, Time Domain Transmission (TDT), Gigabit eyediagrams(2.5Gbps, 5Gbps & 10Gbps) and frequency domain S-Parameters to (1 MHz thru10 GHz).2. In Phase 1-B, a similar program was completed for Point-to-Point backplane interconnectsusing the same dielectric materials. The Gigabit backplane interconnects included commerciallyavailable Gigabit backplane connectors (the HM-ZD).3. Phase 2 involved the creation of physical test vehicles, designed using common digitaltransmission trace parameters to evaluate the dielectric transmission and loss properties of threecommercially available low loss PCB materials. Correlation of Signal Integrity measurementsconducted on the fabricated test articles against theory, H-SPICE simulations and themanufacturers’ published dielectric properties.This paper will present summarized results from each of these phases. The results to be presented aresomewhat sup rising and point out the importance of surface roughness of the copper foil and the featuresize of the PCB reinforcing glass and resin vis-à-vis the trace dimensions.


Physical Design of High Speed PCB

Gisbert ThomkeIBM Corp.

Contents:

Design Tools used/available (Cadence, IBM)Constraints that can be handled (length, diffpair, noise, ..)Costs of constraints from a design system view (TAT, ..)Manual routing versus autoroutingLength errors caused by wiring structuresManufacturable structures versus electrical preferred structuresDesign effort and tools support for specific structuresChecking the designDesign for manufacturing (allow flares, ..)Examples of designs for high end Z-series



Alina DeutschIBM T. J. Watson Research Center

1101 Kitchawan Road, Yorktown Heights, NY 10598

Continued advances in data-rates of high-performance systems require increasingly more accurateinterconnection modeling capability. Such enhanced models for transmission-lines that propagatemulti-gigahertz signals depend upon accurate material characterization. Therefore, measurement bandwidthneeds to extend into the many tens of gigahertz. In the past, the slower rise times that were used were tolerantof less accuracy or even non-causal models. Suppliers provided single value dielectric and loss tangentinformation, TDR-based impedance, and maybe some limited attenuation data. For multi-gigahertz operation,the broad spectral content of variable data-pattern parallel or serial links is generating renewed interest inenhanced measurement techniques. New materials are being developed in order to make possible high-speedsignal transmission. Such materials need to adhere to stricter requirements of lead-free processes and lowermoisture absorption. New fabrication techniques need to be developed without the traditionalroughness-enhanced surface since losses caused by the high-resistance rough ridges have been shown toincrease loss by 5-50%.

All these new materials need to be accurately characterized in configurations that are representative of actualuse. Designers need the material parameters in order to generate broadband, predictive, causal models for awide range of configurations or applications. Traditional frequency-domain characterization techniques, usedfor simpler structures, have been unable to extract the material properties due to the very large interfacediscontinuities present in most cards or boards. New de-embedding techniques are being investigated.

A very simple time-domain technique based on short-pulse propagation [1] will be shown to be able to extractthe complex permittivity for printed-circuit-board materials over the frequency range of 2 GHz to 40 GHz. Itrelies on the use of special, representative test vehicle, wide-bandwidth sampling oscilloscope, signalprocessing, and iterative modeling based on causally enforced field solution [2]. An analytic function basedon the Debye model for the complex permittivity is used to generate causal transmission-line models over the10 KHz to 50 GHz frequency range for key system performance predictions.

Reference[1] A. Deutsch, T-M. Winkel, G. V. Kopcsay, C. W. Surovic, B. J. Rubin, G. A. Katopis, B. J. Chamberlin, R.S. Krabbenhoft, IEEE Trans. Advanced Packaging, vol. 28, no. 1, Page 4-12, Feb. 2005.[2] W. T. Weeks, L. L. Wu, M. F. McAllister, and A. Singh, “Resistive and Inductive Skin Efrfect inRectangular Conductors”, IBM Journal Res. Develop., vol 23, pp.652-660, 1979.


"Packaging Trends & Challenges

Voya Markovich, Chief Technology Officer and GM for R&D and IP

Endicott Interconnect Technologies, Inc.

In today’s market for high performance PWBs, there are two seemingly opposing drivers. The first driver isfor enhanced electrical performance, primarily in the area of clock speeds and data bandwidth. For the last 20years, the computer industry has been basically following Moore’s law. This law states that the number oftransistors used in an Integrated Circuit will double every 18 months. To accomplish this, the size of thetransistor is made smaller and is packed closer together. This packing is done with finer and finer lithographictechniques where now transistors are in the 90 nano meter size features. When the transistors are packed thisclose together, the time it takes to go from one transistor to the next is reduced thus the circuits can be madeto run at higher clock speeds. This speed increase allows a microprocessor to perform calculations at an everincreasing rate The second major driver in the market is for higher integration of functions available on a single part, this caneither be achieved by using larger ASICs or by adding more components onto a given board space. Puttingmore components onto a PWB requires tighter wiring densities to fit all the signals necessary for thecommunications between all the components. Line widths are being pushed to the limits of existingphotolithography where 0.001” lines on redistribution layers and 0.002” lines in inner cores are used. Thisallows for more lines per channel to escape the various components. As the speeds increase in these high end server boards, more attention must be placed on the attributes of theindividual elements used in the construction of these boards. Characteristics of the circuitry are now moreimportant. While Moore’s law require the transistors to get smaller and smaller, the speed increases in theboards drive the copper being used to transmit the signals in the opposite direction. The line widths in today’shigh complexity high reliability server boards are from 0.003”-0.004” (3-4 mils). These lines will now moveto widths of 0.005” (5mils) and wider to improve the signal integrity with the faster clock rates. In order to accommodate the wider lines, a stumbling block has been identified. To achieve a givenimpedance for the signal lines, thicker dielectric needs to be used between the signal plane and the referenceplanes. A rough approximation of the dielectric thickness equal to the line width For Example, for a 5 milwide trace, the dielectric material needs to be 5 mils on top and 5 mils on the bottom of the signal plane. Another consequence of wider lines is the need to increase the number of signal planes needed. This isprimarily due to the reduction in wiring density in the high congestion areas such as under an ApplicationSpecific Integrated Circuit (ASIC) or microprocessor. For example, where the escape using a 3 mil line is 3lines per channel, going to 5 mils will reduce the number of lines per channel to 2. To achieve the samenumber of interconnects, we will have to increase the number of signals planes along with reference planes tocomplete the design. PWBs utilizing these wider lines will require board thickness to go up 0.050” to 0.150”from current thickness. This of course depends on the density of the component being escaped.


Non-Classical Conductor Losses due to Copper Foil Roughness and Treatment

Sid Clouser and Jiangtao WangGould Electronics

In high speed digital interconnects, signal attenuation is a result of both dielectric losses and conductor losses.Previous works have shown the characterization and modeling efforts regarding the impact of dielectric lossin PCBs and the differences between various dielectric materials. Most high speed characterization modelingefforts have not encompassed the variations in conductor losses due to variations in copper foil roughness andtreatments of copper foil for adhesion. Several recent publications have reported frequency dependent copperlosses that do not follow the classical square root relationship. This presentation shows the results of highfrequency loss characterization of various copper foils and the impact of copper roughness on the relationshipbetween conductor loss and frequency. Also discussed in this presentation are the implications in highfrequency modeling resulting from non-classical conductor losses and the impact on causality in simulationresults.


Embedded Passives for Digital System Applications

M. Cases, N. Pham, D. N. deAraujo, P. Patel*, B. Archambeault*IBM Corporation, Austin, TX

*IBM Corporation, Raleigh, NC

Future digital systems require the interconnection of functional components with high performance,high functionality and high reliability. In the year 2010, ITRS projects on-chip clock frequency of 10 GHzand off-chip clock frequency of 3 GHz. These frequencies require careful design of both the power and thesignal distribution systems at the electronic packaging level including radiated emission requirements. Thisincludes chip, module, board and cable subsystems. These lead to signal distribution parameters such asclock/signal jitter, signal attenuation, signal crosstalk and inter-symbol interference; and power distributionparameters such as bandwidth, impedance and decoupling. The integration of both signal and powerdistribution in a package that meets the system design parameters enables the digital processing at highspeeds.

This paper investigates the role of embedded passives such as resistor and capacitors in theenablement of future high speed digital systems. They present opportunities for increased performance,increased functionality, increased package density and decreased cost. For example, as the I/O frequencyincreases for critical system interfaces, the need for low parasitic decoupling capacitors increases requiringtheir close proximity to digital components and higher capacitive density in electronic packages such asprinted circuit boards (PCBs) and laminate substrates. Another example is found in highly dense memorysubsystems where decoupling capacitors and resistor terminators are embedded providing low-profile DIMMsand higher memory capacity with improved design margins. Similarly, as the use of high speed serial (HSS)links becomes more prevalent in digital system interfaces, the use of AC coupling capacitors and moreeffective I/O decoupling becomes critical for proper functionality at high speeds. This paper also describessome of the issues and challenges encountered in the area of design, implementation, total cost andmanufacturing yield.


Panel I: Attenuation sources, Attenuation reduction and wiring challenges

Moderator: Dale BeckerPanelist:Steve Rosser, EIFranz Gisin, Sanmina SCIEd Sayre, NESAGeorge Katopis, DE, IBM-STGTodd Takken, IBM, Yorktown ResearchLei Shan, IBM, Yorktown ResearchTBD, CadenceKen Taylor, Polar Instruments

Multi-GHz signals have become commonplace in printed circuit boards applications. Whether they are seriallinks using standard cores or parallel links using custom transmit and receive circuits, the challenges ofdesigning, characterizing and verifying these interfaces for use in production printed circuit boards havesimilar challenges. The purpose of this panel is to discuss the best design practices and tradeoffs forimplementing these interfaces and which PCB technology developments give the most leverage formaximizing the frequencies or minimizing the bit error rate these interfaces can attain.


RoHS PCB Assembly Update

Jim WilcoxIBM Integrated Supply Chain

The general industry strategies for meeting the EU Restriction of Hazardous Substances Directive (RoHS) arenow widely known. While the directive expressly targets the PCB industry for the elimination of PBB andPBDE fire retardants from laminate resins, many OEM manufacturers such as IBM have already removedthese substances from their material supply chain. The most serious RoHS impacts are therefore associatedwith the elimination of the element Pb. Pb, in the form of SnPb eutectic solder, has become a key material inconventional Printed Circuit Board Assembly (PCBA) manufacturing. This must now be eliminated, not onlyfrom the board attach process, but also from component and board surface finishes.

The most prevalent material substitutions planned for SnPb eutectic solder are near eutectic SnAgCu ternaryalloys. The melting point of this family of solders is roughly 35°C above that of eutectic SnPb.Consequently, PCBs intended for RoHS compliant or Pb-free assembly must be capable of surviving suchelevated temperature exposures without performance or reliability impact. Exposure to Pb-free assemblytemperatures can generate a host of internal PCB damage mechanisms, some not readily apparent to thecontract assembler. The specific temperature exposures required can vary substantially depending on theassembly processes required for the particular PCBA in question. This discussion will review the scope oftemperature exposures that the laminate supplier should anticipate for Pb-free applications. The range ofpotential exposures will depend on the component bill of material and the particular assembly processesrequired.

Specific items to be discussed include peak temperatures and dwell time requirements for surface mountattach, SnAgCu wave solder requirements, and local thermal exposures associated with component rework.Issues of concern include card warpage behavior, delamination and internal voiding. Of particular interest tothe OEM PCB consumer will be a thorough characterization of the cumulative damage incurred by variouslaminate material selections with repetitive high temperature exposures. Other PCB technical challengesassociated with Pb-free assembly will also be discussed.


Resin Developments Targeting Lead Free and High Speed Applications

Bob HearnEpoxy Products and Intermediates R&D

The Dow Chemical Company

Proposed legislation to ban the use of lead based solder in printed circuit boards (PCB) and the higherprocessing temperatures of the lead free replacement solders has caused a change in direction for technologyimprovements. The higher processing temperatures create the need for PCBs with increased thermal resistance.Thermal resistance can be characterized by several types of measurements. The thermal decomposition (Td) point is onereference. Typically, this is the temperature at which 5 wt % of the material laminate is lost to volatile decompositionproducts. Another widely used method is the time to delamination at an elevated temperature after water exposure.Commonly used temperatures are 260, 288 and 300 deg C. The sample delaminates when the internal pressure fromgaseous decomposition products is high enough that the sample cracks and changes dimensions.

A standard high Tg FR-4 material has a T260 (time to delamination at 260 deg C) value in the range of 10 min.and a T288 of 0 min. The Td is in the range of 300 deg C. Lead free solders reflow temperatures are expected to beabout 20 deg C higher than lead based solders. This is posing a serious threat to the standard FR-4 materials.Evaluating data from several different materials with different times to delamination at different temperatures andutilizing the Arrhenius law of kinetics, aA sensible limit for lead free specifications might be a T288 of 6-7 minutes anda Td of 320 deg C. These values were estimated by evaluating data from several different materials with differenttimes to delamination at different temperatures and utilizing the Arrhenius rate law.

The source of the decomposition of cured epoxy resins is the presence of bromine from the flame retardantand/or nitrogen from the hardener. Thermal stability is increased when either one or the other is removed or reduced.The removal of bromine has the largest effect. For example, non-brominated FR-4 systems are capable of reachingT300 times of over 30 min. However, the introduction of flame retardants other than the traditional TBBA isaccompanied by either a heavy cost burden increased costs and/or by a reduction of performance e.g. humidityresistance. For this reason, halogen free materials are not necessarily considered the best answer for lead free solderapplications.

The preferred answer from the industry to cope with the higher thermal requirements is to exchange theentrenched hardener dicyandiamide (dicy) with various types of phenolic hardeners. The phenol novolacs can displaceup to 30 % of the brominated epoxy resins subsequently lowering the bromine content in the laminate. It is not wellunderstood if the lower bromine content and/or the elimination of nitrogen are improving the thermal reliability.

Unfortunately, the change in hardener is also affecting the processing conditions and other properties of thePCB. Phenol novolac hardened systems are known to exhibit brittleness when drilled and have poor copper peeladhesion. The change in the polymer network (e.g. crosslink density, polarity, etc.) has significant effects on suchimportant properties. Correlations are currently being developed between resin toughness and failure modes likedelamination, plated through hole cracks, and copper track disbondment. The objective is to have these parameterswithin the same range as current dicy systems. New test requirements, like IST or the accelerated automotive cyclingtest require more and more materials which not only pass a static temperature requirement but also dynamic/cyclingstress.

With these issues in mind, Dow has developed new products which are suitable for lead free application andcover all Tg ranges. Additional property features like bromine free or low dielectric constant materials (low Dk)complete this portfolio. The resin designed for high speed applications exceeds the limits for lead free application andhas the additional value of generating laminates with a Dk lower than 4.0. This material has been optimized forprocessing and exhibits excellent drilling characteristics. The resin can be used to manufacture high layer count, highdensity multilayer boards, backplanes, and surface mount multilayer for assembly of ball grid array’s (BGA) or otherchip scale packaging (CSP).


Qualification of PCB Fabricators / Standard Loss Tangent Laminates forLead-free Soldering Survivability

Wayne RothschildIBM Corp.

Thermomechanical stresses experienced by a PCB during soldering processes will increase in moving fromtoday's tin/lead solder to tomorrow's SAC solder. Most of this increased stress is due to the increasedinfluence of the higher temperatures upon the resin component of the PCB laminate material. These stressesmay cause irreversible damage to the laminate itself and/or to copper features, resulting in the creation ofopens and/or shorts within the PCB, as well as opens in PCB-to-component connections.

It is reported that the creation of reliable SAC solder joints requires at-the-joint soldering temperatures ofabout 235 C. As the combined thermal mass of the PCB and of the to-be-attached components increases, thetemperature at the PCB surface increases. Survivability of PCBs comprised of many of the laminates that arein common use today becomes increasingly compromised, changing from putting the onus on CMs to tightlycontrol process windows to eventually becoming impossible as thermal mass increases.

This presentation will provide an overview of the process that IBM Dept HT9 is undertaking to qualify PCBfabricators to produce PCBs that will meet System Group reliability requirements after exposure to lead-freeprocessing, using laminates that the fabricator is currently qualified to use for today's applications or usingnew laminates. High-level lessons learned will be shared from the testing that has been undertaken thus far.


The Impact of Lead–Free Assembly on PCBs

Gail TennantCelestica

Toronto, Canada

The RoHS deadline is quickly approaching and the electronics industry in general is desperately trying toprepare for its overall impacts. The technical experts charged with the task of accumulating data for thelead-free assembly environment in 5 years will replace 50 years worth of experience and data in the leadedassembly environment. The removal of lead has resulted in a reflow temperature increase of 34oC, and thischallenge is further intensified when considerations are made for wave solder and rework that will requireeven higher temperatures. The industry to date has directed most of its efforts on the evaluation and testing ofsolder joint metallurgy, component compatibility & survivability, and final joint aesthetics.

The heightened temperatures have resulted in numerous effects on electronic components and PCB’s, rangingfrom increases in MSL (moisture sensitivity level) ratings, to laminate delamination/micro hardening, toreliability issues to name a few. All of these effects have resulted in the need to develop new processes andprocedures in a lead-free assembly environment.

This presentation will investigate some of the impacts on the assembly process when moving from leaded tolead-free. The discussion will review the challenges the EMS will face in three key areas; inspection,reliability and the supply chain.


Panel IIMaterials, Processes and Reliability for Lead-Free Applications

Moderator: Roger KrabbenhoftPanelist:Wayne Rothschild, IBM- ProcurementMitch Ferrill, IBM- ProcurementDoug Trobough, MerixDave Backen, TTM Jim Wilson, EIBill Varnel, PolycladSean Mirshafiei, Isola Bob Carter, MEW/MEM Steve Feltham, Sanmina-Sci Bob Hearn, Dow Gail Tennant, Celestica The aggressive requirements of Pb-free assembly and rework processes will induce added stress to currentand future printed circuit board designs. This is exacerbated by the increased thermal mass of futurecomponent packages and large planar designs. This added stress has the potential to reduce the long termreliability of traditional printed circuit board and assembly structures. A panel of IBM engineers and PCBmaterial / fabrication suppliers will discuss the potential relative impacts to long term reliability, meaningfulassessment methodologies, and risk mitigation techniques.


Embedded Passives Cost Analysis

Chet PaleskoPresident

SavanSys Solutions LLC

This presentation provides an overview of the cost tradeoffs between board designs using discrete passivesand board designs using embedded passives. All of the key manufacturing cost drivers and differencesbetween these two implementations including materials, board fabrication processes, board yield, sizedifferences, assembly cost, and assembly yield are included. The economic characteristics of thin film andthick film technologies for both resistors and capacitors, as well as new promising technology is alsopresented. Finally, design characteristics suitable for cost effective embedding are described and an exampletradeoff is included.


Panel IIIPCB Cost Drivers

Moderator: Erica Jasper Gant, IBM- ProcurementPanelist:Pravin Patel, Justin Bandholz or Kris Clinard, IBM- xSeries/ BladeCenterRandy Kolvick, IBM- HE xSeriesDan Massey, IBM- pSeries/HVEd Seminaro, IBM- iSeries/HVMike Fisher, IBM- iSeriesHarald Pross or Dale Becker, IBM- p/zSeries? (Storage)Peter Fanelli or Patti Sulger-Phelan, IBM- ProcurementPS Hou, IBM- ProcurementRoger Krabbenhoft, IBM- Development

In our On-Demand market, customer preference has taken the front seat on the road of technologyadvancement. Customer preference demands performance across every price bracket. IBM is workingaggressively to meet those cost targets, but with an incomplete understanding of the complex cost matrix forraw card and assembly fabrication, this is becoming more challenging to achieve. A more in-depthunderstanding of the cost matrix interactions is vital for IBM to design systems which can capitalize on theproficiency of our vendors, the commodity market of components and the market share profits we wish toattain. The panel of IBM development and procurement engineers will share general cost challenges by brandand give direction on what vendor feedback is essential for IBM to make design decisions which will be mostcost-efficient. Frustrations from previous cost sizing activity will be shared, and a new survey will bedistributed to vendors in attendance for their feedback in response to the cross-brand information presented.


Poster 1Influences of Fiberglass Fabric on some causes of CAF

Bob Luppino, Danna Kelley-Haddad and Bob St. PierreHexcel Reinforcements

The trend in the design of printed circuit boards is toward finer lines and spaces. This has led to concernsabout potential failures due to Conductive Anodic Filamentation (CAF). CAF is often attributed to eitherincompatibility between the surface finish of the reinforcement and the matrix resin or to incomplete wettingof the fiber by the resin.

Fabric/resin compatibility and completeness of wetting can be modified through technology enhancements.The selection of silane coupling agents and other finish additives can influence the fiber-resin interactionthrough changes in surface properties such as surface energy and bonding site availability. Mechanicalprocesses can be used to improve wetting of individual fiber filaments through spreading of the yarn bundlesor opening capillaries between filaments.

This paper will discuss ways that fiberglass fabric properties can influence some of the causes of CAF.


Poster 2

Advanced PCB Technology to support High Speed Transmission

Yasuhito Takahashi Director

Interconnect Technology Fujitsu Microelectronics America, Inc.

Fujitsu Interconnect Technologies (FICT) is working to support server application beyond 2GHz andtelecommunication application beyond 6.4Gbps up to 10Gbps for next generation. FICT is ready to provide now;

1) MV1 technology that supported by high layer count straight stack up, sequential laminationtechnology, and standard HDI technology.

2) MV3 technology that supported by sequential lamination with HDI technology. Also MV5 that covered by full stacked all layer via technology is under development. FICT proposes sequential lamination structure (14-6-14, 34 layers, 2CH/1.0 mm grid) that can support10Gbps application with advanced low loss materials. MV5 technology is expected to reduce stub structureeven more by controlling stub length.


Poster 3

PWB MATERIALS: LEAD FREE, LOW THERMAL EXPANSION, AND HIGHFREQUENCY

Bob CarterMatsushita

PWB’s of today and tomorrow, demand laminates and prepregs that can meet the tougher lead freerequirements, provide superior thermal mechanical results, better electrical performance, and exceed thehighest reliability standards. This poster examines 3 material families, each designed with resin systems tomeet these requirements. Each resin system/ material offers its own unique combination of advantages for thePWB end user, designer, and fabricator. These materials vary in the interplay of thermal robustness andelectrical signal integrity properties. Data will show how R1755, Megtron Plus, and Megtron 5 are eachstrong PWB material choices depending on the designers needs.


Poster 4Lead free assembly and Laminate Materials

Tarun Amla Isola Group Sarl.Chandler Arizona

With ROHS and WEEE directives Lead free Reflow requirements will require use of much higher assemblyTemperatures. While there are many challenges on the component side and the selection of the appropriatealloy for use in the lead free process, this paper focuses on the challenges on the substrate material side.The Laminate Substrates need to be able to withstand much higher temperatures and multiple excursions up totemperatures over 260 Deg C. The paper is an attempt to look at the impact of various Thermal and physicalattributes at the Laminate level as well as the board level to withstand the lead free processing.The work here is intended to provide information to the user on the suitability of various materials for specificend use applications. The paper discusses the various inputs at the Product design and Process design stagethat will lead to robust lead free compatible materials. In this paper an attempt has been made to definethresholds for laminate thermal and attributes that shall lead to robust lead free compatibility.


Poster 5

Printed Circuit Board and Backplane Technology Solutions for High FrequencySystems

Franz GisinSanmina SCI

The High End Computing industry has escalating needs for increased bandwidth and reduced Bit ErrorRates. At the same time, electronic packaging drivers continue to push increasing wiring densities, smallerfeatures and finer line widths on Printed Circuit Boards. The PCBs and Backplanes for these applicationsdiffer significantly from their cousins used for consumer and portable applications such as cellular phones.Signal Integrity, reliability and performance at reasonable cost are paramount to successful productintroduction.

The design of high speed/high performance PCB and Backplane/Midplane interconnects operating at Gb/sspeeds must take into consideration a number of factors including the desired data rate, bit error rate (BER),total end-to-end signal attenuation and maximum allowable signal distortion. Interconnect building blocksthat impact these factors include the active drivers and receivers, connectors, PCB via geometries,transmission line lengths, and the locations of any impedance mismatches along the interconnect path. Avariety of solutions can be applied within each building block to create a high speed interconnect thatpreserves the “fidelity” of the signal propagating though it.

This poster board will present various building block technologies to achieve up to and beyond 10 Gbps datatransmission over long line lengths. Topics to be covered will include:

Thermal reliability and Electrical Characterization of High Performance Laminates Backdrilling and OptiVia Tm techniques for removal of parasitic via stub effectsUse of Advanced Buried Capacitance planes for improved power distribution at elevatedfrequencies.Cost effective Buried Resistor technology utilizing novel laser trimming for improved tolerancesComposite Material Stackups for high performance at reduced costHigh Speed Connector alternatives and tradeoffsHDI and Microvia strategies for increased wiring density Use of compensation techniques that correct for frequency dependent interconnect losses.Signal Integrity and modeling results of 10 Gbps transmission as demonstrated on aan ATCAcompliant Full Mesh backplane product.


Poster 6

The Role of Drilling in High-end PCB Design

Elec & Eltek

The trends in PCB design have continued to demand increase in circuit density, complexities, higher electrical as well asreliability performances. Environmental considerations also drive the use of environmentally-friendly materials and alsohigher PCB thermal reliability performance due to lead-free requirements. In combination, high quality and highreliability of the finished PCB become more critical than ever. Drilling capability is one of the key factors to achievesuccess in the competitive environment. This presentation will outline the key PCB designs affecting the drillingcapability and the consequential effects to the PCB performance.

This presentation will focus on the current trends and challenges in PCB drilling. The challenges are classified in threemajor sections:

· Complex technologies and designs· Use of exotic materials· High quality and reliability performance

1. Complex technologies and designs

This section will focus on the challenges brought by the nowadays complex designs which offer more functions aswell as electrical performances. Discussion will also be made on the effects of these designs to the drillingtechnical capabilities.

2. Use of exotic materials

High speed / low loss materials will become more commonly used to improve signal transmission speed as well assignal integrity. Environmentally-friendly materials and materials of higher reliability performances are alsodemanded. This section will focus on the effects on the drilling capabilities due to the use of the exotic materials.

3. High quality and reliability performance

High quality and reliability performance are essential for today’s PCB industry. This section will discuss theeffects of the drilling quality to the reliability performance such as IP separation, CAF and thermal reliability.


Poster 7

Balancing Cost and Performance in Lead-Free Compatible Base Materials

Ed Kelley & Bill VarnellPolyClad

Regulations restricting the use of lead in electronic equipment are posing very significant challenges to alllevels of the electronics supply chain. The higher temperatures required for printed circuit assembly withlead-free components adversely impacts the long-term reliability of conventional base materials used inprinted circuits, and may also result in defects during assembly. At the same time, cost pressures in theindustry are as intense as ever. Selecting materials that provide the required level of short-term reliability(through assembly), long-term reliability (via reliability, CAF resistance), and system performance (i.e.electrical performance) with the right cost and availability parameters is critical for both product quality andcompany profitability.

For base materials, these requirements impact each of the three main components; resin system, fiberglassreinforcement, and copper foil. In addition, control of the manufacturing process for both optimalperformance as well as product consistency is critical. This presentation will summarize the critical basematerial properties required and the influence the main components have on these properties and then presentthermal analysis data showing how properties can change upon exposure to thermal cycling to 260oC. Testingthat correlates performance in thermal analysis cycling (i.e. DMA and TGA units) with short- and long-termreliability is underway and initial data will be presented. The properties of a new mid-Tg/high-decompositiontemperature FR-4 material for lead-free applications will be introduced, and applications that may beappropriate for this material reviewed. It is expected that this product will offer an attractivecost/performance ratio for multilayer PCBs of intermediate complexity.

Finally, based on data from controlled testing, as well as field experience with various products, generalguidelines for selecting the most cost effective material for a given application will be presented. Theseguidelines will cover “standard FR-4” materials, as well as materials with improved electrical performance.


Poster 8

Failure Mode Characterization of IST Reliability Data

Keith G. Kitchens Principal Engineer

TTM Technologies Inc. Chippewa Falls, Wisconsin

As reliability of printed circuit boards continues to elevate, the complexity and cost of replacement continuesto increase. The complexities of manufacturing mandates that an ongoing reliability testing program includemethodologies that quantify the PTH (Plated Through Hole) interconnect integrity. One industrymethodology, IST (Interconnect Stress Testing) does quantify the PTH interconnect integrity. A processcharacterization study was performed to understand what the reliability data means. A large database of IST reliability data was characterized into four common modes of failure. Each of themodes of failure was scientifically examined to determine the process characteristics associated with eachmode. Based on laboratory failure analysis and experimentation a high correlation was developed for eachmode of failure. By understanding the failure modes associated with IST reliability data from a process perspective, newmaterials and processes can be quantitatively evaluated. The assessment of raw IST reliability data can beeasily interpreted in process terms utilizing this failure mode characterization.


Poster 9PWB Solutions for High Speed Systems

Jim StackEI

As system level clock speeds start to exceed 1 GHz in high end servers, the individual design and board levelmanufacturing attributes become more and more important. These attributes include trace width andthickness, dielectric materials, roughness of copper circuits, via structures and PTH stubs.

In this paper, the various attributes were modeled at different levels to understand the impact that eachattribute can have on total system performance. For this study, the system design was fixed, consisting of 3separate boards operating at 1.5 GHz with a net length of 80 centimeters and a total of 6 plated through holesin the net. Individual component adders (e.g. connectors, BGA solder, etc.) were not considered in this study. With the fixed design point, each attribute could be quantified and thus ranked in order of relativeimportance. Test boards were also built and measured to verify the model for several of these attributes.

Finally, various solutions to achieve the high speed performance improvements are suggested and analyzedwith respect to other impacts to the system, including system cost, ease of manufacture, wiring density andreliability. The end result will provide the system and board level designer with an understanding of variousperformance improvement options available and the tradeoffs associated with each of these.


Poster 10PCB Characterization Using a Recessed Probe Launch

Young Kwark, Christian Schuster, Lei Shan, Christian Baks, Jean TrewhellaIBM Corp.

Yorktown Research

Characterization of printed circuit board structures such as embedded transmission lines and vias has relied on surface launches using coaxial connectors or high frequency microwave probes to provide interfaces to testequipment. Both approaches require an access via to characterize internal layers which can severely distorthigh frequency behavior of the structure being measured. This poster describes a different access techniquethat allows a clean launch directly from microwave probes into a stripline structure. The quality of the launchis sufficient to permit characterization of small structures in excess of 40GHz.


Poster 11CAF Failure Mechanisms, Measurement and Options for the Future

Chung Li Industrial Park, Taoyuan Taiwan

Taiwan Team: Dr. Dennis Lin, Dr. Anderson Cheng, Dr. Song Lee, H.H. Lin, Nick Liang, Dino Chen, Martin Tung

USA team: Gold Circuits - Michael Griffin, (Georgia) Joseph Beers (New York)

Guest: DRF Solutions Inc Dr. Craig Hillman, (Design for Reliability) Maryland

With increasing densities and decreasing via to via spacing, the prospect of CAF induced failures in the fieldlooms more ominous, especially as assembly temperatures climb with the implementation of lead freeprocessing. There is considerable attention to the many contributing processing factors in the manufacture oflaminate and printed circuit boards. However, more focus on CAF formation mechanisms, might lead to“designing” a material that is robust against hostile processing and moisture.

GCE has cooperatively worked with the University of Maryland, CALCE group and DFR SolutionsIncorporated to apply unique CAF testing and analysis that assist in the goal to achieving a material designedfor CAF that is more easily testable and leads to lower cost solution. Namely, this work has suggested thatmaterial and printed circuit board ‘pre-screening’ is possible to predict anti-CAF success or failure, byfocusing on product measurements that directly correlate with properties consistent with the mechanisms ofCAF.

A key point of CAF activity to date focuses on the generation of corrosion along a pre-existing pathway.Specifically, the pre-existing pathways related to mechanical separation from drilling, excessive desmearingand wicking and micro separation due to poor thermal shock resistance have been well discussed.Furthermore, pre-existing conditions from laminate suppliers related to effective encapsulation of all glassstrands with resin have also lead to significant improvements in the anti-CAF results.

However, through the use of SQUID spectroscopy (Superconducting QUantum Interference Devices),continuous resistance measurement and utilization of very dense CAF coupons, pathways can be generatedduring CAF testing itself. This realization and subsequent mechanistic approach clearly suggests thatrobustness of material and process design needs to go beyond just process control factors, as increasingdensities (hole to hole spacing and hole to ground spacing) accelerate.

The presentation that follows will review the mechanical, thermo-mechanical, and electrochemicalmechanisms for CAF formation and failure and discuss the measurements that exist today and suggest newones for the future. In addition, we will discuss the idea of failure mechanism elimination and the scope ofsuch continued work in the coming year.


Poster 12Characteristics of Copper Foils for High Speed Systems

Abbas Moosavi- Oak-Mitsui Inc.Takuya Yamamoto- Oak-Mitsui Technologies Inc.

Many factors effect the propagation of signals through printed circuit boards. Until recently, the majorconcerns were the dielectric constant and loss tangent of the dielectric material as well as the bulkconductivity of the copper trace. As the frequencies get higher, the phenomenon know as “skin effect”becomes a factor, as most of the signal now “travels” along the outside of the conductor.

Copper foils used in making printed circuit boards usually have the surfaces modified to enhance peelstrength and to passivate the highly reactive surface of the copper. This mechanical and chemicalmodification of the surface can cause signal loss at high frequencies due to an increase in signal path (i.e.navigating the rougher surface) and increased resistivity (due to less conductive alloys on the surface).

This presentation will show the effects of copper profile and chemical modifications on the loss ofsignal attenuation at high frequencies. Additionally it will be shown that the standard 90o peel test may not bethe best indicator of copper bonding that affects PCB reliability. This can allow modification of the copperprofile to obtain better electrical performance without sacrificing reliability.

Design and Performance of Ultra-thin Substrates for use as EmbeddedCapacitors in High Speed Systems

John Andresakis- Oak-Mitsui Technologies Inc.Takuya Yamamoto- Oak-Mitsui Technologies Inc.

As CPUs increase in performance, the number of passive components on the surface of the boards areincreasing dramatically. To reduce the number of components, as well as improve the electrical performance(i.e. reduce inductance), designers are increasingly embedding capacitive layers in the PCB.

The majority of the products in use today utilize reinforced epoxy laminates. These products arerelatively easy to handle, provide good electrical performance, but a need exists for even better performancethan a fiberglass reinforced product can produce.

A need exists for an ultra-thin (less than 25 micron) material that not only provides improvedelectrical performance, but can be readily manufactured using standard PCB processing.

We will discuss the design criteria we used for developing our family of products, as well as theresults. The design of the conductor (copper foil) has been determined to be critical and is examined as wellas the dielectric. The products have been through both internal and external testing and are compared toexisting and developing capacitor materials. We will describe the electrical as well as the processingcharacteristics in detail, and how these types of products can greatly improve performance of high-speedsystems.


Poster 13Polar PCB Stack Up and Impedance Design Package

Ken TaylorPolar Instruments Incorp.

i. Polar Instruments design software for impedance, Inductance, Resistance, Capacitance, Conductance, Skindepth, Resistive attenuation, Conductive attenuation, Total attenuation (Np/m), Total attenuation (dB/m),Impedance real, Impedance imaginary, Surface resistance and modal velocity. I plan to have some pictureson the poster as well as the headings. I plan to keep it graphic. I will also have the software running on alaptop on the table.ii. PCB stackup design software. This is an economical, easy to use but sophisticated stackup builder softwarethat was conceived with engineers and OEM board designers in mind. It can also couple to the impedancesolving software to include impedance track information in the impedance layers.


Poster 14

Allegro Design Workbench

Craig LewisCadence

Historically, product data management (PDM) has been focused in the mechanical domain. But board-levellibrary and design data management introduce challenges not present in the mechanical world. This sessionwill describe methods for integrating the board-level design flow with a data management system, how thisintegration enables the engineering team to collaborate and how this leads to more effective design andmanufacturing outsourcing. Discussion will also focus on additional benefits of electronic designmanagement, such as revision control and design reuse. As board-level design continually becomes morecomplex and the size of engineering teams increase, there is growing need for effective management ofboard-level design and component data. If utilized correctly, board-level design tools and processes can beintegrated with PDM/PLM offerings for more effective library management, work-in-progress design datamanagement (for concurrent design) and release data management at the enterprise level. This enables thedesign team to collaborate more effectively, reuse design data and manage their processes across workgroups,both inside and outside the firewall.


Day 2

04:00Closure

02:15-04:00Daniel de Araujo, IBM- xSeries Roger Weekly, IBM- pSeries/HVEd Seminaro, IBM, pSeries/HV Mark Bubel, IBM- ProcurementPS Hou, IBM- ProcurementRoger Krabbenhoft, IBM- Development

Panel discussionThe panel of IBM development and procurementengineers will share general cost challenges by brandand give direction on what vendor feedback is essentialfor IBM to make design decisions which will be mostcost-efficient.

02:00-02:15Erica JasperCost Drivers

01:30-02:00Chet Palesko, ConsultantDesign and Cost Impact of EmbeddedPassives

Erica JasperChairperson & Moderator12:30-01:30Lunch

10:45-12:30Wayne Rothschild, IBM-ISC Procurement Eng.Mitch Ferrill, IBM-ISC Procurement Eng.Doug Trobough, Merix Dave Backen, TTMJim Wilson, EIBill Varnell, Polyclad Sean Mirshafiei, Isola Bob Carter, MEW/MEM Steve Feltham, Sanmina-Sci Bob Hearn, Dow Gail Tennant, Celestica

Panel discussionA panel of IBM engineers and PCB material /fabrication suppliers will discuss the potential relativeimpacts to long term reliability, meaningful assessmentmethodologies, and risk mitigation techniques.

10:30-10:45Roger KrabbenhoftMaterials, Processes and Reliability forLead-Free Applications Panel

Roger KrabbenhoftModerator10:15-10:30Break09:45-10:15Gail Tennant, CLS- TorontoAssembly requirements and impact on PCB09:15-09:45Wayne Rothchild, IBM- ISCLead Free Material Studies Update

08:45-09:15Bob Hearn, DowResin development targeting lead free andhigh frequency applications

08:15-08:45Jim Wilcox, IBM- ISCROHS UpdateJaveed AhmedChairperson

TimePresenterTopic


Integrated Supply Chain

IBM PCB Symposium April 20-21, 2005 © 2003 IBM Corporation

RoHS PCB Assembly Update

Dr. James R. WilcoxIBM Corporation


© 2003 IBM Corporation2 IBM PCB Symposium April 20-21, 2005

RoHS Impact to PCB Industry Practices

RoHS = Restriction of use of certain Hazardous Substances– Six substances banned from electrical and electronic equipment

(EEE) sold in the EU as of July 2006

Certain brominated fire retardants banned– PBB (polyBrominated Biphenyl)

– PBDE (polyBrominated Diphenyl Ether)

– Already disallowed by many major OEMs, including IBM.

Pb banned for many EEE applications– Primarily SnPb solder (surface finish or component attach solder)

– Some exemptions • solder for server, storage, and telecom applications• high melting temperatures (>85%Pb)• die interconnect solder joints, TCM c-ring, press-fit pins, etc.



Elimination of SnPb Eutectic Solder

SnPb solder exemption for Server card assembly – Necessity for exemption re-evaluated by EU

on four year intervals starting in 2008

Common Pb-free solders are near eutectic SnAgCu (SAC) alloys: SAC305, SAC387, SAC405– Melting temperature ~35°C above that of

eutectic SnPb.

– Manufacturing use requires elevated temperature robustness for all components and PCB laminate structure.

NEMI SMT alloy

EIAJ SMT alloy

ternary ternary eutecticeutectic

Ag3Sn

Cu6Sn5



Sn-Pb 195°CSnAgCu SolderingReduced Wetting Performance

high surface tension inhibits spreading

less available superheat

Reflow Temperature Constraintsminimum of 230°C for acceptable wetting

~20°C superheat desirablemaximum of 260°C (PCB temperature) driven by:

component and PCB survivability thermal stresses on assembly

Reflow Process Window of ~20°C solder joint temperatures: 230 to 250°C

SnAgCu 230°C



Pb-free Solder Reflow PCB Peak Temperatures

SnAgCu Pb-free assembly– 12 layer card, 1.2mm thick

Profiling constraints– component body <250°C– BGA balls >230°C

Two Assembly Vendors– different peak card temps– .

SMT Attach Profile – rework not included

Front Side

Back Side234 244

241

243

245

237

247

244 Y.Yoshikawa, K.Takei (2004)

(°C)



Pb-free Capable PCB Design Considerations*

Where functional design flexibility allows….

Distribute large components evenly across board– clusters of large mass components exaggerate reflow temperature

disparities among components

Avoid placing smaller components in isolated areas– overtemp risk during reflow

Position large components away from edge of board– edge regions tend to have lower peak reflow temperatures

* From HDPug General Purpose Lead Free user guide



Pb-free PCB Assembly Manufacturing Exposures

Surface Mount Soldering– 2 passes; back side/front side (245-260°C)– approximately uniform board temperature; TAL217

Wave Solder for PIN Components– direct backside exposure to molten solder (~270°C)

Solder Fountain Attach/Rework– local backside heating; direct solder contact

SMT Component Rework– backside preheat (~180°C)– front side direct impingement heating (~260°C)

PCB Qualification Recommendation: 5X reflow verification at 260°C– SMT backside + SMT frontside + Wave solder + 2X rework allowed.



Laminate Damage with 260°C ExposureExtreme damage mechanisms externally visible– warpage, delamination, blistering

Internal damage mechanisms less apparent– delamination, voids, resin detachment from PTH– fracturing, cloth coupler integrity– copper integrity (cracks, IP sep, pad lifting)

Damage more severe for increasing board complexity Damage may be cumulative with successive exposures

Resin recession from PTH Laminate voids; 5X reflow

UIC UIC

PTH cracking CAF formation

UIC

IBM IBM



Mixed Assembly…. Halfway Measures?

Mixed Assembly: SnPb and Pb-free assembly hybrids– Pb-free solder paste + SnPb bearing components (Forward Compatible)

• uncommon with SnAgCu paste because of component temperature limits– SnPb solder paste + Pb-free components (Backward Compatible)

• leadframe and leadless components – considered low risk• SnAgCu BGA alloys – caution required (“mixed BGA assembly”)

Mixed BGA Assembly– Process selection often driven by supplier conversion of BGA components

to SAC while remainder of BoM not ready for Pb-free assembly.

– Requires metallurgical homogenization of mixed solder joint.

– Assembly temperatures elevated above conventional SnPb temperatures but less than SnAgCu process temperatures.



Mixed Solder BGA Joints (SAC ball with SnPb paste)Reflow below SAC melt

(non-homogenous)Reflow above SAC melt

(homogenous)

Universal Instruments Consortium



Mixed BGA Solder Assembly Mixed BGA Assembly Mfg immature – most EMS suppliers hesitant to embrace

Range of potential PCB peak temperatures not yet established.Must define reflow profile using metallographic confirmation.

Manufacturing Process VariabilityCard level solder joint composition

No standard Pb-free BGA alloy (SnAg, SAC 305, 387, 405, etc.)SnPb solder paste volume determines final joint composition

Reflow profile parametersTpeak and dwell (> Tliquidus) determines extent of solder homogenizationPeak temperature determined by largest mass component

BGA Component rework temperatures melt temperature of homogenized solder joint different than initial attach.

Process Temperatures above SnPb Process an Anticipated Reduced PCB reliability impacts (depends on card complexity)Temperature tolerance of other BoM components (beyond J-STD-020B)

Recommending 245°C peak PCB temperature for now.



Mixed BGA Solder Assembly Example

21” x 23” x 0.126” thick server board

SnPb SMT assembly: Profile for 200-220°C SnPb joint temperature

Peak temperature driven by 52.5mm CCGA solder joint Tmin (203°C).

20 mm PBGA with SAC solder balls

PBGA body temperature 235°C

solder joint temperature ~233°C; TAL217 ~80s homogenization

Board Temperatures

top side Tpeak: 228, 231, 222, 233, 231 °C, bot side Tpeak: 233, 236, 229, 231, 230 °C,

W.M. Ma (IBM)



PCB Plated Copper ConsiderationsPTH Robustness– higher CTE induced stress during reflow

thermal excursion• IP separation, PTH cracking

– Pb-free press fit pin? (no SnPb lubricant)

Solder Intermetallic Voiding– extreme voiding possible in Cu3Sn

intermetallic within SnAgCu solder joint during thermal age

– widely varying response observed– origin of variability as yet unknown; copper

structural/impurity effects suspected– empirically confirm non-voiding copper

source or else PCB may be prone to embrittled solder joints

150°C 1000 hrs

L. Patry (IBM)



RoHS Capable PCB: Qualification ConsiderationsUse expected product PCB attributes– card thickness/ layer count– via diameter / pitch– max. copper plane thicknessLead Free assembly: 5X reflow at 260°C– reduced temperature requirements possible for simple, low complexity,

card applications, e.g., DIMM cards– consider total reflow temperature tolerances ±7°C (HDPug GPLF Guide)Mixed BGA assembly: 5X reflow at 245°CRevisit all possible PCB damage mechanisms – need full complement of risk sites in qualification vehicles– No qualification ‘bridge’ from conventional assembly practicesVerify performance through all required assembly operations – SMT, Wave, rework, press-fit, etc.



PCB Unknowns in Pb-free Environment

Internal PCB damage accumulation rate during multiple SAC reflowcycles– Subsequent board failure rates after 1X, 2X, 3X, etc., reflows

• various damage mechanisms– Damage rate dependence on board thickness/complexity

– Role of oxygen? air vs. N2 reflow environment

Moisture Sensitivity in Assembly– Is reflow damage sensitive to board moisture content?

– Historically, PCB moisture not controlled in assembly mfg environment

SAC solder joint interfacial integrity dependence on copper plating– Intermetallic voiding mitigation strategy



PCB Industry Needs to Support RoHS?

PCB Assembly Tolerance Rating System?– Peak temperature capability ratings (225C, 245C, 260C?)

• Tg is not indicator of temperature robustness– Moisture sensitivity level rating to support LF manufacturing?

EMS Recommendations for Process Temperature Requirements– Guidelines for maximum PCB temperature exposures

– Dictated by component BoM and board construction

Card Level Solder Joint Interfacial Integrity Test– Plated copper certification procedure?

– Board flex, BGA ball pull?

– Thermal aging standards

4/21/2005 RLH UNRESTRICTED - May be shared with anyone Page 1

Resin Developments Targeting Lead Free and Low Dk Requirements

Bob HearnThe Dow Chemical Company

April 21, 2005

IBM PCB Technology Symposium


Topics

• Legislation summary• Lead Free Solder Choices• Testing and Specifications• Laminate Requirements• Resin Systems Development Direction• Dow Products for Lead Free Application

– Existing Commercial– New Development



LegislationYear

• US– EPA has lowered reporting threshold for lead and 2001

lead compounds under the Toxic Release Inventory (TRI)– (TRI) reporting threshold for lead compounds has been 2002

drastically cut from 25,000 lb to 100 lb. beginning July 1, • Japan

– Home Electronics Recycle Law – “Japanese consumer electronics 2003 will be substantially lead-free by 2003”

• Europe – Waste Electrical and Electronic Equipment (WEEE) and RoHS 2006

(Restriction of Hazardous Substances) states that from 1 July 2006,new electrical and electronic equipment put on the market does not contain lead, mercury, cadmium, hexavalent chromium, PBB or PBDE.(NOTE: TBBA is the common source of bromine in laminatesand is not currently on the WEEE ban list)



Lead Free Solders

• Replacement lead free solders have higher reflow temperaturesPrice Factor

1 1.7 3 3.9 8.6 11 260 Temp Temp Absolute Paste Bar

In Pb Zn Cu Sb Bi Sn Ag Preferred Liquidus Reflow US$/Kg US$/Kg US$/Kg 37 63 Standard 183 Max

220 3.70 1 1

36 62 2 7.50 52 48 104.00 97 3 195.00 0.8 0.5 96.7 2 213 233-

243 9.20 1.05 2.06

5.1 91 5.10 5 95 5.40 10 65 25 52.40 0.7 95.5 3.8 Motorola/

Nokia/ Ericsson/ Philips

217-218 238-248

12.60 1.06 2.21

0.5 95.4 4 218 238-248

13.00

1 95 4 * 218 238-248

14.60

96.5 3.5 Motorola/ Ford

221 240-250

12.10 1.07 2.29

0.7 99.3 Nortel 227 245-255

5.50

58 42 8.20 20 72.2 2.8 48.70

• Preliminary consolidations seem to be around the SnAgCu (SAC ) alloys



Solder TemperaturesSolder Temperatures of "SAC" alloys

220

230240

250

260

270280

290

300

Temp. Price

Property

[°C]

1

1.21.4

1.6

1.8

22.2

2.4

2.6

Pric

e fa

ctor

[SnP

b =1

]

SnPblevel

ProcessBase MaterialPerformance

Base material performance must match process need’s



Thermal Resistance Tests

• Two common test used today will be designated on the proposed lead free laminate specification sheet (IPC4101B/99) and used to determine fitness for – Time to delamination at specific temperatures (T260, T288,

T300)• IPC-TM-650 2.4.24.1 - TMA• Internal pressure from decomposition products is sufficient to

cause the sample to delaminate and change dimensions (TMA)– Thermal decomposition - Td (or Thermal stability)

• IPC-TM-650 2.3.40 - TGA (@ 10 deg C/min – under revision)• Temperature at which a designated weight loss (e.g. 5, 3,1 wt %)

of a sample is lost to volatile decomposition products (TGA)



Time to Delamination

Time to delamination TXXX-Test

0.1

1

10

100

1000

240 260 280 300 320 340

Temperature [°C]

Tim

e [m

in]

StdTgHigh Tgv. High TgHigh Tg/TdMidTg/highTdStd Tg/high Tdlow DkBr-free

An increase of 20 - 25 °C in solder temperature



– Time to Delamination (TMA)• Std high Tg FR4 laminates has T-260 value in the range of 5 - 10

min. and works well with current lead based solder• Lead Free Solder ~ 20 deg C higher than leaded solder• Follows that a 20 degree higher delamination temperature would

be required– T-280 ~ 5 - 10 min or a T-288 ~ 3 – 6 min

– Thermal Decomposition (TGA @ 10 deg C/min ramp)• Std high Tg FR4 laminates have Td ~ 300 deg C• Sensible limit for lead free solder would be ~ 320 deg C

Establishing Lead Free RequirementsIBM PCB Technology Symposium


Development of More Thermally Resistant Resins for Lead Free Solder Applications



Dominant Flame Retardant

• The source of decomposition of cured epoxy resin is the presence of bromine from the flame retardant (TBBA) and/or nitrogen from the hardener (dicy)

Br

BrBr

Br

OHOH

Cas No: 79-94-7Name:

Tetrabromobisphenol AAbreviations TBBA, TBBPAFormula Weight: 543.7Bromine-Content: 58.8 %Melting Range, °C: 179 – 182Specific Gravity: g/ml: 2.2TGA weight loss: 5% at 244°C

10% at 261°C50% at 304°C



Bromine vs Bromine Free Systems

• Non-Brominated FR4 systems are certainly capable of reaching T300 > 30 min but– High cost– Performance issues (brittleness, humidity resistance, etc.)

• Dow is working on brominated systems that release bromine at the right time– Release with fire to maintain V0 but hold on to the backbone in the

case of high temperature exposure– Current Methods

• Displaces the entrenched dicy hardener with various phenolic hardeners• Phenolic novolacs can displace up to 30 % of the brominated epoxy in the final

cured system – Not known if the lower bromine content or the elimination of the nitrogen

containing dicy is improving the thermal stability



Thermal Resistance Measurements

TgThermal

ResistanceTests

ThermalCycling and

otherTests

Temp at whichkey propertieschange e.g. modulus,CTE, electrical

Decomposition/Degradation temp/time

Combination of properties e.g.adhesion, decomp.,“aging”.

In-Use In-Process In-ProcessIn-Use

Past Future?Present

New resin systems must take into account not only standard thermal performance properties (Tg, Td, T-288) but also emerging test related to continued performance improvements and end use needs



Emerging Testing Requirement

• Some additional tests are being proposed/required for lead free solder applications– Cycle tests

• Interconnect stress test (IST)• Reflow test• Cisco solder dip test• Accelerated automotive cycling test (-50 deg C +155 deg C/500 times) test, etc.

– CAF (conductive anodic filament) tests– Toughness testing

• Improved thermal resistance requires tighter cross linked systems which are inherently brittle

• Resins system can be modified for improved drillability / better processabilityw/o effecting other properties

• Tests – Drilling/halo, impact, fracture toughness test, etc.



Improved Laminate Toughness

(a) Standard Low Dk laminate (reference)- brittle laminate, delamination, poor drillability(b) Dow Low Dk with toughened hardener- tough laminate, no delamination, good drillability

delamination no delamination

Dow XZ92567/XZ92568 Thermally Resistant Low Dk Resin System



• High Thermally Resistant Resin Systems − LF 150 & LF 170 for Lead Free − HTR 170 A for higher thermal reliability and toughness− HTR 170 B for higher thermal reliability and improved dielectric

properties− XZ92567/XZ9268 for best dielectric properties while maintaining high

thermal reliability

Dow Developments EffortsIBM PCB Technology Symposium


LF 150

“Eas

e of

pro

cess

ing”

“Thermal Reliability”

HTR 170A

For Lead Free(Mid & High Tg)

Traditional Non-DICY

LF 170DER 530

DER 539

DER 592

DER 593Standard

FR-4Higher Thermal

Resistance

Lead Free Three Targeted Markets

HTR 170B

XZ92567/68

Improved DielectricsHigher Thermal

Resistance Improved Dk



Lead Free (LF 150 & LF 170 )System Characteristics• Newly developed two Package Resins (Epoxy & Hardener)• LF 150 and LF 170 are designed to meet stringent thermal resistance like lead free market• Standard FR-4 like process and characteristics• LF 150 and LF 170 maintain D.E.R. 539A80 and D.E.R. 592A80 proven performances

such as process window, adhesion and compatibility with PCB process. • The brittleness of regular phenol cure systems has been overcome by a back bone

modification. This is demonstrated by improved peel strength data.Laminate Properties LF 150 LF 170

Tg (°C) 154 170 Decomposition Temp (°C) 10 °C / min onset

> 330 >330

T- 288(min) 10 6 PCT 2 hr + solder 288°C20 sec X 5 times

Pass Pass

Copper Peel Strength (lb/in)

8-9 8-9



Higher Thermal (HTR 170)

Laminate Properties HTR 170 (A) HTR 170 (B) Tg (°C) > 170 > 170 Decomposition Temp (°C) 10 °C / min onset

345 365

T- 288(min) 14.5 39 PCT 2 hr + solder 288°C20 sec X 5 times

Pass Pass

Copper Peel Strength (lb/in)

10-11 5-6

System Characteristics• Two package developmental resins (Epoxy & Hardener). Target sampling timing 2Q ‘05• HTR 170 is designed to meet most demanding thermal resistances. There are two

developmental systems.− HTR 170 (A) has one of the best thermal resistance while maintaining good copper

peel and toughness.− HTR 170 (B) has the highest thermal resistance with improved Dk/Df performances



Best Dielectric with High ThermalSystem Characteristics• XZ92567/XZ92568 – Commercially available

– XZ 92567.01 and XZ 92568.01 is a two package system especially formulated to be used together

– System is enhanced for reduced brittleness/improved drillability– Designed to produce Electrical Laminates with reduced dielectric constants (Dk/Df)

and improved thermal properties (Tg, thermal resistance)Laminate Property Typical Values

Tg (DSC), °C 180 - 185 Dk / Df @1MHz 3.9 / 0.007 Dk / Df @1GHz 3.8 / 0.009 T288 (TMA), min > 50 Td (TGA, 5% wt loss), °C 365 PCT 2 hr + solder 288°C, 20 sec X 5 times 100% pass Copper peel strength, lb/in 5-6



Proposed Lead Free Spec Comparison

Dow Material Designation LF 150 LF 170 HTR 170A HTR 170B

XZ92567/ XZ92568

Material Type

Mid Tg/Thermal Resistant

High Tg/Thermal Resistant

High Tg/Higher Thermal Resistant

High Tg/High Thermal Resistant/ Improved Dielectrics

High Tg/High Thermal Resistant/ Low Dk/DF

Proposed * Lead Free Specification > 0.50 mm (> 0.0197 in) 40 % RC Units

Laminate RequirementGlass Transition Temp >150 >170 >170 >170 180-185 170 min ** deg CDecomposition Temp (Td) 5 wt % loss, 10 deg C/min >330 >330 345 365 365 330 deg CT-288 (10 deg C ramp) 10 6 14.5 39 >50 5 minZ Axis Expansion (< Tg) 50-70 50-60 50-60 50-60 50-60 75 max ppm/deg Cz Axis Expansion (>Tg) 250-260 250-260 250-260 250-260 250-260 300 max ppm/deg CPeel strength (std. foil) 8-9 8-9 10-11 6-7 5-6 4.57 lb/inMoisture Absorption 0.3 0.3 0.35 0.39 0.3 0.8 %Permittivity, @ 1MHz 4.5-4.8 4.5-4.8 4.5-4.8 4.2-4.4 3.8-3.9 5.4Loss Tangent @ 1 MHz 0.016 0.016 0.016 0.014 0.009 0.035Flammability V0 V0 V0 V0 V0 V1

* Proposed Lead Free Solder IPC Spec 4101B/99 (Subject to change)** Spec may split into two - Mid Tg and High Tg

• These products all meet the new proposed IPC Lead Free Specification(IPC4101B/99)



Lead Free Solder Specification

• Even though products are available to meet the proposed specification, we must be careful to not set the specifications too high.

• As thermal requirements of the resin systems increase, brittleness issues increase and dielectric properties are compromised. These issues can be overcome but usually at increased costs and the sacrifice of other properties.

• The specification limits should be set based on performance data from real lead free solder applications not from characteristics of existing products designated for this application

• Laminates may not be the limiting factor. Some components such as electrolytic capacitors, and other discrete parts may also require increased thermal resistance.



Summary

• All bromine free systems meet Lead Free requirements but cost and processing issues have restricted their use

• Brominated resin systems will work well with lead free solder

• There are existing commercial products and new improved development products available

• Systems with good thermal resistance, electrical properties, and toughness can be provided


Qualification of PCB Fabricators / Standard Loss Tangent Laminates for Lead-free Soldering Survivability

Wayne RothschildIBM / Dept HT9Rochester, MN

WJR 1 of 21 April 21, 2005


Agenda

Peak Soldering Temperature Requirements

Affected PCB Material Constituents

Potential Effects Upon Laminate

Qualification Process

Status

Lessons

WJR 2 of 21 April 21, 2005


PCBs Must Withstand Higher Peak Temperature

Thermal Rating Requirement Must be Stated on Assembly and PCB Drawings

Peak PCB Temperature Application(s)

245o C * Mixed-solder (SnPb Attach of SAC-balled BGAs)* Low Thermal Mass Assemblies (eg, pDIMMs, I/O)

260o C * Higher Thermal Mass Assemblies

280o C + * Plan-of-Record Rework for Special Connectors

WJR 3 of 21 April 21, 2005


PCB Materials Directly Affected by Higher Temperatures

Organic Materials

LaminateFocus of This Presentation

Solder Mask

Inks

OSP

WJR 4 of 21 April 21, 2005


Effects of Higher Temperatures on Laminate Has Major Influence on PCB Reliability

Potential Irreversible Laminate Structural Changes

Delamination, Cracking (Shorts)Glass-to-Resin Separation

Warpage (Solder Joint Opens)

Potential Indirect Effects Upon Integrity of Circuitry

Expansion of Laminate versus Expansion of Copper (Opens)Via Cracks, Internal Land-to-PTH Barrel Separation (Opens)

Thermal Survivability of Most of the "High-Temp" Laminates in Common Use Today ....

On / Near Fall-off of Survivability Curve at 245o CClear Problems at 260o C

WJR 5 of 21 April 21, 2005


Laminate Selection is Critical For a Given PCB Design and Application

ReliabilityThermal EfffectsRH EffectsMechanical Effects

Electrical PropertiesCostAvailability

PCB Fabrication Process is Also Important

Introduction of New Laminate is Not a Drop-inLamination, Drilling, Desmear, Plating, etc.

WJR 6 of 21 April 21, 2005


All PCB Fabricators that Are Strategic to IBM System Group Must be Requalified

For Appropriate Peak Temperature

Regardless of Whether Change Laminate and/or Fabrication Process

WJR 7 of 21 April 21, 2005


Qualification Approach

Mutually Agreed Upon PCB Technology Key Design Attributes

Defines Maximum Level of PCB Complexity if Successful Electrical Properties

Mutually Agreed Upon Laminate Electrical Measurements if New to Dept HT9

Supporting Internal Reliability Testing Data Results from Supplier

Submit Test Vehicles to Dept HT9 for TestingKey Risk SitesWired to Allow Precise Monitoring for Onset of Opens or Shorts

Regression Testing if NecessaryAs New Hazards Identified During TestingAs New Risk Sites Become Part of Future Product Designs

WJR 8 of 21 April 21, 2005


Test Sample "Suite"

PN Dimensions Description21P8336 11" x 9" Via Reliability (8-, 10-mil vias @ 0.8-, 1-mm pitch)

Interconnect Reliability in ATC (40-mil PTHs)Via-to-Plane IR/Hi-pot (BGA, VHDM-accommodating PTHs)Material Characterization

39J5005 5" x 4" Via-to-Via IR (CAF) (Various Cu-Cu Spacings)

39J0073 1.25" x 1.25" Interconnect Reliability (Solder Float Test)

GP40001(PWB Corp)

5" x 0.6" IST with Modification for Auxiliary Measurements of Capacitance Changes

21P8338 2" x 1" Material Characterization

WJR 9 of 21 April 21, 2005


PN 21P8336

WJR 10 of 21 April 21, 2005


PN 39J5005

WJR 11 of 21 April 21, 2005


PN 39J0073

PN 21P8338

WJR 12 of 21 April 21, 2005


Test Plan

As ReceivedInspect SurfacesLayer-to-layer RegistrationSolder Float TestIST

After Preconditioning (5 x 260o C at Contract Manufacturer)Inspect Surfaces (again)ATC, IR

Includes VHDM-accommodating PTHsIST

Including Capacitance Before and After (PWB Corp)Hi-potCross-section

Thermal Analysis of Laminate Before / After Preconditioning

WJR 13 of 21 April 21, 2005

Limited Number of Laminate / PCB Fabricator Candidates Tested / In Test Thus Far


Peak Temp Fabricator Lam 1 Lam 2 Lam 3 Lam 4/5245 C A 50 mils

(pDIMM)

B 50 mils (pDIMM)

260 C A 100 mils (different TV)160 mils

C 160 milsD 130 milsE 130 mils 130 mils

Scout with different TV

F 130 mils Scout with different TV

WJR 14 of 21 April 21, 2005

Concerns Thus Far (260o C)

Dearth of Laminates with Potential of Meeting Electrical and Mechanical RequirementsOpportunities

Process Simulation-induced Delamination / CrackingNot Observed After Sn/Pb Soldering SimulationNot Always Externally VisibleExtent Dependent on Material, Fabrication Process, PCB Features / AttributesNeed to Also Run Real PNs to Explore Responses to Other Design Attributes

Process Simulation-induced IP Separation


WJR 15 of 21 April 21, 2005

Blistering


WJR 16 of 21 April 21, 2005

More Blistering Observed in Area with 37-mil Grid Than in Area with 39-mil Grid


WJR 17 of 21 April 21, 2005

Laminate Cracking / Fracturing


WJR 18 of 21 April 21, 2005

Laminate Cracking / Fracturing


WJR 19 of 21 April 21, 2005

General Comments

Cannot Select Laminates Solely on Basis of Material Properties

Effects of Laminate / Design / Fabrication Process on Structural Integrity Accentuated by Higher Temperatures

Much Work In Front of Us, Little Time, Limited Resources

Need Tight Interlock Along Members of Supply Chain Laminate Suppliers, PCB Fabricators, CM, OEM

Weigh Proprietary Nature vs. Progress


WJR 20 of 21 April 21, 2005


WJR 21 of 21 April 21, 2005

The Impact of Lead-Free Assembly on PWBS

Gail TennantTeam leader for Regional Supplier Engineering Americas

•Introduction to Lead-free

•Inspection Impacts

•Reliability Impacts

•Supply Chain Impacts

•Conclusions

Agenda

Environmentally friendly electronics

15/04/2005 3

Conversion to more environmentally friendly electronic assemblies is being

driven from two fronts:

Legislative Requirements

• Specifically the E.U. (European Union) with its WEEE and RoHS directives

• Many other jurisdictions planning to put in place similar legislation modeled

after EU directives (ie. China)

Competitive Pressures

• Primarily from Japanese OEMs

The Driving Forces

Environmentally friendly electronics

EU legislative directives

EuP Directive(Energy Using Products Directive)

Design ComplianceEnact in 2007

EuP Directive(Energy Using Products Directive)

Design ComplianceEnact in 2007

WEEE Directive(Waste Electrical and Electronic Equipment Directive)

Electronic waste recycling & disposalWaste collection system established Aug., 2005

Pay for system & take back waste Jan.,2006

WEEE Directive(Waste Electrical and Electronic Equipment Directive)

Electronic waste recycling & disposalWaste collection system established Aug., 2005

Pay for system & take back waste Jan.,2006

2003 2004 2005 2006 2007 2008

Non-EU jurisdictions are proposing

similar

Legislation for product

shipped into the EU.

After deadline, non-compliant product

will be barred.

Non-EU jurisdictions are proposing

similar directives: Japan, China, etc.

RoHS Directive(Restriction of Hazardous Substances Directive)

six materials BannedLead & flame retardants out by July, 2006

RoHS Directive(Restriction of Hazardous Substances Directive)

six materials BannedLead & flame retardants out by July, 2006

15/04/2005 5

• Lead (Pb)

– Used in virtually all solders, electronic components and many PWBs.

• Cadmium (Cd)

– Used in batteries (NiCd), plastic stabilizers, platings

• Mercury (Hg)

– Used in some electrical components, batteries, pigments

• Chromium VI (Cr6+)

– Used in dyes, pigments, plating solutions, alloys

• PBB & PBDE (Polybrominated-Biphenyls, Polybrominated Diphenylethers)– Used as flame retardants in plastics, some PWBs

(not FR4), insulation

RoHS Banned Materials Details

EU legislative directives

Alternative “Pb-free” Solder Solutions

• No direct drop in replacement exists for Sn/Pb solders in use today

• All recommended alternatives require higher soldering temperatures:

• current front runner alloy is Sn/Ag/Cu (Tin/Silver/Copper)

• melting point 30OC higher than existing solder (approx. 2170C)

• assembly temperatures required will exceed temperature limits of current

component and board materials

• development in new component materials and assembly methods is required

Assembly Process Implications

Eutectic solder(Sn-Pb)

Lead-Free solderSn-Ag-Cu

240

200

180

220

Tem

pera

ture

°C 23

* - ∆T is dependant on min. temp for good wettability. Conflicting data exists on actual number.

Component Danger Area

Legend: Profile Max Temp Solder Melting Point Min. Temp for Good Wettability

∆T = 8-10

∆T = 1557*

Sn63Pb37 Melt 183°C Sn10Pb90 ball Melt 275°C-302°CReflow temp 205°C

PCB

Sn10Pb90

CBGA

Sn95.5Ag3.8Cu0.7 Melt 217°C SAC ball Melt 217°CReflow temp 232-max.250°C

“Pb-free” Process Development

SAC

Rework Process Implications

• J-STD-020C temperature range is 245 to 260C

• Temperature range from 230 to 255 C for joints and body temperatures.

• Up to eight minute Cycle time for most packages

• TAL from 60 to 90C

Inspection Impacts

Higher processing temperatures place greater stress on the PWB

These stresses result in • Externally visible

defects– Delamination – Solder mask coloration

change

Inspection Impacts

• Internal Defects– Delamination visible

externally– Delamination which

is visible only by x-section

Inspection Impacts

Joint AestheticsLead-free joints have a grainy and rough appearance

SnPb solder with PbSn high melt balls LF solder with lead-Free balls

Inspection Impacts

Solder Spread

Sn/Pb Pb-free

Inspection Impacts

Solder Flow

Sn/Pb Pb-free

Inspection Impacts

Visual Inspection Development• Educate inspectors how to distinguish between

external defects that are rejectable and non rejectable.

• Develop inspection methods for internal defects.• Education on new joint appearances• Methods for detecting non-wets and normal lead-free

flow.• Define new hole fill requirements

Reliability Impacts

Metallurgy (alloy)

*Component finish, paste, board finish...

Substrate\Laminate

Moisture sensitivity level

Solder joint reliability model

CTE mismatch between laminate material and copper in the vias.– Marginal defects relative to tin/lead

process may become more significant relative to SAC

process.– Greater overall stress upon copper.– Manifested as opens.

» During assembly process (blatant defects)

» During customer operation (latent defects)

Reliability Impacts

15/04/2005 18

Temperature effects on glass-to-resin adhesion• Greater exposure for CAF

formation due to increased likelihood of formation of growth-accommodating pathways between conductors.

Reliability Impacts

Pictures from IPC-9691

Reliability Impacts

0

1

2

3

4

5

6

7

PLCC PQFP QFP TBGA TQFP BGA SCSP uBGA

Pkg Type

MSL

Rat

ing

220-225C235-240C250-255C

Fail

ReflowTemp.

MSL Rating of Existing Componentsvs Peak Reflow Temperature

Component MSL rating significantly impacted as a function of peak temperature

How does the increase in processing temperature effect PWBS?

Will PWBs require baking?Will PWBs require different packaging?

15/04/2005 20

Increase in Wrapage• Designing boards to

minimize wrapage• Assembling large

components

Micro-hardening• Impacts on handling• Joint strength

Reliability Impacts

15/04/2005 21

Reliability Impacts• Testing of barrels• Testing for CAF• Reliability joints when warpage is large• New handling requirements

Reliability Impacts

15/04/2005 22

Designing Products• Selection of a Supplier• Selection of a laminate• Qualification proceduresSourcing Lead-free products• Ensuring Supply

– Multiple laminate types– Multiple qualified suppliers

• Minimizing the cost impactData management• Storage of C of C and material declarations

Supply Chain Impacts

15/04/2005 23

ConclusionLead-free impacts many areas of the assembly

process. • Inspection• Reliability• Supply Chain

TIME FOR ACTION IS NOW!

Conclusion

IBM System and Technology Group


Materials, Processes, and Reliability for Pb-Free Applications

Panel IntroductionR. Krabbenhoft



Materials, Processes, and Reliability for Pb-free Applications

–Our Panel• Wayne Rothschild, IBM-ISC Procurement Eng.• Mitch Ferrill, IBM-ISC Procurement Eng.• Morgan Viggers, Merix• Dave Backen, TTM• Jim Wilson, EI• Steve Feltham, Sanmina-Sci• Bill Varnell, Polyclad• Sean Mirshafiei, Isola• Bob Carter, MEW/MEM• Bob Hearn, Dow• Gail Tennant, Celestica




Abstract: ……discuss the potential relative impacts to long term reliability, meaningful assessment methodologies, and risk mitigation techniques.

A lot of material already presented.

Generate open discussion between those affected at various stages of the material and fabrication process.



Materials, Processes, and Reliability for Pb-free ApplicationsTopics to Consider– Design related issues

• PTH Pitch/Density• Thickness / Aspect Ratio• Heavier Cu (2oz +)• Resin Rich Areas

– Specifications / Qualifications• Qualification Complications Due to Design Sensitivities• Test Methodology Changes• IBM Requirements vs. Industry Requirements• Performance Requirements




–Resin Formulation / Filler Choice• Reliability / Performance / Cost• Filled vs. Unfilled

–Treated Material Impacts• CTE• Tg vs Td• CAF

– Moisture Absorption– Glass / Resin Interface




–Fabrication• New Lamination Process Requirements

– Delamination Concerns• Drill Parameter Optimization• Via Reliability

– Inherent Reduction?• Cu Adhesion

– Smoother Cu vs. Higher Stress Environment• Resin Flow / Voiding / Image Transfer




–Assembly Process Definition• IR Reflow vs. Vapor Phase• Component thermal mass• Rework• Long Term Reliability of Solder Joint

–Stages of Rollout of Pb-free Requirements• Eutectic Sn/Pb Mixed Assembly Pb-free/SAC• Timing Ability to intercept• Field Returns and ETN (Equivalent To New)

Chet Palesko – April 21, 2005Slide - 1

Embedded Passives Cost AnalysisIBM PCB Symposium

April 20 & 21, 2005

Chet A. PaleskoSavanSys Solutions LLC

Phone (512) – 402 – 9943Email : [email protected]

www.savansys.com


Agenda

Embedded Passives Cost Overview

Embedded Passives Technology Overview

Designs suitable for Embedding

Sample Embedded Trade-off Analysis

Summary


What is an Embedded Passive?

Discrete Passive Embedded Passive


Effect of Embedding on the Design Flow

The manufacturing value added shifts from assembly to fabrication• Fabrication costs increase• Assembly costs decrease

Effect of Embedded Passives on Cost:

Materials &Equipment

Fabrication CostBoard Size

Assembly &Component Cost

OPTIMAL PRODUCT

CostPrice

Materials & Equipment

ManufacturersBoard

Fabrication

OEMsCostPrice CostPrice

BoardAssembly


Why the Decision to Embed or not is so Difficult

Tradeoff spans design, board fabrication, and board assembly• Design cost is higher• Board costs may be higher or lower depending on the size difference• Assembly cost is lower

Costs vary greatly across the industry• Driven by large variations in pricing• For example, cost per discrete placement may range from ½ cent to 5 cents per

device

Cost data is confidential• Little sharing across the industry

Dynamic nature of costs involved• Costs for both embedded and discrete passives change frequently


Embedded Passives Cost Drivers – Substrates

Higher Substrate Fabrication Costs• Higher material costs per layer pair

Varies per layer pair per panel and per device• Additional processing steps per layer pair

Varies per layer pair per panel (occasionally with a small per device component)Capital equipment investment adds a volume dependency

• Laser trimming per resistorVaries per layer pair and per deviceCapital equipment investment adds a volume dependency

• More inner layer pairsVaries in discrete steps based on number of devices


Assembly Effects of Embedding

BOARD SERIALIZATION

SCREEN PRINTNO-CLEAN SOLDER

PASTE

SMT PLACEMENTCHIPSHOOTER

SMT PLACEMENTFINEPITCH

SMT PLACEMENTINSPECTION MANUAL

AUDIT PART MARKINGS

REFLOW

SMT INSPECTIONTARGETED INSPECTION

MANUAL

SMT INSPECTIONAUTOMATED OPTICAL

INSPECTION

SMT INSPECTIONAUTOMATED X-RAY

MECHANICAL, PRESSFIT

PLACE THROUGH HOLES

WAVE SOLDER

SMT/PTH INSPECTIONBOTTOMSIDE

AUTOMATED OPTICAL

ICT

POST TEST ASSEMBLYHEATSINKS ETC.

FUNCTIONAL TEST

FINAL INSPECTION

PACK AND SHIP

REWORK

REWORK

Return forbottom side

• Use glue on side 2

• Skip reflow on side 2 if doing wave later

Steps in blue are less expensive with fewerdiscrete passives


Embedded Passives Yield Management

Since rework with embedded passives is usually not possible, yield can be a huge cost driver.• Expressed as yield per embedded device and should be quite high.• Example :

If you embed 400 resistors on a board and the resistor yield is 99.9%, the board yield from embedding will only be 67%. This will then be multiplied by all the other yield hit contributors and could result in a total board yield of less than 50%.

Resistor yield management• Larger devices (for PTF) give better yield• Spreading them out means easier trimming• Same aspect ratio and orientation gives better results

Capacitor yield management• Smaller devices for capacitors give better yield


Thick Film Resistors

Polymer thick film resistors are the most common, but ceramic thick film is also an option. Paste is applied to panelwith a high precision screen printer.

Advantages• PTF is a mature process and used extensively in production.• Paste is only applied to resistor area, so the cost is good

Driven by total resistor area, not total board area• Almost any board fabricator already has the expertise and equipment to

build boards with PTF technology (without laser trimming).

Disadvantages• Without laser trimming, tolerance of +/- 20% is achievable• With laser trimming +/- 5% is achievable• Ceramic fabrication requires a significant capital investment by the board

fabricator.


Thick Film Capacitors

Ceramic thick film capacitors are the most common. Paste is applied to panel with a high precision screen printer.

Advantages• The capacitance per area is at least an order of magnitude higher than

any other embedded capacitor technology.Ceramic material (from Dupont) 1.5nF/mm2 . 3M material .0088nF/mm2

• Paste is only applied to capacitor area, so the cost is goodDriven by total capacitor area, not total board area

• Board fabricators do not need a license to build ceramic thick film boards

Disadvantages• Ceramic fabrication requires a significant capital investment


Thin Film Resistors

Resistor material is applied to entire panel and unwanted area is etched away

Advantages• Processing is easy for any good board fabricator• Very mature process

Disadvantages• Cost can be quite high unless resistor density is also quite high• Without laser trimming, tolerance of +/- 20% is achievable• With laser trimming +/- 5% is achievable


Thin Film Capacitors

Thin capacitor material is sandwiched between two conductive planes. Entire plane can be used for power distribution management, or plane can be patterned to form individual embedded capacitors.

Advantages• Processing is easy for any good board fabricator• Given the significantly lower inductance, a 1 for 1 replacement of a

discrete capacitor value on the surface is not necessary.

Disadvantages• For the board fabricator, a Sanmina license may be required. This adds

cost.• Capacitive density is quite low. It can be pushed a little higher with filled

dielectric material, but usually at the expense of voltage breakdown.


Other Promising Technologies

Laser printing resistors• More precise control as compared to screen printing

Physical Vapor Deposition of materials• Currently limited to glass substrates, but achievable capacitance per area

is quite high.


Designs Suitable for Embedded Passives

Designs with a significant percentage of passives compared to active components

• Good chance for a size reduction• Relative embeddable passives vs. actives is a critical factor

High performance designs• Electrical characteristics of embedded devices and the interconnect to get to them is strong

Size constrained designs• May be able to add more functionality in the same space

Designs which have excess routing capacity• Embedding passives without adding a layer pair reduces extra cost• Designs containing high pin count BGAs are candidates since the board layer count is driven by

the BGA escape routing, not total routing requirements

Large designs with only 1 or 2 up per panel are challenging for embedding. However, assembly costs for these big complex boards can also be high so some may be candidates

• Economics will be driven by yield per embedded device, but yield can be managed by effectively using the area.


Embedded Passives may enable a Change in Layout or Technology

Ability to fit a two sided board all on one side

Ability to combine two boards into one

For large boards, the ability to get more up per panel• Going from 1 board per panel to 2 boards per panel will cut the board

cost in half

Avoiding the need for 0201 devices, which are very hard to assemble

Performance requirements are so high that copper “runs out of gas”. The maximum operating frequency for an embedded design is higher than a discrete design.


Modeling the Tradeoffs with SavanSys

Analysis with SavanSys includes both design and manufacturing, enabling designers to optimize their products for cost, yield, and performance across both

domains.

Design Manufacturing Model(s)

Optimized Product


Assembly Cost Drivers


Fabrication Cost Drivers


Sample Embedded Tradeoff Analysis Summary*

Assumptions:• Baseline board/panel cost is $200, but not relevant for embedded vs. discrete

comparison• Average discrete cost in .5 cents• Annual volume is 5,000 boards• ~600 out of ~900 total resistors embedded• Generic assembly flow used – not calibrated to IBM’s actual costs

8.52

11.54

Component Cost (Partial)

80%

77%

First Pass Yield

Total CostAssembly, test, & rework cost

Board Cost

327.43101.22217.7600 Resistors Embedded

329.10117.56200Baseline

* Incremental fabrication PTF cost model courtesy of Aspocomp Group. Baseline panel cost is not modeled.


Future Trends

As the end product size shrinks, the cost of embedded passives goes down and the cost of using discrete passives goes up.• Smaller designs result in more embedded devices per panel• Smaller designs result in mechanical assembly challenges

Cost perPassivedevice

Passive devices per area

Discrete passives

Embedded passives


Summary

High level models are good to decide whether to consider embedding or not, but to know the real cost difference, you must do a design specific analysis on your design using your costs• High level models will often give the wrong answer• The economics vary drastically based on:

Your fabrication cost, not some industry averageYour assembly cost, not some industry averageYour component costsThe specific characteristics of the target design

It is not a matter of “if” embedded passives will cost less, it is matter of “when” they will cost less for you

ISC Procurement Engineering

E. Jasper Gant © 2005 IBM Corporation

PCB Cost Challenges at IBM

PCB SymposiumApril 21, 2005


© 2005 IBM CorporationE. Jasper Gant

General Cost Challenges: Trends

Component Selection >>> Smaller Via Diameter and Pitch

Layer Count Reduction >>> Complicated Signal Planes (multiple trace widths/Zo targets + voltage shapes)

Pb-free Processing >>> Robust Laminates

Attenuation Drivers >>> Small Via Connectors, Wider Traces, Back-Drilling, Low Df Material, Buried Vias, Subcomposites

High Aspect Ratios (Wider Traces >>> Thicker PCBs)Cost Targets Getting LowerVolumes Cannot Compete with Mobile



Cost Challenges with New Technology

Buried Passives seem $ Prohibitive

New Materials w/ Better Performance seem $Prohibitive

Pb-free Processing Requires more Robust Materials (even in LE), $ Prohibitive for LE targets

Smaller/Dense Components Require Smaller Vias, Drilling/Plating Technology is a Step Function in $

No Insight into Long-Term Price Relaxation



IBM Controls Driving Cost - Our Understanding

Qualified, Robust LaminateFixed Laminate & OSP ChoiceConstrained Cross Section and L/WConstrained Wiring (no authority to move traces/adjust pad diameters)Constrained Tolerances (geometry, drilling, plating, etc.)

Open Holes (not closed w/ plating or SM-tented)

Cross Section Construction Rqmts (2-ply/HiPot)

IBM Specifications vs. IPCMultiple Zo targets per layer



Cost Savings Not Realized

Good Panel Utilization– Ineffective if Assembly CM requires alternate array design or

can’t accommodate panel in test equipment.8mil vias Qualified– Still more expensive to use 10mil drill bits/plate high AR viasSupplier Geography– Material selection can wash out svgs between plant sites.Zo & l/w target– Certain core / fill thickness materials are inherently more

expensive– Not just thin vs. thick dielectrics.



Approaches to Cost Take-Downs

Bully the Vendor for Price Reductions (-)

Give Vendor Complete Freedom to “Fix” Design to Suit Preferred Operations (mat’l, process & test) (-)

Qualify additional vendors in lower cost geos (-/+)

Forge Business Partnerships with guaranteed volumes (+/-)

Respond to Vendor Capability with Design Modifications (+)



Conclusion

PCB Designs should Leverage Vendor Strengths– Improved Yields (first pass and production)– Lower Price with Appropriate MarginsPCB Pricing is Complicated – IBM Understands– Beginning of process: most vulnerable time for us to make a

design choice that adversely impacts cost. – Not enough info to share w/ vendors for them to give an

accurate RFI. – Cost Factors Must be Weighed IndependentlyFull Disclosure with Cost Surveys Needed– Responses Remain Confidential



Vendor Input Needed

PCBs are becoming piece-priced. Individual factors are weighed against each other to determine the best cost approach.– Difficult to Achieve:

• with conflicting/incomplete cost information available now.• with length of time vendors require for RFI activity.• with lack of response by vendors to cost inquiries, RFIs or

design cost sizings.

qualification of pcb fabricators / standard loss tangent laminates

Documents