qoriq ls1012a product brief - mouser electronics · 3 product-ready software solutions nxp offers...

1 IntroductionThis document provides an overview of the features andfunctionalities of the LS1012A integrated processor. LS1012Ais targeted at the consumer NAS, IoT gateway, broadbandEthernet gateway, and industrial automation markets, anddelivers an unmatched level of features and performance. TheLS1012A features an advanced 64-bit ARM v8 Cortex-A53processor, with 32 KB of parity protected L1 I-cache and L1D-cache, as well as 256 KB of ECC protected L2 cache.Hardware coherency is supported by the ARM CCI-400interconnect. LS1012A offers an optimized blend of systemacceleration logic, extremely small package size, and the ultra-low power utilization required for fan-less IoT and broadbandgateways, consumer NAS, industrial automation and generalembedded applications.

The LS1012A processor is a cost-effective, power-efficient,and highly integrated system-on-chip that extends the reach ofNXP’s QorIQ communications processors into new low-power applications without compromising on performance.The device delivers greater packet processing performancethan any prior sub 1 W microprocessor with extremely power-efficient 64-bit Cortex v8 core running at up to 800 MHz andyielding over 2,000 Coremarks. Also, it includes an integratedhardware packet acceleration engine, together with high-speedinterfaces and support for DDR3L running at 1000 MHz.High-speed peripherals include PCIe Gen2, USB 2.0, SATA3.0, super speed USB 3.0 and dual gigabit Ethernetcontrollers, with support for RGMII, and SGMII that can

NXP Semiconductors Document Number: LS1012APB

Product Brief Rev. 0, 06/2016

QorIQ LS1012A Product Brief

© 2016 NXP B.V.

Contents

1 Introduction................................................................1

2 Application examples................... ............................ 2

3 Product-ready software solutions....... .......................5

4 Features summary....................... .............................. 6

accommodate 2.5 GB Ethernet PHYs. To deliver outstanding security performance, the device features a hardware-basedacceleration engine to support secure boot, and networking with both ARM TrustZone and NXP’s QorIQ Trust Architecture.

For additional BOM cost savings, the super speed USB3.0 controller is supported by an integrated PHY, which includes adedicated SerDes.

2 Application examplesLS1012A is a very small footprint, highly versatile and ultra-power-efficient microprocessor that can be configured tosupport consumer NAS, IoT aggregation, entry-level broadband gateway applications and many other low-endcommunication applications. The following sections provide several use case examples supported by LS1012A.

2.1 Entry-level broadband Ethernet gatewayThe figure below shows LS1012A supporting an entry-level broadband Ethernet gateway. Point-to-point broadband gatewayscan be used for copper, wireless, or fiber-to-the-home applications, which use different optical connectors for Fiber WANinterface transceivers. With this technology, ISPs and Telcos (operators and carriers) can offer greater bandwidth over greaterdistances to deliver IPTV or home entertainment services to end customers.

Figure 1. Entry-level broadband Ethernet gateway

2.2 Consumer NAS/DAS and battery-powered NAS applicationsThe increasing adoption of digital cameras and Wi-Fi connectivity in practically all mobile devices, including laptop PCs,tablets, smart phones, and digital cameras has led to an ever increasing demand for storage, over both wired and wirelessnetworking links. As shown in the figures below, LS1012A has been engineered to support both wired and wireless storageneeds with a high-speed USB 3.0 controller for direct attached modes, or through a Wi-Fi radio connected to its PCIe port, orone of the two SDIO ports.

Application examples

QorIQ LS1012A Product Brief, Rev. 0, 06/2016

2 NXP Semiconductors

Following are the advantages of LS1012A when used to support consumer and battery-powered NAS application:

• Scalable 64-bit ARM Cortex-A53 core that supports Wi-Fi devices using the latest generation of 802.11ac Wi-Firadios.

• Half-speed battery mode support for extending wireless NAS performance.• PCIe Gen 2 controller to support dual-band 802.11ac WLAN networks.• USB 3.0 to support LTE/4G wireless broadband backhaul or super-fast direct attachment.• SATA 3.0 to support high-speed data streaming to both disk-based or solid-state storage media devices.• Dual SD/MMC enables configuration for small media storage or low-bandwidth wireless connectivity.

Figure 2. Consumer NAS/DAS with optional Wi-Fi

Figure 3. Battery-powered consumer NAS



NXP Semiconductors 3

With the ever increasing demand for scalable, cost-efficient storage growing day by day, there has been a significant movetoward modular, Ethernet to SATA storage solutions. As shown in the figure below, LS1012A addresses this use case with avery low cost system design, where a HDD or SSD can be attached through SATA to a board that supports single or dualEthernet ports. To differentiate, LS1012A supports the new 2.5 GB Ethernet PHY's, which significantly increase data transferspeeds.

Following are the advantages of LS1012A when used to support Ethernet NAS drive:

• Scalable 64-bit ARM Cortex-A53 core that supports high-performance NAS.• Dual Ethernet controllers, which can be configured as the first controller supporting 2.5 GB SGMII PHY and the

second controller supporting 1 GB RGMII PHY.• SATA 3.0 to support high-speed data streaming to both disk-based or solid-state storage media devices.

Figure 4. Ethernet to SATA HDD

2.3 IoT gatewaysThe figures below illustrate the flexibility of LS1012A showing different use cases for IoT aggregators and gateways,including support for next generation 802.11ac wireless LAN networking and a variety of protocols used for IoT nodeconnectivity.

Following are the advantages of using LS1012A for IoT gateways:

• Scalable 64-bit ARM Cortex-A53 core that supports Wi-Fi devices using the latest generation of 802.11ac Wi-Firadios.

• PCIe Gen 2 controller to support dual-band 802.11ac WLAN networks.• USB 3.0 to support for LTE/4G wireless broadband backhaul or super-fast data transfers.• SATA 3.0 to support for high-speed data streaming to both disk-based or solid-state storage media devices.• Dual SD/MMC enables configuration for small media storage or low-bandwidth wireless audio streaming.




Figure 5. IoT gateway with LS1012A

Figure 6. IoT gateway with audio networking

3 Product-ready software solutionsNXP offers two solutions for software development on LS1012A:

• QorIQ SDK: The QorIQ is a free-of-charge Linux-based enablement solution based on the Yocto-build environment,which supports nearly all the QorIQ family devices. For more information, refer Linux® SDK for QorIQ Processorsavailable at www.nxp.com.

• Vortiqa application solution kit (ASK): The Vortiqa ASK is a premium production-grade Linux®-based OpenWRTsoftware platform, which optimizes system performance for networking and storage applications. The field-hardenedand feature-rich OpenWRT software package enables customers to significantly shorten their software design cycle andachieve quicker time to market without compromising on quality or features.The VortiQa ASK offer two full suite ofnetworking application packages covering a variety of market needs such as service provider, enterprise networkingand the industrial segment. These packages are:

Product-ready software solutions



http://www.nxp.com/

• Broadband Home Router: ideal for small business routers, mobile broadband routers, integrated services, Mi-Fiand consumer wireless access points applications

• Network Attached Storage: ideal for personal storage, wireless personal storage, NAS and chip-on-driveapplications

These packages allow access to the source code of all the board support packages, OpenWRT ASK and binaries of packet-forwarding engine. A list of supported features can be found in the LS1012 ASK webpages.

4 Features summaryThe chip includes the following distinctive functions and features:

• One 64-bit ARM® v8 Cortex®-A53 core with the following capabilities:• Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC protection• Speed up to 800 MHz• Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache• Neon SIMD engine• ARM v8 cryptography extensions

• One 16-bit DDR3L SDRAM memory controller:• Up to 1.0 GT/s• Supports 16-/8-bit operation (no ECC support)• Supports for x16 devices (also supports two x8 devices totaling to 16-bit data)

• ARM core-link CCI-400 cache coherent interconnect• Packet Forwarding Engine (PFE)• Cryptography acceleration (SEC)• Ethernet interfaces supported by PFE:

• Two quad-speed Ethernet MACs supporting 2.5G, 1G, 100M, 10M• Supports RGMII, SGMII 1G, SGMII 2.5G• Up to 2 x SGMII supporting 1000 or 2500 Mbps.• Supports 1000Base-KX• Energy efficient Ethernet support (802.3az)

• One Configurable x3 SerDes:• Two Serdes PLLs supported for usage by any SerDes data lane• Supports up to 6 GBaud operation

• High-speed peripheral interfaces:• One PCI Express Gen2 controller, supporting x1 operation• One serial ATA (SATA Gen 3.0) controller• One USB 3.0/2.0 controller with integrated PHY• One USB 2.0 controller with ULPI interface. Supports operation only as a stand-alone USB host.

• Additional peripheral interfaces:• One quad serial peripheral interface (QuadSPI) controller for serial NOR flash• One serial peripheral interface (SPI) controller• Two enhanced secure digital host controllers supporting SD 3.0, eMMC 4.4 and eMMC 4.5 modes• Two I2C controllers• One 16550 compliant DUART (two UART interfaces)• Two general purpose IOs (GPIO)• Two FlexTimers• Five synchronous audio interfaces (SAI) supporting I2S• QorIQ platform's trust architecture• Debug supporting run control, data acquisition, high-speed trace, and performance/event monitoring• Pre-boot loader (PBL) provides pre-boot initialization and RCW loading capabilities• Single-source clocking solution enabling generation of core, platform, DDR, SerDes, and USB clocks from a

single external crystal and internal crystal oscillator• Thermal monitor unit (TMU) with +/- 3C accuracy

Features summary



• Two WatchDog timers• ARM generic timer

4.1 Block diagramThe figure below shows the major functional units within the LS1012A.

Watchpoint Cross Trigger

Trust Zone

Power Management

SPI

DUART

16-bitDDR3L

Memory Controller

Real Time Debug

PerfMonitor2x GPIO, 2x I2C

2x eSDHC

256 KBL2 - Cache

Secure Boot

2x FlexTimers

Security 5.5(XoR, CRC)

PFE

MAC1

PC

I Exp

ress

2.0

SAT

A 3

.0

Trace

3-Lane 6 GHz SerDesUSB3.0 w/PHY

QuadSPI

Cache Coherent Interconnect (CCI-400™)

32 KBD-Cache

32 KBI-Cache

ARM® Cortex®

A53 64b Core

5x I2S

MAC2

RG

MII S

GM

II

USB2.0 (ULPI)

eDMA

SG

MII

Figure 7. Block diagram

4.2 ARM Cortex-A53 coreThe ARM® Cortex®-A53 processor is an extremely power efficient ARM v8 processor capable of supporting 64-bit codeseamlessly. It makes use of a highly efficient 8-stage in-order pipeline balanced with advanced fetch and data accesstechniques for performance.

The chip features one high-performance Cortex-A53 core:

• 64-bit execution state for scalable high performance• 32 KB Instruction Cache, 32 KB Data Cache with parity protection• NEON technology - Accelerates multimedia and signal processing algorithms such as video encode/decode, 2D/3D

graphics, gaming, audio and speech processing, image processing, telephony, and sound synthesis. Also useful inaccelerating floating point code with SIMD execution

• Floating point unit - Hardware support for floating point operations in half-, single- and double-precision floating pointarithmetic. This also includes IEEE754-2008 enhancements

• Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution• Integrated low-latency high bandwidth level-2 cache controller, supporting 256 KB coherent L2 cache with ECC

(correct single-bit errors and detect double-bit errors)

Features summary



• 16 way cache with sequential TAG and Data RAM access• Automatic data prefetching into L2 cache for load streaming

• NEON SIMD extensions onboard

4.3 ARM CoreLink CCI-400 cache coherent interconnectCCI-400 combines interconnect and coherency functions into a single module. The CCI-400 cache coherent interconnect isan infrastructure component that supports:

• Data coherency between the Cortex-A53 core and all I/O masters with three independent Points-of-Serialization (PoS)and full barrier support high-bandwidth, interconnect functionality between the masters and up to three slaves

• Quality-of-Service (QoS) regulation for shaping traffic profiles• Performance monitoring unit (PMU) to count performance-related events• Programmers view (PV) to control the coherency and interconnect functionality

4.4 PreBoot loader and non-volatile memory interfacesThe PBL performs the following functions:

• Simplifies boot operations, replacing pin strapping resistors with configuration data loaded from non-volatile memory.• Uses the configuration data to initialize other system logic and to copy data from QuadSPI into fully initialized DDR or

OCRAMs.• Releases CPU from reset, allowing the boot processes to begin from fast system memory.

The non-volatile memory interfaces accessible by the PBL are described in the subsequent sections. Note that these interfacesmay be accessed by software running on the CPU following boot; they are not dedicated to the PBL.

4.5 Multi-mode DDR controller (MMDC)The MMDC is a configurable high performance and optimized DDR controller that supports DDR3L. The key features are asfollows:

• Supports data rate up to 1.0 GT/s• One 16-bit DDR3L SDRAM memory controller• Supports 16-bit operation (no ECC support)• Supports one x16 or two x8 devices totaling to 16-bit data• Supports one chip-select

4.6 Enhanced direct memory access (eDMA) and direct memoryaccess multiplexer (DMAMUX)

The eDMA module has the following general features:

• 32 channels support independent 8-, 16- or 32-bit single value or block transfers• Supports variable sized queues and circular queues• Source and destination address registers are independently configured to post increment or remain constant• Each transfer is initiated by a peripheral, CPU, periodic timer interrupt or eDMA channel request

Features summary



• Each DMA channel can optionally send an interrupt request to the CPU on completion of a single value or blocktransfer

• DMA transfers possible between system memories, General Purpose I/Os (GPIOs) and Slave Peripherals that supportDMA

• Programmable DMAMUX allows assignment of any DMA source to any available DMA channel with up to a total of64 potential request sources

The DMA channel request can be initiated by the following peripherals:

• 2x I2C• 1x SPI• QuadSPI

4.7 DUART

DUART supports full-duplex operation and is compatible with the PC16450 and PC16550 programming models. All thetransmitter and receiver support 16-byte FIFOs. It also supports auto flow for clear to send (CTS_B) and ready to send(RTS_B) modem control functions.

4.8 FlexTimer module (FTM)

The key features of the FTM are as follows:

• Selectable FTM source clock and programmable prescaler• 16-bit counter supporting free-running or initial/final value and counting is up or up-down• Input capture, output compare, edge aligned and center aligned PWM modes• Operation of FTM channels as pairs with equal outputs, pairs with complimentary outputs, or independent channels

with independent outputs• Deadtime insertion is available for each complementary pair• Generation of hardware triggers• Software control of PWM outputs• Up to four fault inputs for global fault control• Configurable channel polarity• Programmable interrupt on input capture, reference compare, overflowed counter or detected fault condition• Quadrature decoder with input filters, relative position counting and interrupt on position count or capture of position

count on external event• DMA support for FTM event

4.9 Universal serial bus (USB) 3.0 controller and PHYThe universal serial bus (USB) 3.0 controller with integrated PHY provides point-to- point connectivity that complies withthe Universal Serial Bus Revision 3.0 Specification. The USB controller and integrated PHY can be configured to operate asa stand-alone host, a stand-alone device, or with both host and device functions operating simultaneously.

The host and device functions are configured to support the following types of USB transfers:

• Bulk• Control• Interrupt• Isochronous

Features summary



Key features of the USB 3.0 controller include the following:

• Supports OTG 2.0• USB dual-role operation and can be configured as host or device• Supports operation as a stand-alone USB device

• Supports one upstream facing port• Supports six programmable USB endpoints

• Supports operation as a stand-alone USB host controller• Supports USB root hub with one downstream-facing port• Extensible host controller interface (xHCI) compatible

• Super-speed (5 GT/s), High-speed (480 Mbps), and full-speed (12 Mbps) operations.

4.10 USB 2.0 controller with ULPI interfaceThe USB 2.0 controller with ULPI interface provides point-to-point connectivity that complies with the USB specification,Rev. 2.0. The device doesn't have an integrated PHY for this USB 2.0 controller and instead supports external PHY withULPI interface.

The USB 2.0 controller with ULPI interface can be configured to operate only as a stand-alone host controller.

Key features of the USB 2.0 controller include the following:

• Complies with USB specification, Rev. 2.0• Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations.• Supports operation only as a stand-alone USB host controller

• USB root hub with one downstream-facing port• Enhanced host controller interface (EHCI) compatible

4.11 High-speed I/O interfacesThe chip supports the SGMII, PCI Express 2.0, USB 3.0, and SATA3 high-speed I/O interface standards.

4.11.1 Serial advanced technology attachment (SATA) controllerThe serial advanced technology attachment (SATA) controller is compliant with the Serial ATA 3.0 Specification and theAHCI 1.3.1 specification. The SATA controller includes the following features:

• Supports SATA Gen1, Gen2, and Gen3 data rates: 1.5 GBaud (first-generation SATA), 3 GBaud (second-generationSATA), and 6 GBaud (third-generation SATA)

• Single SATA 3.0 controller with chip-level interface• Supports asynchronous notification and hot plug

• Asynchronous signal recovery• Link power management• Native command queuing• Staggered spin-up• Port multiplier support

• Standard ATA master-only emulation• Supports ATA shadow registers• SATA superset registers• SError, SControl, SStatus• Interrupt driven• Supports power management

Features summary



• Supports error handling and diagnostic features• Far-end/near-end loopback• Failed CRC error reporting• Increased ALIGN insertion rates• Scrambling and CONT override

4.11.2 PCI Express 2.0 interfaceThe PCI Express interface is compliant with the PCI Express Base Specification Revision 3.0. Key features of the PCIExpress interface include the following:

• Power-on reset configuration options allow root complex or endpoint functionality• The physical layer operates at 2.5 or 5 Gbps data rate• Both 32- and 40-bit addressing and 256-byte maximum payload size• Full 64-bit decode with 36-bit wide windows• Inbound INTx transactions• Message Signaled Interrupt (MSI) transactions

4.11.3 SGMIIThe serial gigabit media independent interface (SGMII) is a high-speed interface linking the Ethernet controller with anEthernet PHY. SGMII uses differential signaling for electrical robustness. Only four signals are required: receive data and itsinverse, and send data and its inverse; no clock signals are required. SGMII operates up to 2.5 or 1 Gbps depending on themaximum rate selection.

4.12 Integrated interchip sound (I2S) / synchronous audiointerface (SAI)

LS1012A integrates five I2S/SAI modules, out of which two are full duplex and three are simplex. The I2S module provides asynchronous audio interface (SAI) that supports full-duplex serial interfaces with frame synchronization such as I2S, AC97,TDM, and codec/DSP interfaces.

The I2S/SAI module provides the following features:• Transmitter with independent bit clock and frame sync supporting a data line• Receiver with independent bit clock and frame sync supporting a data line• Maximum frame size of 32 words• Word size between 8 bits and 32 bits• Word size configured separately for the first word and the remaining words in a frame• Asynchronous 32 x 32-bit FIFO for each transmit and receive channel• Supports graceful restart after FIFO error

4.13 Enhanced secure digital host controller and SDIOThe chip supports two eSDHC interfaces.

• eSDHC1: Supported primarily for SD cards. Card initialization happens at 3.3V, but can dynamically switch to 1.8V.• eSDHC2: Supported for 1.8V embedded SDIO and 1.8V eMMC.

Key features of the SD/eSDHC/eMMC controller include the following:

Features summary



• Conforms to the SD host controller standard specification version 3.0• Compatible with the MMC system specification version 4.5• Compatible with the SD Memory Card Physical Layer specification version 3.01• Compatible with the SD - SDIO card specification version 2.0• Designed to work with eMMC devices as well as SD Memory, SDIO, and SD combo cards and their variants• Supports SD UHS-1 speed modes

Table 1. eSDHC modes supported on chip

Mode eSDHC1

4 bit

eSDHC2

4 bit

SD (SD cards/SDIO cards/embedded SDIO)

SD memory card in Default(25 MHz) / High speed (50 MHz) Y N

SDIO card in Default(25 MHz)/High speed (50 MHz) Y N

SD memory card SDR50 Y N

SD memory card DDR50 Y N

SD memory card SDR104 Y N

SDIO card SDR50 Y N

SDIO card DDR50 Y N

SDIO card SDR104 Y N

eSDIO SDR50 N Y

eSDIO DDR50 N Y

eSDIO SDR104 N Y

MMC/ eMMC

MMC card in Default(20MHz)/High speed (52MHz) N N

eMMC DDR N Y

eMMC FS/HS/HS200 N Y

4.14 Integrated security engine (SEC)The security engine (SEC 5.5) is designed to support Secure Boot, ARM TrustZone as well as Trust Architecture. Themodular and scalable SEC 5.5 supports booting to a known good state (secure boot) with untamperable boot code, keystorage, IO protection, and secure debug.

The SEC 5.5 security engine can process all algorithms associated with IPSec, IKE, SSL/TLS, iSCSI, SRTP, IEEE Std802.11i™, IEEE Std 802.16™ (WiMAX), and IEEE Std 802.1AE™ (MACSec).

Also, the SEC 5.5 is optimized to perform multi-algorithmic operations (for example, 3DES-HMAC-SHA-1) in a single passof the data.

The SEC 5.5 security engine supports the following key features and functions:

• XOR engine for parity checking in RAID storage applications• Four crypto-channels, each supporting multi-command descriptor chains• Cryptographic execution units:

• PKHA - Public Key Hardware Accelerator• DESA - Data Encryption Standard Accelerator• AESA - Advanced Encryption Standard Accelerator• MDHA - Message Digest Hardware Accelerator

Features summary



• CRCA - Cyclical Redundancy Check Accelerator• RNG - Random Number Generator

4.15 Inter-integrated circuit (I2C) controller

The I2C is integrated with eDMA and allows communication between a number of devices. LS1012A supports two I2Ccontrollers.

4.16 Quad serial peripheral interface (QuadSPI)The QuadSPI is integrated with eDMA and has the following general features:

• Boot from QuadSPI flash• Interface for external quad serial flash memory for code/data storage and code execution• Supports industry standard: Single, dual and quad mode serial flashes

4.17 Serial peripheral interface (SPI)

The chip supports the synchronous serial bus for communication to an external device.

The SPI module is integrated with eDMA and supports the following features:

• Full-duplex, three-wire synchronous transfers• Buffered transmit operation using the transmit first in first out (TX FIFO) with depth of 16 entries• Support for 8/16-bit access to the PUSH TX FIFO register data field• Buffered receive operation using the receive FIFO (RX FIFO) with depth of 16 entries• Asynchronous clocking scheme for register and protocol interfaces

4.18 Watchdog timer (WDOG)

The WDOG monitors internal system operation and forces a reset in case of failure. It operates on RTC 32 KHz clock and IPclock (platform clock). LS1012A supports two Watchdog timers. Out of two WDOGs, one is dedicated for Trustzone supportand another is for A53 core.

Features summary



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Information in this document is provided solely to enable system and softwareimplementers to use NXP products. There are no express or implied copyrightlicenses granted hereunder to design or fabricate any integrated circuits basedon the information in this document. NXP reserves the right to make changeswithout further notice to any products herein.

NXP makes no warranty, representation, or guarantee regarding the suitability ofits products for any particular purpose, nor does NXP assume any liability arisingout of the application or use of any product or circuit, and specifically disclaimsany and all liability, including without limitation consequential or incidentaldamages. “Typical” parameters that may be provided in NXP data sheets and/orspecifications can and do vary in different applications, and actual performancemay vary over time. All operating parameters, including “typicals,” must bevalidated for each customer application by customer's technical experts. NXPdoes not convey any license under its patent rights nor the rights of others. NXPsells products pursuant to standard terms and conditions of sale, which can befound at the following address: nxp.com/SalesTermsandConditions.

NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTERWORLD, Freescale, the Freescale logo, and QorIQ are trademarks of NXP B.V.All other product or service names are the property of their respectiveowners. ARM, AMBA, ARM Powered, Cortex, and TrustZone are registeredtrademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere.CoreLink is trademarks of ARM Limited (or its subsidiaries) in the EU and/orelsewhere. All rights reserved. Synopsis and Design Ware are registeredtrademarks of Synopsis, Inc. Portions of this document contain informationprovided by Synopsis, Inc., reprinted with permission.

© 2016 NXP B.V.

Document Number LS1012APBRevision 0, 06/2016

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