qinetiq q20 high sensitivity gps receiver · 2019. 10. 12. · 6.2.28 pin 28 2v8_test 21 6.2.29 pin...

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Copyright © QinetiQ ltd 2005QinetiQ Proprietary

QinetiQ Q20High SensitivityGPS Receiver

Specification

QINETIQ/FST/I&C/SPEC044447/2.0

27th October 2005

Any person finding this document should hand it or post it to the Group Security Manager, QinetiQ Limited, Cody Technology Park, Farnborough, Hampshire GU14 0LX, with particulars of how and where found.

Requests for wider use or release must be sought from:

Intellectual Property DivisionQinetiQ LtdCody Technology ParkFarnboroughHampshireGU14 0LX

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QINETIQ/FST/I&C/SPEC044447/2.0 Page 2QinetiQ Proprietary

Administration pageRecord of changes

Issue Date Detail of Changes

1.0 17th November 2004 First Formal Release

1.1 17th May 2005 Updated pin-out descriptionsUpdated minimum application circuit diagram

2.0 27th May 2005 Updated for Version 2 software performance improvements

'This document is supplied in confidence to the recipient for information purposes only and is not to be released outside the recipient's organisation without the prior written permission of QinetiQ. Requests for permission for wider use or release should be made to Intellectual Property Department, QinetiQ.

QinetiQ accepts no responsibility for any claims or damages arising out of the use of this document, or from the use of modules based on this document, including but not limited to claims in respect of loss or damage based on infringement of patents, copyright or other intellectual property rights. QinetiQ makes no warranties, either expressed or implied, with respect to the information and specifications contained in this document and the recipient accepts full responsibility for the use to which such information is put'.

Although every effort has been made to ensure the details are correct at the time of issue, QinetiQ reserves the right to change this specification without notice.

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List of contents1 Introduction 5

1.1 Technical Assistance 51.2 Your Comments 5

2 Q20 Module Functional Description 62.1 General Description 62.2 Features 62.3 Block Schematic 72.4 Front End Filter and Low Noise Amplifier 72.5 Radio Frequency Front End 72.6 Baseband Processor 82.6.1 Signal Processing 82.6.2 Navigation Solution 82.6.3 Real Time Clock & EEPROM 82.6.4 Input / Output 92.6.5 Reset Logic 92.7 Operating Modes 102.8 Operation on power up 102.9 Operation on power interrupt 102.10 Power Consumption 112.11 Protocols 11

3 Performance Specification 12

4 Mechanical Specification 134.1 Dimensions 134.2 Specification 134.3 PCB Outline 144.4 Recommended Layout Footprint 144.5 Electrical Connections 15

5 Electrical Specification 165.1 Absolute Maximum Ratings 165.2 Operating Conditions 165.3 Q20 Module Pin I/O Details 175.4 RF Input Parameters 17

6 Interfaces 186.1 Outline Description 186.1.1 Serial Interface 186.1.2 Reserved 186.2 Detailed Pin Description 196.2.1 Pin 1 nTRST 196.2.2 Pin 2 nRESET 196.2.3 Pin 3 COM 1 RX 19

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6.2.4 Pin 4 COM 1 TX 196.2.5 Pin 5 COM 2 RX 196.2.6 Pin 6 COM 2 TX 196.2.7 Pin 7 COM 3 RX 196.2.8 Pin 8 COM 3 TX 196.2.9 Pin 9 MODE 196.2.10 Pin 10 EXT CLOCK 196.2.11 Pin 11 Reserved 196.2.12 Pin 12 Reserved 196.2.13 Pin 13 VBATT 206.2.14 Pin 14 1V8_Test 206.2.15 Pin 15 DIG_GND 206.2.16 Pin 16 VCC 206.2.17 Pin 17 FREQ OUT 206.2.18 Pin 18 TIMEMARK 206.2.19 Pin 19 Reserved 206.2.20 Pin 20 LED 3 206.2.21 Pin 21 LED 2 206.2.22 Pin 22 LED 1 206.2.23 Pin 23 TDI 206.2.24 Pin 24 TCK 206.2.25 Pin 25 JTAGSEL 206.2.26 Pin 26 TDO 206.2.27 Pin 27 TMS 206.2.28 Pin 28 2V8_Test 216.2.29 Pin 29 RF_GND 216.2.30 Pin 30 RF_GND 216.2.31 Pin 31 RF_IN 216.2.32 Pin 32 RF_GND 21

7 References 22

8 Abbreviations 22

9 Glossary 23

A Q20 Module Minimum Application Circuit 24A.1 Passive Antenna 24A.2 Active Antenna 25

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1 IntroductionThank you for your interest in the QinetiQ Q20 High Sensitivity GPS Receiver. The Q20 represents the state of the art in GPS receiver technology. The Q20’s high sensitivity enables GPS positioning in locations where other receivers fail to operate and therefore brings the benefits of GPS to a host of new applications.

This document describes the features and specifications of the QinetiQ Q20 GPS module, a high-sensitivity, low power, GPS receiver macro-component.

The document details the mechanical and electrical characteristics of the Q20 module, and is intended to aid the integration of the module into higher-level systems and products.

1.1 Technical Assistance

If you are experiencing difficulties integrating the Q20 module which cannot be resolved using the documentation supplied, please email us at the following address and we will do our best to assist you as quickly as possible.

Send an email to: [email protected]

1.2 Your Comments

We are continually trying to improve our products and services and we value your feedback. If you have any suggestions or comments please forward them to the following address and we will endeavour to take account of them in our future products and updates.

Send an email to: [email protected]

Figure 1: Q20 High Sensitivity GPS Receiver Module

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2 Q20 Module Functional Description

2.1 General Description

The QinetiQ Q20 GPS Module is a high sensitivity, ultra-compact GPS receiver offering state of the art indoor and outdoor positioning capability. The high sensitivity of the Q20 module enables operation in environments where conventional GPS receiver technology cannot function, e.g. urban canyons, under wet foliage and indoors. The Q20’s novel architecture also enables extremely rapid Time-To-First-Fix (TTFF) in a conventional signal environment.

The module is based on a state of the art QinetiQ GPS baseband processor, which provides rapid signal acquisition and very low signal strength tracking capability. The QinetiQ baseband processor provides digital interfaces for access to the positioning output and control of the module functions. Embedded in the processor are highly reliable software and navigation library functions. These have been optimised for execution on the baseband’s high performance ARM966 microprocessor.

The baseband processor is integrated with a low noise RF front end to give unprecedented sensitivity in such a small receiver module. The RF front end and associated filtering provide effective protection from out of band interference.

The module also contains a real time clock that can be battery backed and a low drift temperature compensated crystal oscillator, optionally an external reference oscillator can be used instead1. There is onboard memory for storing all the necessary receiver software plus data that can assist acquisition: time, date, frequency bias, last known position, ephemeris and almanac.

2.2 Features

The Q20 offers the following features:• 12 channels to provide an All Satellites in View tracking capability• Fast Time-To-First-Fix (TTFF)• High sensitivity with or without Network Assistance• Almanac and Ephemeris data demodulation at extremely low signal

levels• 1 Hz position and velocity updates• 3 Serial Ports• 1 Pulse Per Second (1 PPS) timing output• Operating Voltage 3.0 to 3.6 V• Embedded ARM966 processor• Wide operating temperature range: -30°C to +80°C• Small size: 22.0 mm x 26.5 mm x 3.3 mm (including RF shield)• Weight 2.5 g

1 Build-time option

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2.3 Block Schematic

The Q20 module is a complete GPS receiver requiring a minimum of external components and connections to operate. The user can be up and running simply by connecting power, an antenna and a device to the serial port capable of interpreting standard NMEA data messages. A demonstration kit is available to make the process even easier. This includes a boxed Q20 with rechargeable battery and mains power supply together with all the cables and software required to start exploring the benefits of high sensitivity GPS.

The main functional components within the Q20 are shown in figure 2 and described in detail below.

ExternalAntenna

VCC

VBATT

External Reset

Freq Out

Serial I/O3

GPS Status3

BasebandProcessor

RFFront End

Front EndFilter

IF Filter

RF PSU

TCX

O I2C RTC,

Reset LogicE2PROM

Crystal

DigitalPower

LNA

Mode

External Clock

1 PPSExternalAntenna

VCC

VBATT

External Reset

Freq Out

Serial I/O3

GPS Status3

BasebandProcessor

RFFront End

Front EndFilter

IF Filter

RF PSU

TCX

O I2C RTC,

Reset LogicE2PROM

Crystal

DigitalPower

LNA

Mode

External Clock

1 PPS

Figure 2: Q20 Block Schematic

2.4 Front End Filter and Low Noise Amplifier

GPS signals from the antenna first encounter a high performance ceramic front-end filter which effectively removes any unwanted signals (i.e. signals outside the L1, C/A-code GPS bandwidth). After filtering the signals are amplified by an onboard Low Noise Amplifier (LNA) prior to input into the RF-front end.

2.5 Radio Frequency Front End

The RF Front End used in the Q20 is a single Silicon-Germanium BiCMOS device. It amplifies the very weak GPS signals to a magnitude useable by the digital circuits. To do this it requires a power gain in excess 140 dB. Such a high gain, applied to all the signals incident at the antenna, would result in very large signals in the RF/IF system, so it is also necessary to incorporate filters to exclude unwanted signals outside the GPS bandwidth. The RF section of the receiver down-converts the GPS signals to an Intermediate Frequency (IF) which the baseband processor’s digital circuits can process. The RF section of the receiver is driven by the reference oscillator.

Control of the RF device is via a digital 4-wire Serial Peripheral Interface (SPI). This interface provides control of power to the RF circuits, Automatic Gain Control (AGC),

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synthesiser dividers, and Analogue to Digital (A-to-D) thresholds. Adjustable A-to-D thresholds are helpful in improving signal-to-noise ratios when operating in interference environments.

2.6 Baseband Processor

2.6.1 Signal Processing

The IF signal, received at the RF/baseband interface, is a digitised composite of the signal from all received GPS satellites. It retains the full bandwidth of the GPS signal.

The baseband process separates out the individual satellite signals, by correlation with their individual Pseudo Random Noise (PRN) codes, removes any residual IF and Doppler frequency components and then provides further filtering to a rate at which software techniques become more appropriate.

Signal acquisition is implemented using a parallel search strategy in both code and frequency. In code space the baseband processor provides many more parallel correlators than conventional GPS receivers. Further parallel processing is provided for a search in the frequency domain, by using a powerful dedicated Fast Fourier Transform (FFT) engine implemented in hardware.

The reference oscillator provides the digital clock signal to the baseband processor.

2.6.2 Navigation Solution

The baseband processor contains an embedded on-board ARM966 processor, which uses the raw measurements provided by the dedicated signal processing to calculate an accurate navigation solution (position, velocity and time) using an advanced Kalman filter. The processor also executes proprietary algorithms to reject interference and reduce the effects of multipath.

2.6.3 Real Time Clock & EEPROM

The Q20 module contains a Real Time Clock (RTC), reset controller and 32K x 8 Bits of EEPROM connected to the baseband processor on a 2-wire I2C bus. The RTC can be battery backed by the user, thus remaining active when primary power is removed from the Q20 module. This will enable the module to quickly establish which satellites are in view upon switch on for faster starts from power on.

On power down, the EEPROM is used to store useful information including an Almanac, Ephemeris, last known position and frequency bias. This information, in conjunction with date and time information from the RTC, enables the Q20 module to rapidly acquire GPS satellite signals from switch-on.

The Q20 module software provides EEPROM management. For example Write cycles are managed to provide an EEPROM lifetime of more than 10 years.

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2.6.4 Input / Output

The module hardware provides various Input / Output (I/O) options for transferring information and data to / from the module.

• Three serial I/O ports at CMOS level (3V0 - 3V3), Baud rate configurable in software. Default settings are as follows:COM 1: 4800 Baud, no parity, 1 stop bit

NMEA (GGA, GLL, GSA, GSV, RMC) outputQinetiQ proprietary ASCII commands in and outQinetiQ proprietary network assist

COM 2: 38400 Baud, no parity, 1 stop bitNMEA (GGA, GLL, GSA, GSV, RMC) outputQinetiQ proprietary ASCII commands in and outQinetiQ proprietary network assist

COM 3: 4800 Baud, no parity, 1 stop bitNMEA (GGA, GLL, GSA, GSV, RMC) outputQinetiQ proprietary ASCII commands in and outQinetiQ proprietary network assist

Please note that full network assistance data may take a long time to download if used at low Baud rates.

• One Pulse Per Second (1 PPS) precision timing output

• Frequency out - reserved for timing application software.

• Mode – reserved for High Dynamic software

• Three GPS status outputs (to drive LEDs) as followsLED 1: On when there is no fix and the Q20 is searching for satellitesLED 2: Pulses high for each satellite tracked without ephemeris dataLED 3: Pulses high for each satellite tracked with ephemeris data

• External reset input

• External clock input. This option (specified at build time) enables the use of an external reference oscillator in place of the on-board TCXO

2.6.5 Reset Logic

An onboard reset control is provided to perform a controlled reset of the device under ‘brown-out’ conditions. Reset occurs at 2.85 V ±100 mV.

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2.7 Operating Modes

Operating Mode Description

Normal In normal mode selected peripherals are enabled and the system runs at its designated operating frequency. The Q20 acquires and tracks satellites and generates a navigation solution.

In this mode, the Q20 offers high performance, but consumes the most power.

Sleep In sleep mode, the Phase Lock Loop (PLL) output is dropped to a very low level. GPS functionality is not available. UART functionality is significantly decreased, but it is still be possible for serial activity to cause a UART to generate an Interrupt Request (IRQ). Sleep mode is entered from normal mode under software control, and is exited under external command on COM 1 (any activity on COM1). The PLL will also return to its previous mode on the assertion of the IRQ by external stimulus (i.e. by asserting the nRESET discrete).

Auto Place-holder

Software Update In software update mode no navigation solution is generated. The Q20 module supports software upgrade from any serial port.

! Note: Software update will only operate at 38,400 BAUD.

Software Upgrade Mode is entered on software command or at start-up by holding the COM 1 RX pin low.

Software Upgrade Mode is exited on receipt of the appropriate software command or by resetting the module.

Software commands and protocols are detailed in the Q20 GPS Receiver Module Interface Control Document.[1]

Table 1 - Q20 Module Operating Modes

Time to switch between sleep and normal modes is less than 5 seconds.

2.8 Operation on power up

On application of power the Q20 module will perform a power-on reset and transition to the normal mode of operation.

2.9 Operation on power interrupt

The Q20 module contains a reset controller. In the condition of power interrupt or power ‘brown-out’ it will perform a reset and transition to the normal mode of operation. Reset occurs at 2.85V ±100 mV.

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2.10 Power Consumption

The Q20 power consumption can be minimised by intelligently switching between operating modes. The Q20 is able to obtain a fix much faster than conventional GPS receivers and so is ideally suited to intermittent operation.

Mode Current Consumption (mA)

Fix 145

Sleep 10

Software Update 200Max consumption during sequence

Table 2 - Q20 Module Power Consumption

2.11 Protocols

The Q20 supports several different serial protocols; these are described in the Q20 GPS Receiver Module Interface Control Document.[1]

Protocol Type Runs On

NMEA Output, ASCII, 0183, V2.1 and V2.2

COM 1, COM 2, COM 3

QinetiQ ASCII command set

Input / output, ASCII, QinetiQ proprietary

COM 1, COM 2, COM 3

Network Assist Input, QinetiQ proprietary COM 1, COM 2, COM 3

Table 3 - Q20 Module Serial Data Protocols

! Note Individual messages may be switched on / off under software control. This is on a per-module basis, i.e. a message disabled on one COM port will be disabled on both other COM ports.

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3 Performance Specification

Receiver Type 12 parallel channel C/A L 1 (1575.42 MHz)

Performance RF Reception Sensitivity -185 dBW acquisition-189 dBW tracking

Signal Acquisition

HotWarmColdReacquisition

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4 Mechanical Specification

4.1 Dimensions

RF_GND 32

TDI 23

LED 2 21

LED 1 22

LED 3 20

Reserved 19

TIMEMARK 18

FREQ OUT 17

RF_GND 29

TMS 27

TDO 26

JTAGSEL 25

TCK 24

2V8_TEST 28

RF_IN 31

RF_GND 30

1 nTRST

10 EXT CLOCK

12 Reserved

11 Reserved

13 VBATT

14 1V8_TEST

15 DIG_GND

16 VCC

5 COM 2 RX

6 COM 2 TX

7 COM 3 RX

8 COM 3 TX

9 MODE

2 nRESET

3 COM 1 RX

4 COM 1 TX

26.5 + 0.0 / -0.2 mm

22.0 + 0.0 / -0.2 mm

PCBShielding Can

24.79 ± 0.1 mm

3.22 ± 0.1 mm0.87mm

0.86mm 0.38mm

21.23 ±0.1 m

m

RF_GND 32

TDI 23

LED 2 21

LED 1 22

LED 3 20

Reserved 19

TIMEMARK 18

FREQ OUT 17

RF_GND 29

TMS 27

TDO 26

JTAGSEL 25

TCK 24

2V8_TEST 28

RF_IN 31

RF_GND 30

1 nTRST

10 EXT CLOCK

12 Reserved

11 Reserved

13 VBATT

14 1V8_TEST

15 DIG_GND

16 VCC

5 COM 2 RX

6 COM 2 TX

7 COM 3 RX

8 COM 3 TX

9 MODE

2 nRESET

3 COM 1 RX

4 COM 1 TX

26.5 + 0.0 / -0.2 mm

22.0 + 0.0 / -0.2 mm

PCBShielding Can

24.79 ± 0.1 mm

3.22 ± 0.1 mm0.87mm

0.86mm 0.38mm

21.23 ±0.1 m

m

Figure 3 - Q20 Module Mechanical Outline

4.2 Specification

Parameter Specification Tolerance UnitLength 22.0 +0.0 / -0.2 mm

Width 26.5 +0.0 / -0.2 mm

Thickness 3.22 ±0.1 mm

Pitch connector pad 1.35 mm

Width connector pad 0.88 mm

Weight 2.5 grams

Table 5 - Q20 Module Mechanical Specification

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4.3 PCB Outline

Figure 4 – Q20 PCB Outline

4.4 Recommended Layout Footprint

Figure 5 – Q20 Recommended PCB Layout

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4.5 Electrical Connections

Pin Number Name Type Description1 nTRST JTAG Reset2 nRESET External Reset3 COM 1 RX I COM 1 Serial Data Input4 COM 1 TX O COM 1 Serial Data Output5 COM 2 RX I COM 2 Serial Data Input6 COM 2 TX O COM 2 Serial Data Output7 COM 3 RX I COM 3 Serial Data Input8 COM 3 TX O COM 3 Serial Data Output9 MODE Discrete Reserved: HD Software Only

10 EXTERNAL CLOCK I Build dependant11 Reserved Reserved: Tie to Vcc with 3K3 resistor12 Reserved Reserved: Tie to Vcc with 3K3 resistor13 VBATT PWR +1.8V to +5.5V Backup power for RTC14 1V8_Test PWR +1.8V DC Digital Power Test Point15 DIG_GND PWR Digital Ground16 VCC PWR +3.15V Power Input17 FREQ OUT O Reserved: Timing Software Only18 TIMEMARK O 1 PPS Output19 Reserved DO NOT USE20 LED 3 O GPS status LED 321 LED 2 O GPS status LED 222 LED 1 O GPS status LED 123 TDI JTAG Data In24 TCK JTAG Clock25 JTAGSEL JTAG Select26 TDO JTAG Data Out27 TMS JTAG Mode Select28 2V8_Test PWR +2.8V DC Digital Power Test Point29 RF_GND PWR RF Ground30 RF_GND PWR RF Ground31 RF_IN PWR RF Input32 RF_GND PWR RF Ground

Table 6 - Q20 Module Pin Allocations

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5 Electrical Specification

5.1 Absolute Maximum Ratings

Parameter Symbol Min Max Units

Power Supply Voltage VCC -0.3 3.6 V

Battery Backup Voltage VBATT -0.3 7.0 V

Input Pin Voltage VIN -0.3 5.0 V

Table 7 - Q20 Module Absolute Maximum Ratings

! Warning Stressing the device beyond the ‘Absolute Maximum Ratings’ may cause permanent damage. Q20 is not protected against over-voltage or reversed voltages. Voltage spikes exceeding the power supply voltage specification given in the table above must be reduced by using appropriate protection diodes.

5.2 Operating Conditions

Parameter Symbol Min Max Units

Power Supply Voltage VCC 3.0 3.6 V

Power Supply Voltage Ripple VCCPP 70 mV

Backup Battery Voltage VBATT 1.8 VCC V

Input Pin Voltage VIN 0 VCC V

Input Pin Low Voltage VIN_LOW 0.15 V

Input Pin High Voltage VIN_HIGH VCC - 0.4 V

Output Pin Low Voltage VOUT_LOW 0.4 V

Output Pin High Voltage VOUT_LOW 0.67 x VCC V

Table 8 - Q20 Module Operating Conditions

! Warning The VBATT supply shall be constrained to be no higher than VCC. If VBATT exceeds VCC, 50μA – 150μA current will continually be drained from the VBATT supply. Additionally, there is a risk that I2C bus will not operate correctly and that custom settings (e.g. Baud Rate) will be lost.

! Warning Operation beyond the ‘Operating Conditions’ is not recommended and extended exposure beyond the ‘Operating Conditions’ may affect device reliability.

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5.3 Q20 Module Pin I/O Details

Pin Name O/P (mA)

Open Collector

Schmitt I/P

Bias FTYP 5V Tolerant

COMx TX [0:2] 4 No Out Only None 230k -

COMx RX [0:2] In Only - No Up - Yes

nRESET In Only - Yes Up - Yes

TIMEMARK 6 No No None 1M Yes

nTRST In Only - No Up - Yes

TMS In Only - No Up - Yes

TCK In Only - No Up - Yes

TDI In Only - No Up - Yes

TDO 6 No Out Only Up 1M Yes

JTAGSEL In Only - No Up - Yes

EXT CLOCK In Only - - - 20M No

Table 9 - Q20 Module Pin I/O Details

5.4 RF Input Parameters

Parameter Frequency Typical

@ +25°C

-40°C to +80°C Units

Insertion loss 1573.42 – 1577.42 1.25 1.5 max dB

824 – 829 67.0 50.0 min dB

1850 – 1910 53.0 45.0 min dB

1710 – 1785 24.0 10.0 min dB

Input filter

attenuation

2400 - 2484 50.0 20.0 min dB

Max power

in-band

1573.42 – 1577.42 -90.0 -90.0 dBm

Table 10 – Q20 Module RF Input Parameters

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6 Interfaces6.1 Outline Description

6.1.1 Serial Interface

Three UARTs are provided in the Q20 and are of the 16C550 type with 16 deep FIFOs on their receive and transmit buffers. They support fully programmable, individually selectable, baud rates up to 230,400 baud.

The UARTs provide:• Network connectivity (e.g. network assist)• User environment (application. software)• Developer access

All UARTs support direct connection to an external IrDA transmitter/receiver. Although the UARTs support a variable number of data bits, only 8 data bit transfers are required.

Because the UARTs only have 16 deep FIFOs, interrupt response can be an issue at high baud rates. Each UART has 5 interrupt outputs that are combined to form 3 interrupt sources for the interrupt controller. An interrupt is generated when either a character is received or the FIFO remains unemptied for the timeout period; when the transmit buffer can except more data; or when modem status changes or errors occur. All of the individual causes of interrupt in a UART can be masked within that UART.

Outputs from the UARTs are non-inverted, and at CMOS level. In quiescent state the UART transmit is held to the marking (HIGH) level. The UART receive is biased HIGH.

Figure 6 - Q20 Module Transmit Timing

6.1.2 Reserved

Reserved for future firmware upgrade.

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6.2 Detailed Pin Description

6.2.1 Pin 1 nTRST

JTAG active low reset. Input only (biased high), 5 V tolerant

6.2.2 Pin 2 nRESET

External reset – active low with Schmitt trigger input (input is triggered on high-to-low transition). This is the hard reset input and is used to completely reset the Q20 module. It is recommended that when asserted, nRESET is held low for at least 1ms.A hard reset occurs when the nRESET signal is asserted low or at power on. During a hard reset the following actions happen:

• the Q20 is set to run from the PLLCLK input• the PLL is set to its default frequency• GPIO functions are set to default• the RTC counter is reset

6.2.3 Pin 3 COM 1 RX

COM 1 serial port - receive signal. Input only (biased high), 5 V tolerant

6.2.4 Pin 4 COM 1 TX

COM 1 serial port - transmit signal. Output only, unbiased push-pull outputIOUT(MAX) = 4 mA









6.2.9 Pin 9 MODE

Reserved for High Dynamic (HD) software

6.2.10 Pin 10 EXT CLOCK

External clock input - available as a hardware option instead of the internal TCXO

FIN = 20 MHz. DC coupled clipped sine wave, 0.8V Min / 1.2V Typ / 2.2V Max

6.2.11 Pin 11 Reserved

Reserved for future firmware upgrade. Tie to Vcc with 3K3 resistor


Reserved for future firmware upgrade. Tie to Vcc with 3K3 resistor

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6.2.13 Pin 13 VBATT

Battery backup input for Real Time ClockVBATTMAX = Vcc

VBATTMIN = 1V8

IOPERATE = 2.8µA (typical @ Vcc = 3V15)

6.2.14 Pin 14 1V8_Test

Test point for the 1V8 power for the digital baseband circuitry - derived on-board the Q20 module. This can be used as a low current output at 1V8.

IOUTMAX = 25mA

6.2.15 Pin 15 DIG_GND

Electrical ground for the baseband digital circuitry.

6.2.16 Pin 16 VCC

Primary power for the Q20 module. All input power (except battery backup for the real time clock – VBATT) is derived from this input.

6.2.17 Pin 17 FREQ OUT

Reserved for timing software

6.2.18 Pin 18 TIMEMARK

1Pulse Per Second, rising edge aligned to UTC second rollover, pulse length 100 μs.


Reserved for future firmware upgrade

6.2.20 Pin 20 LED 3

LED 3 is configured as a GPS status LED output drive which pulses to indicate the number of satellites tracked for which valid ephemeris data is available

6.2.21 Pin 21 LED 2

LED 2 is configured as a GPS status LED output drive which pulses to indicate the number of satellites tracked for which valid ephemeris data is not available

6.2.22 Pin 22 LED 1

LED 1 is configured as a GPS status LED output drive which pulses when power is applied, but no navigation solution is available

6.2.23 Pin 23 TDI

JTAG data in. Input only (biased high), 5 V tolerant

6.2.24 Pin 24 TCK

JTAG clock. Input only (biased high), 5 V tolerant

6.2.25 Pin 25 JTAGSEL

JTAG select. Input only (biased high), 5 V tolerant

6.2.26 Pin 26 TDO

JTAG data out. Output only (biased high), 5 V tolerantIOUT(MAX) = 6 mA

6.2.27 Pin 27 TMS

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JTAG mode select. Input only (biased high), 5 V tolerant

6.2.28 Pin 28 2V8_Test

Test point for the 2V8 power for the RF circuitry - derived on-board the Q20 module.

! Note: TEST ONLY. Do not use as a 2V8 source6.2.29 Pin 29 RF_GND

Electrical ground for the RF front end circuitry

6.2.30 Pin 30 RF_GND


6.2.31 Pin 31 RF_IN

RF input from 50-ohm impedance antenna. This input is AC coupled (see Appendix A -Q20 module circuit diagram)

! Note: The provision of an electrical supply to power an external antenna with an active low noise amplifier is not supported on the Q20 module.

6.2.32 Pin 32 RF_GND


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7 References[1] QINETIQ/FST/ICD035773/2.6, ‘Q20 GPS Receiver Module Interface Control

Document’, November 2004.

8 Abbreviations

1 PPS One Pulse Per SecondAGC Automatic Gain ControlAHB ARM™ High-speed BusAPB ARM™ Peripheral BusA-to-D Analogue to DigitalC/A-code GPS Coarse/Acquisition-codedBi decibel isotropicdBW decibel WattsEEPROM Electrically Erasable Programmable Read-Only MemoryESD Electro-Static DischargeFFT Fast Fourier TransformFIFO First In First OutGNSS Global Navigation Satellite SystemGPIO General Purpose Input OutputGPS Global Positioning SystemHz Hertz (cycles per second)ICD Interface Control DocumentIF Intermediate FrequencyIRQ Interrupt RequestL1 Link 1 frequency (1575.42 MHz)LED Light Emitting DiodeLNA Low Noise AmplifierMHz Mega Hertz (106 cycles per second)mW Milli Watt (10-3 Watt)NCO Numerically Controlled OscillatorNMEA National Marine Electronics AssociationPCB Printed Circuit BoardPDOP Position Dilution Of PrecisionPLL Phase Lock Loopppm parts per millionPRN Pseudo Random NoisePVT Position, Velocity, TimeRF Radio FrequencySiGe Silicon-GermaniumSPI Serial Peripheral InterfaceTBC To Be ConfirmedTCXO Temperature Compensated Crystal OscillatorUTC Universal Time Co-ordinated

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9 GlossaryAcquisition The initial process of aligning a spread spectrum receiver's

local pseudo random code sequence with the corresponding sequence received from the transmitter

C/A-code Coarse/Acquisition-code. A unique (per satellite) pseudo-random code used to modulate the GPS carrier. The C/A-code is 1023 bits long and repeats every millisecond (1.023 MHz chipping rate). C/A-code is currently transmitted only on the L1 frequency of 1575.42 MHz.

Cold start A Cold Start is defined as starting the acquisition process using no previous GPS almanac, ephemeris, and degraded time and position data.

Fix The generation of a single GPS based position solution. This may include the time to acquire sufficient satellite signals (usually four) to calculate a position solution, and to demodulate ephemeris data from the navigation data stream.

Hot start A Hot Start is defined as starting the acquisition process using a valid almanac, valid ephemeris, position to better than 1 km accuracy and time to better than 1 ms accuracy.

Sensitivity The smallest RF signal received that can be used to provide a useful output. In the case of a GPS receiver this is the lowest signal level that can be used to contribute to a position solution.

Signal to Noise The dimensionless ratio of bit energy to noise plus interference energy accumulated over the period of one bit.

Tracking Maintaining the alignment of the incoming GPS satellite signal with the receiver’s replica code.

Warm start A Warm Start is defined as starting the acquisition process using a valid almanac, position better than 10 km accuracy and time better than 1s accuracy.

QinetiQ Proprietary


A Q20 Module Minimum Application Circuit

A.1 Passive Antenna

Figure 7: Minimum Application Circuit – Passive Antenna

32 RF_GND

23 TDI

21 LED 222 LED 1

20 LED 319 Reserved 18 TIMEMARK17 FREQ OUT

29 RF_GND

27 TMS26 TDO25 JTAGSEL24 TCK

28 2V8_TEST

31 RF_IN30 RF_GND

nTRST 1

EXT CLOCK 10

Reserved 12Reserved 11

VBATT 131V8_TEST 14DIG_GND 15

VCC 16

COM 2 RX 5COM 2 TX 6COM 3 RX 7COM 3 TX 8

MODE 9

nRESET 2COM 1 RX 3COM 1 TX 4

VCC

RS232LevelShifter

BackupBattery

Passive Antenna

(5mm max from Q20 module)

3K3

3K3

32 RF_GND

23 TDI

21 LED 222 LED 1


29 RF_GND


28 2V8_TEST

31 RF_IN30 RF_GND

nTRST 1

EXT CLOCK 10



VCC 16


MODE 9


VCC

RS232LevelShifter

BackupBattery

Passive Antenna

(5mm max from Q20 module)

3K3

3K3

QinetiQ Proprietary


A.2 Active Antenna

Figure 8: Minimum Application Circuit – Active Antenna

32 RF_GND

23 TDI

21 LED 222 LED 1


29 RF_GND


28 2V8_TEST

31 RF_IN30 RF_GND

nTRST 1

EXT CLOCK 10



VCC 16


MODE 9


VCC

RS232LevelShifter

BackupBattery

Active Antenna

VANT

Fuse 50mA

LANT47NCANT

1N0

3K3

3K3

32 RF_GND

23 TDI

21 LED 222 LED 1


29 RF_GND


28 2V8_TEST

31 RF_IN30 RF_GND

nTRST 1

EXT CLOCK 10



VCC 16


MODE 9


VCC

RS232LevelShifter

BackupBattery

Active Antenna

VANT

Fuse 50mA

LANT47NCANT

1N0

3K3

3K3

qinetiq q20 high sensitivity gps receiver · 2019. 10. 12. · 6.2.28 pin 28 2v8_test 21 6.2.29 pin...

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