Punchthrough effects on the electrostatic discharge robustness of ultrathin siliconfilms on insulator devicesJam-Wem Lee and Howard Tang

Citation: Applied Physics Letters 89, 103508 (2006); doi: 10.1063/1.2345377 View online: http://dx.doi.org/10.1063/1.2345377 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/89/10?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Adaptation of the pseudo-metal–oxide–semiconductor field effect transistor technique to ultrathin silicon–on-insulator wafers characterization: Improved set-up, measurement procedure, parameter extraction, and modeling J. Appl. Phys. 114, 164502 (2013); 10.1063/1.4826631 Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gatemetal-oxide-semiconductor field-effect transistor (MOSFET) J. Appl. Phys. 114, 014507 (2013); 10.1063/1.4812735 A revised reverse gated-diode technique for determining generation parameters in thin-film silicon-on-insulatordevices and its application at high temperatures J. Appl. Phys. 97, 093718 (2005); 10.1063/1.1893211 Carrier scattering induced by thickness fluctuation of silicon-on-insulator film in ultrathin-bodymetal–oxide–semiconductor field-effect transistors Appl. Phys. Lett. 82, 2916 (2003); 10.1063/1.1571227 Leakage current models of thin film silicon-on-insulator devices Appl. Phys. Lett. 72, 1199 (1998); 10.1063/1.121012

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APPLIED PHYSICS LETTERS 89, 103508 �2006�

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Punchthrough effects on the electrostatic discharge robustness of ultrathinsilicon films on insulator devices

Jam-Wem Leea�

Department of Nano Device Technology, National Nano Device Laboratories, Hsinchu 300, Taiwan

Howard TangUnited Microelectronic Corporation, Hsinchu 300, Taiwan

�Received 13 March 2006; accepted 12 July 2006; published online 6 September 2006�

Physical mechanisms that dominate the electrostatic discharge �ESD� robustness ofsilicon-on-insulator �SOI� devices are theoretically and experimentally investigated here. Theauthors experimentally find that the ESD robustness depends strongly on the device geometrycorrelated turn on mechanism. Moreover, the punchthrough mechanism is theoreticallydemonstrated to be the unsuitable turn on mechanism that causes a nonuniform current distributionand a low ESD strength. The punchthrough mechanism, according to their theoretical analysis, willoccur in scaled down structure and reduce the benefits arising from sizing down. Therefore,optimization of a device structure is necessary to prevent nanoscaled SOI devices from thepunchthrough induced ESD robustness degradation. © 2006 American Institute of Physics.�DOI: 10.1063/1.2345377�

Silicon-on-insulator �SOI� technology is a promising ap-proach to suppress latchup, junction capacitance, andnoise.1–4 Accordingly, this technology is attractive for thecircuit applications involving radio frequencies, high speed,and low power. Unfortunately, SOI technology has long suf-fered from immensely low electrostatic discharge �ESD� ro-bustness, which is particularly critical for ultrathin-body5 de-vices. Many circuitry approaches6–9 have been proposed toenhance the ESD strength of ultrathin-body SOI devices. Thesuccess of those methodologies is highly correlated to thefunctionality of ultrathin-body SOI devices; however, fewstudies have been aimed to optimize device structure throughproviding a suitable protection mechanism.

ESD is a high-current but short-time stress condition10,11

that causes parasitic bipolar junction transistors �BJTs� toturn on. During the ESD stressing, a parasitic BJT can beturned on through two major mechanisms: junction break-down and punchthrough breakdown. Punchthrough break-down is a phenomenon that occurs whenever the source anddrain depletion regions come into contact. The mechanism ishighly sensitive to the doping distribution; thus, it will createlocal high-density current paths and burn out those routes.On the other hand, junction breakdown turns on the parasiticBJT with less dependent on the degree of doping. It is evenbetter that the base resistance of SOI structure is naturallyhigh; the junction prebreakdown current may make theemitter-to-base barrier height low enough to activate theparasitic BJT entirely. In summary, junction breakdownmechanism is more suitable turn on mechanism for ESDprotection. Therefore, we performed both experimental andsimulated12,13 analyses to quantitatively compare the differ-ences in ESD robustness that arise from these two physicalmechanisms. We found that the punchthrough process is nota good protection mechanism because it severely degradesthe strength of the ESD protection.

a�

Electronic mail: jamwem.ee85g@nctu.edu.tw

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Punchthrough and junction breakdowns were investi-gated simultaneously by using two kinds of SOI wafers forthe fabrication of the test devices. The main concept behindthe experimental design was based on the well-known phe-nomenon that the channel boron concentration is greatly re-duced as a result of segregation effects. Because the channelboron concentration in a thinner silicon sample is relativelylow, punchthrough breakdown is more likely to occur. TheSOI thicknesses of the two samples were 140 and 90 nm,respectively. We used 90 nm complementory metal-oxidesemiconductor technology for the fabrication of devices thathad minimum feature sizes of 90 nm. The cross section viewof the SOI device is shown in Fig. 1; additionally, the gateoxide thickness of each device was 1.2 nm, and the depth ofthe source/drain extensions was 90 nm.

The ESD robustness was characterized using a transmis-sion line pulse.14 To determine the simulated ESD character-istics, the Poisson, drift diffusion, impact ionization, andband-to-band tunneling equations were solved using an ISE

simulation platform.In investigating the physical mechanisms that dominate

the SOI device operation under ESD stressing, several two-dimensional semiconductor equations are solved by TCAD

simulator. In simulation, the following equation �1� is thePoisson equation that is used for potential, electric field, andcarrier concentration calculation; moreover, the depletion re-gions are also simulated from the function to determine the

FIG. 1. Cross section view of the SOI device.

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103508-2 J.-W. Lee and H. Tang Appl. Phys. Lett. 89, 103508 �2006�

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punchthrough. By coupling Poisson equation to drift-diffusion equation listed as Eq. �2�, the electron and holecurrent density will then be obtained. In addition to thosetwo equations, impact ionization function is necessary forjunction breakdown simulation. The hydrodynamic equation�3� is finally solved to have the temperature distribution overthe entire device structure.

In poisson equation,

�� · �� = − q�p − n + ND − NA� . �1�

In Eq. �1�, � is the electrical permittivity, q is the elementaryelectronic charge, n and p are the electron and hole densities,ND is the number of ionized donors, and NA is the number ofionized acceptors.

In drift-diffusion equations,

Jn� = − nq�n��n, Jp

� = − pq�p��p, �2�

where �n and �p are the electron and hole mobilities; more-over, �n and �p are the electron and hole quasi-Fermi poten-tials, respectively.

In hydrodynamic equations,

J�n = − q�n�n�Ec + kBTn � n + fntdkBn�Tn

− 1.5kBTn� ln me�

and

J�p = − q�p�p � Ev + kBTp�p + fptdkBp�Tp

− 1.5kBTp� ln mh� . �3�

In the above equations, Ec and Ev are the conduction andvalence band energies. The first term takes into account thecontribution due to the spatial variations of electrostatic po-tential, electron affinity, and the band gap. The three remain-ing terms take into account the contribution due to the gra-dient of concentration, the carrier temperature gradients, andthe spatial variation of the effective masses me and mh. Ad-ditionally, the kB, Tn, and Tp are the Boltzmann constant,electron temperature, and hole temperature, respectively. fn

td

and fptd are the simulation parameters that are simply equal to

0 in this work.Figures 2�a� and 2�b� present the current density plots of

both the �a� thick- and �b� thin-channel film devices. To ob-tain the consistent simulation results, we carefully calibratedthe simulated structures with the experimental data. FromFigs. 2�a� and 1�b� we observe that the current distributionsof the two structures were significantly different. We inferthat the thinner channel had a relatively high-density currentpath near the silicon-buried-oxide interface. On the otherhand, the thicker channel had its current uniformly distrib-uted over the entire film region. The results of the simula-tions are highly consistent with our assumption that punch-through breakdown should dominate over junctionbreakdown for such thin-channel film devices. For the factthat the punchthrough occurs whenever the depletion regionsof both source and drain come to contact together, inspec-tions of the depletion regions conform that the depletion re-gions of the thinner one are merged into one path. The path ismarked in Fig. 2�b� that presents a similar region with high-current density route. This situation arose due to the fact thatthe boron doping concentrations between the source anddrain extensions were sufficiently low to cause the punch-ticle is copyrighted as indicated in the article. Reuse of AIP content is

through breakdown to occur in the short-channel �gate length

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�0.15 �m� devices. Whenever the punchthrough processoccurs, a local high-density current path, similar to that dis-played in Fig. 2�b�, is soon to be built and burned out.

Figures 3�a� and 3�b� present the ESD robustness asmeasured by using TLP. Figure 3�a� indicates that the ESDstrength of the thick-channel film devices depended onlyslightly on the gate length. This result is consistent with ourtheoretical analysis suggesting that the nature of the junctionbreakdown will turn on the entire device area. Under thiscondition, the ESD robustness of SOI devices is dominatedby the ability to dissipate heat; consequently, we observed aweak dependence on the gate length. The ESD robustness inFig. 3�b� correlates strongly with the gate length; the protec-tion mechanism failed abruptly whenever the gate length wasbelow 0.15 �m. We believe that this significant feature re-sults from our previous simulation finding that the punch-through process will occur for gate lengths shorter than0.15 �m. In other words, junction breakdown will be thedominant protection mechanism and a stable ESD will beobtained when the gate length is greater than 0.15 �m. Incontrast, when the gate length is below 0.15 �m, punch-through will occur to create a local high-density current pathto burn out the devices immediately. Those two zones arealso identified in Fig. 3�b� to make a more clear correlationbetween ESD robustness and turn on mechanisms. We note

FIG. 2. TCAD-simulated current density distributions of the �a� thick- and �b�thin-channel film SOI metal-oxide-semiconductor field-effect transistor�MOSFET� devices.

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that the steady ESD robustness investigated on the thin-7 Oct 2014 08:54:30

103508-3 J.-W. Lee and H. Tang Appl. Phys. Lett. 89, 103508 �2006�

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channel film devices having gate lengths longer than0.15 �m was slightly worse than that of the thick one. Thisresult was caused simply by the fact that the thinner-channelfilm device exhibited higher densities of both current andheat; thus, the degradation of the ESD strength is predictable.

In summary, it is well known that the scaling down ofboth the gate length and silicon film thickness plays the mostcrucial role in integration circuit evolution. Unfortunately,according to the experimental results, sizing down the SOIdevice without carefully adjusting the turn on mechanismwill cause a failure in ESD protection. The problem ismainly caused by the punchthrough effect which has a higheroccurring possibility for the SOI device with thinner siliconfilm. Consequently, an optimization process is necessary toavoid the risk from punchthrough induced ESD problem.

In this study, we performed both experimental and theo-retical analyses to investigate whenever the ESD robustness

FIG. 3. ESD robustness plotted against the gate length of the �a� thick- and�b� thin-channel film SOI MOSFET devices.

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is affected by different protection mechanisms. We concludethat the punchthrough-dominated discharging process wasextremely weak and caused the thin-channel devices to failwhenever the channel length was shorter than 0.15 �m. Onthe other hand, junction breakdown led to a channel-length-independent ESD strength; those values were slightly higherthan 3 mA/�m for the thick-channel devices and slightlylower than 3 mA/�m for the thin ones. We conclude that theprotection mechanism is the most important factor that pre-vents a circuit from undergoing ESD damage. Furthermore,the protection mechanism is determined by the doping pro-files and, thus, careful optimization of device structures isnecessary not only for improved circuitry performance butalso for ESD robustness.

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