Jeroen Ottens

Metrology in the context of holistic Lithography

Public

Product System Engineer YieldStar, ASML

Lithography is at the heart of chip manufacturing25.April.2017

Public

Slide 2

Repeat 30 to 40 times to build 3 dimensional structure

Overlay and CD-Uniformity (CDU) are critical for device performance

20 November 2017

Public

Slide 3

Rule-of-thumb:

OV 30 % of CD

CDU 10 % of CD

OVCritical Dimension

(CD)Today’s devices: CD 16 nm

OV < 5 nm

CDU < 1.5 nm

Holistic Lithography Concept

Scanner aspects

Metrology aspects

- YieldStar

- Computational Metrology

- Pattern Fidelity Monitoring

Conclusions

25.Apirl.2017

Slide 4

Publicl

ASML Holistic Lithography approach seeks to

maximize patterning process performance and control

Full chip process window detection

Process Window Enhancement

Process Window Control

Lithography scanner with advanced capability (Imaging, overlay and focus)

Computational Lithography Metrology

1

3 2

25.April.2017

Public

Slide 5

1

Scanner aspects

25.April.2017Slide 6

Public

40 years projection lithographydriving performance improvements 3 orders of magnitude*

Slide 7

“Innocence”

UnderstandingModels and setup

Process controlMetrology feedback

Mark design and sampling

* Use overlay as example based on SPIE publications 1973 - 2015

Micralign

NXT:1950i

Holistic approachHigh order corrections

Integrated metrology

Computational litho

Design for control

Public25.April.2017

25.April. 2017

Slide 8

Public

ASML Scanners at the core of patterning control capability

ASML scanners measure 100% of the wafers ASML scanners knobs control every die

100% of the wafers

are measuredWafers processed

field by field

Metrology aspects

25.April. 2017

Slide 9

Public

ASML Holistic Lithography approach seeks to

maximize patterning process performance and control

Full chip process window detection

Process Window Enhancement

Process Window Control

Lithography scanner with advanced capability (Imaging, overlay and focus)

Computational Lithography Metrology

1

3 2

25.April. 2017

Public

Slide 10

Measurem

ent

Signal type Target size

( µm2 )

Primary application

Overlay

Pupil 40x160 Monitor wafer

Dark field image 10x10 On Product

Focus

Pupil 40x40 Monitor wafer

Dark field image 10x10 On Product

CD Pupil 40x40 – 5x5 Monitor & On Product

25.April. 2017

Slide 11

Publicl

YieldStar Optical Scatterometry SystemOverlay, Focus and CD measurement capability

YieldStar

Stand alone

Integrated

Applying scanner corrections needs holistic approach supporting* the setup & optimization of Overlay, Focus, Dose

Ramp Process development HVM

Optimal correction

models and sampling

Static process setup

Overlay and Imaging

On-Product Performance

3

Reduce Lot-lot and

Wafer-wafer variation

3Dynamic process

setup

wafe

r 2 w

afe

r

lot 2 lot

machine 2 machine

Reduce Impact of Variations

4Process control &

monitoring

Excursion control thru

scanner, metro &

process KPI monitoring

Maintain Performance

5

Matched

machine overlay

on all layouts

Scanner

Performance1

1.7nm

* Supported with LithoInsight (LIS) software and the off-tool Litho Computation Platform (LCP)

Optimal metrology

accuracy, precision

and throughput

Metrology setup

YieldStar and Smash

Metrology

mDBO

mDBF

SMASH XY

2

CD

Public

Slide 13

Improved Overlay performance with minimized samplingLogic example HOPC +CPE control

~ 2 month ~ 1 month

LiS control

Enabled

On

-pro

du

ct o

ve

rla

y [m

3s]]

LiS control

Saturated

POR control strategy :

POR Sampling 557 pt /wfr ; 1wfr/ck

Correction Model : HOPC3txty+iHOPC+Dynamic CPE

LiS control strategy :

SSO Sampling 200 pt/wfr ; 1wfr/ck (64% less than POR)

LiS Estimation Model : 5th order

Correction Model : Same as POR model

Product/layer : Logic/FEOL

Lot exposure via dedicate chuck on NXT:1970Ci

Monitoring trend via POR layout

Overlay measurement by multiple YS S-250

10 hours

Performance measured

on POR layout

Public

Slide 14

25.April. 2017

Slide 15

Public

Metrology Sampling Density RoadmapThe number of metrology points needed is higher than physically practical !

Computational metrologyPublic

Product wafer

Emu

late

d fi

nge

rpri

nt

BMMO

corr

ect

Ap

ply

measured wafer

Scanner with integrated YieldStar Stand-alone YieldStar

Scanner

interface

ADI

metrologyAEI

metrology

Focus

& CD

OVL

Comp. Metro

Focus ADI

OVL on device

Etcher

BMMO

residuals

YieldStarARM-CD/OVL

OVL ADI

ARM (LIS est.)(Waver level) corrections Comp. Metro

YS-IM YS-IDM

CD on device

SPIE 2017: W. Tel, Efficient Hybrid metrology for focus, CD, and overlay

Measured OVL

Computational Overlay for LELE case Evaluation after 2nd litho step

Computational Overlay =

etch+leveling+uDBO Delta OVL map

μDBO Level sensor etcher monitoring80 pts

200 pts

SPIE 2017: W. Tel, Efficient Hybrid metrology for focus, CD, and overlay

PublicSlide 17

<Date>

Slide 18

Publicl

Proof of principle CD

SPIE 2017: W. Tel, Efficient Hybrid metrology for focus, CD, and overlay

<Date>

Slide 19

Confidential

25.April. 2017

Slide 19

Publicl

28 February 2017

Public

Slide 20

Advanced in-production hotspot prediction and monitoring with micro-topography, 10145-33, SPIE Advanced Lithography, San Jose, CA, USA, Feb 28, 2017

HVM Defect patterning defect predictions on 100% of wafer

Simulated PW

Predicted Defect Map

Best focus mapDepth of focus

map

FEM per

HotSpot

Verification sampling plan

Hybrid process modulation map

+

On Wafer Defect Prediction

On Wafer Defect Observation

Validation

Note that (in this

experiment) validation

can only be done at the

same sampling scale as

verification plan

25.April. 2017

28 February 2017

Public

Slide 21

Advanced in-production hotspot prediction and monitoring with micro-topography, 10145-33, SPIE Advanced Lithography, San Jose, CA, USA, Feb 28, 2017

Patterning Fidelity Monitoring verifies the predicted defects on

wafer using E-beam CD metrology tools

HDFM focus map Defect prediction

7569 73

25 31 270

20

40

60

80

100

M3DR4 AI60L1R3_AI90L1R9 LMC19

Rat

e (

%)

Established good correlation between dense focus map and measured pattern defects

Defect observation

Capture rate: Percentage of successfully

(verified) predicted defect locations

25.April. 2017

Summary

- The large number of “knobs” on the scanner allows correction for

process variations both Intra- and Inter-field.

- The metrology required to feed control loops for high frequency spatial

and temporal process variations requires computational methods to

create per-wafer high density metrology information

- Combination of Scanner model, multiple metrology sources and

computational modeling allows for defect prediction and in turn scanner

model optimization.

25.April.2017

Slide 22

Publicl

Thank you !

25.April. 2017

Slide 23

Public

I would like to recognize the following ASML colleagues for their contributions:

Wim Tel, Stefan Hunsche, Marinus Jochemsen, Leon Verstappen,

Arie den Boef, Jan Mulkens, Martin Ebert

Overlay 3 orders of magnitude down¹

Overlay correctables 4 orders of magnitude up

The future: extending Holistic approachHigh order corrections

Process robust metrology, broad wavelength, polarization

and multiple orders using marker reconstruction,

Integrated metrology

Computational litho and metrology optimization

Dense on product sampling enabling litho control; lot-lot,

wafer-wafer, on product

Reference : Key note Metrology conference 2016 . M vd Brink

#U

se

r s

ele

cta

ble

lit

ho

co

rre

cti

on

s

Public

Slide 24

Improved Overlay performance for Logic HOPC + CPELogic example HOPC +CPE control : 23% average overlay improvement,64% less samples

~ 2 month ~ 1 month

LiS control

Enabled

On

-pro

du

ct o

ve

rla

y [m

3s]]

LiS control

Saturated

POR control strategy :

POR Sampling 557 pt /wfr ; 1wfr/ck

Correction Model : HOPC3txty+iHOPC+Dynamic CPE

LiS control strategy :

SSO Sampling 200 pt/wfr ; 1wfr/ck (64% less than POR)

LiS Estimation Model : 5th order

Correction Model : Same as POR model

Product/layer : Logic/FEOL

Lot exposure via dedicate chuck on NXT:1970Ci

Monitoring trend via POR layout

Overlay measurement by multiple YS S-250

10 hours

Performance measured

on POR layout

Public

Slide 25

<Date>

Slide 27

Confidential

Proof of principle for Focus

Level Sensor: measures wafer height map h(x,y)

20 November 2017

Public

Slide 28Requirements:

1. Accuracy: nm-range

2. Available time: few seconds

3. Resolution: 22 mm2

Concept: optical triangulation

grating (pitch P)grating

detector

Wafer stage

wafer

Light

source

sin2

P

h

detector

response

measured

height

Height variations are caused by:

1. Wafer thickness variations

2. Layer thickness variations

3. Deformation (warp) due to processing

Image

rotation

prisms

+90

-1 +1

(+1,-1)

(+1,-1)

detector

wafer

laser

-90

Wafer stage X

P

XAA 122 4cos

X1X0 X2

Solution: Interferometric alignment sensor (“SMASH”):measures the position of any target with 180 rotation symmetry

20 November 2017

Public

Slide 29

1je

A1-je

A

X1

X0

PX

4

111

P

X11 2

P

X11 2

1--1 is measured with a

self-referencing interferometer

<Date>

Slide 30

Confidential

Level Sensor and Alignment run in parallel with wafer exposure

20 November 2017

Public

Slide 31

Overlay [nm]55 WPH 125 WPH 185 WPH145 WPH

NXE:3300B

NXE:3350B

NXE:next

High NA

Slide 32

Public

EUV extension roadmap

NXE:3400B2017

2015

2013

introduction

products under study

7

3.5

3

<3

<2

SPIE 2017

More on high-NA in talk of Alberto Pirati: 10143-12