protoflex: fpga-accelerated instrumentation • software monitoring/analysis – e.g. debugging,...

Computer Architecture Lab at

PROTOFLEX:

FPGA-Accelerated Instrumentation

Michael K. Papamichael, Eric S. Chung,James C. Hoe, Babak Falsafi, Ken Mai

[email protected], {echung, jhoe, babak, kenmai}@ece.cmu.edu

PROTOFLEX

Our work in this area has been supported in part by NSF, IBM, Intel, and Xilinx.

19-Aug-2008

The Simulation Bottleneck

• Performance Simulation via Simulation Sampling– perf. measurements by sampling small segments of execution

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Execution

Detailed Warm-up (cycle-accurate simulation)

Measurement (cycle-accurate simulation)

Short &Parallelizable

Long & NOT Parallelizable

!Checkpoints (i.e. system state snapshots )

Functional Warming (functional simulation)

• Speed of cycle-accurate simulator inconsequential

• Functional Warming is the Real Bottleneck

FunctionalCMP Cache Model

Functional Branch Predictor Model

Faster Simulation w/ FPGAs

• Functional Warming requires– Full-system functional simulator (e.g. Simics)

– Instrumentation (e.g. functional cache model)

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BlueSPARC(16-cpu)

Instrumented HW Simulator Fast Functional Warming

SW-based HW-based

SW HW

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Simics(16-cpu)



HW vs. SW Simulation Performance

• Functional Warming requires– Full-system functional simulator (e.g. Simics)

– Instrumentation (e.g. functional cache model)

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BlueSPARCSimics

SW-based HW-based

SW HW

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WITH Instrumentation Speedup: 37x


Outline

• BlueSPARC Simulator (1-slide review)

• FPGA-Accelerated Instrumentation– CMP Cache Simulator

– Branch Predictor Simulator

• Design Experiences & Future Work

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BlueSPARC



Outline





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BlueSPARC

BlueSPARC Simulator

• Full-system HW-based Functional Simulator– Models 16-cpu UltraSPARC III server

– Can boot OS, run commercial apps

• Virtualization Techniques– Hybrid Full-System Simulation

– Multiprocessor Host Interleaving

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2

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CPUP

Memory Devices

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Common-case behaviors

Uncommon behaviors

Memory

4-way P 4-way P

PP

PP

PP

PP

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Outline





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BlueSPARC


Shared L2 Directory

CMP Cache Model

• Piranha-like CMP Cache Hierarchy – Private L1 I&D Caches

– Single Shared L2 Cache (Victim Cache)

– L1 coherence maintained through directory in L2

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Target Cache Model

– Multiple concurrent memory refs– Directory for coherence

L1

P

L1

P

L1

P

L1

P

Shared L2

L1 L1 L1 L1

Virtualized Cache Model

– Memory refs serialized– Parallel L1 accesses for coherence

PP

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Memory

Refs

Architecture

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L1 I&D Caches

Cache

Contents

Instruction Caches

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2-way L1 caches

8 ways

8-way L2 cache

FPGA-Accelerated CMP Cache Simulator

L2 Cache

8-way pseudo-LRU

Statistics

Statistics

Data Caches

…

Statistics

Implementation Details

• Runs @ 100MHz on BEE2 board

• 2500L of fully parameterized Verilog– Parameters: # CPUs, L1/L2 dimensions, # ways, etc

• Purely Functional Model– No timing info

– Only tags + status bits stored and updated

• FPGA Resource Usage (Virtex II Pro 70)

• Limitations– FPGA resource usage dominated by on-chip memory

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64KB L1s - 4MB L2 128KB L1s - 16MB L2

LUTs 7483 (11%) 7277 (11%)

BRAMs 134 (40%) 292 (89%)

Outline





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BlueSPARC



Branch Predictor Model

• Typical 2-level Branch Predictor– Meta predictor selects Bimodal or Gshare predictor

– 8-way Branch Target Buffer

• 16 BTBs (one per cpu) too large for BEE2 FPGA

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BTB

GshareBimodal

Meta

Target BP Model

BTB

GshareBimodal

Meta

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Virtualized BP Model

GshareBimodal

Meta

Single SharedBTB

GshareBimodal

Meta…

– Single Shared BTB for all CPUs– One BTB per CPU

Multiple BTBs vs. Single BTB

• OK to use single BTB? Generally no, but OK for– Functional warming of homogeneous workloads

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Separate BTBs vs. Single BTB(16K-entry, 8-way)

Separate BTBs

Single BTB

Single BTB achieves same accuracy as multiple BTBs

Implementation Details

• Runs @ 100MHz on BEE2 board

• 700L of fully parameterized Bluespec– Parameters: # CPUs, Predictor Sizes, BTB Size/Associativity

• Realistic Prototype Configuration– 16 CPUs

– 8K-entry Meta, 32K-entry Bimodal, 8K-entry Gshare

– Single shared 16K-entry 8-way BTB

• FPGA Resource Usage (Virtex-II Pro 70)– LUTs: 3938 (5%)

– BRAMs: 193 (58%)

• Limitations– Single shared BTB may not perform accurately for all workloads

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Outline





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BlueSPARC



Design Experiences

• Identify opportunities for simpler designs

– Virtualization reduces resource requirements/complexity

– Less-constrained functional simulation environment

– Think about specific requirements of application

• Efficient mapping to FPGA resources is crucial

– Reorganizing the cache modules allowed for 2x larger designs

• Existence of SW reference design is important

– Reduces design time

– Simplifies verification

• Bluespec reduces design complexity

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Future Work

• Software Monitoring/Analysis

– e.g. debugging, performance tuning, instruction set profiling

• Rapid Exploration of new Architectures

– Simple functional models for first-order perf. results

– Detailed cycle-accurate models for high-fidelity simulation

• SW Developer/Educational Tool

– Real-time viewing of system state and statistics (Check out our DEMO )

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Other Instrumentation Applications

Future Directions• Scale number of CPUs

• Augment simulation models with timing extensions

Demo

• Web-based Real-time Viewing of Statistics

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Thanks! Any [email protected]://www.ece.cmu.edu/~protoflex

AcknowledgementsWe would like to thank our colleaguesin the RAMP and TRUSS projects.

protoflex: fpga-accelerated instrumentation • software monitoring/analysis – e.g. debugging,...

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