Proposal for read-out of Forward Detector straw tubes

• PANDA DAT requirements

• General layout

• Prototypes

M. Idzik, M. Kajetanowicz, K.Korcyl, G. Korcyl, H.Kuc, A. Misiak, P.Salabura, J. Smyrski, R. Trębacz Krakow Panda group

Straw tubes read-out chain

FE cards (preamp+ shaper+ discriminator) Sensitivity ~ 3 fC, noise <1 fC

• based on available ASIC's : CARIOCA or new development based on LUMICAL++ (Marek Idzik)

• located on detector frames

• differential output (LVDS)

Trigger and Read-our Boards- TRB

• based on HTDC : time measurement + TimeOverThreshold for amplidtude meas.

• time w.r.t external common clock , 780 ps binning (low resolution-40 MHz clock)

• Zero suppression & Hit detection. Slow control interface (i.e EPICS)

• data output via GBit optical link

Common Clock Distribution

Detector Concentrator : Compute Node ATCA standard

• several TRB inputs

• Detector memory buffer

• feature extraction –cluster and tracklet finding i.e based on fired wires numbers and time stamps

FE

TRB

Detector Concentrator

Straws: ~ 15000 tubes (6 chambers*8 planes)

• Max drift time ~ 150 ns, @ 500 kHz max averaged hit rate pile up <10%, 2-3 ns time resolution

• Gain: ~ 2 * 104

• Ar (90)/CO2 (10) mixture

FEE Connection to detector

Zdet (f) (f >50 MHz) L/C=370

Cdet = 9pF/m (14-18 pF)

NEED LOT OF ATTENTION !!!!

? (not decided, yet)CARIOCA

?

CiG

LiRfZ

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FEE cards should be electr. shielded !

FEE (LUMICAL) connected to straws

(UJ october 2008)

FEE Connection to detector

additional resis. ?

CARIOCA 10• CARIOCA (IBM 0.25 m CMOS6SF ): 8 channels, preamp, shaper,

BLR, discriminator, differential (LVDS) output:• radiation hardness (checked for LHC requirements: no effects up to

20 Mrad dose)• Sensitivity : at 220 pF for negative pulse : 2.3 mV/fC• peaking time 14 ns, pulse width 60 ns • power consumption 25 mW/channel

4 ASIC FEE-UJ’2008

CERN -proto

Characteristic (I): amplitude as a function of injected charge : CARIOCA 10

gain ~ 2,6 mV/fC

TR

TDTF

C

1pFV

TD = 2ns

TF = 34nsPW = 1ns

V1 = 0

TR = 1ns

V2 = -1000 mV R50

FREQ = 50 kHz

INA

V/56

Carioca+Straw tube (TOT)

HV: 1500 V

HV: 1400 V

no sourceSr90 source

• Noise (external pick-up) ~ 8 fC (status last year) – not satisfactory

• New FEE board (better grounding) + em. shielding expected to improve situation

Time Over Threshold – energy loss HADES MDC

• Signal height (V) ~ dE/dx •dE/dx vs momentum

Jochen Markert, A.Schmah (GSI)

24 * ~7 mm gaps He:Iso (2:1)FEE based on ASD8 chip

Time Over Threshold – energy loss resolution measured by HADES MDC

Garfield simulations for straws

Pions 0.8 GeV/c

Protons0.8 GeV/c

one straw average from 20 straws

• Ar:CO2 (90:10) @ 2 bars• HV 1500 V• charge integration time 100 ns • perpendicular incidence

~5-6%

AddOn connector

Trigger and Read-out Board developed in synergy with

HADES experiment 128 channel TDC based on

HPTDC optional On-board DAQ functionality via

ETRAX-FS (LINUX OS 3 200 MHz processors: 100MBit/s Fast Ethernet interface)

Optical Digital link 2GBit/s) High speed (15 Gb/s) AddOn-

connector (32 LVDS) DSP (TigerSharc TS201) for

on-line triggeralgorithms/pre-processing

LVDSTTL TTL

Virtex4(LX40)

EtraxFSEtraxFS

SDRAM

2GBit/s 2GBit/s optical optical

linklink

DSP (TS201)

Optional

SDRAM

100MBit/s ethernet

HPTDCHPTDC HPTDCHPTDC HPTDCHPTDC HPTDCHPTDC

Marek Palka, GSI 13

The TRBv2

DC/DCDC/DCETRAXETRAX

DSPDSP

FPGAFPGAVirtex4Virtex4

TDCTDC0, 10, 1

TDC 2, 3TDC 2, 3

SDRAMSDRAM Optical linkOptical link

SDRAMSDRAM

EthernetEthernet

4 TDC – 128 channels (~40ps RMS resolution) FPGA – Virtex4LX40 4x512Mb SDRAM ETRAX FS 100Mb/s,TCP/IP 2,5 Gb/s optical link DSP TigerSharc AddOn connector DC/DC converters

HUB

1212TRB

Conversion from 2 Gb/s 8/10 bit serial transmission to Ethernet protocol (UDP)

16 SFPs (Small Form-factor Pluggable transceivers) optical connectors

receive/transmit: ie 12 * 2Gb/s and 4 * 1Gb Ethernet

FPGA (Lattice SCM 25) with IP core

Conversion to Ethernet tested(G. Korcyl)

Expected rates

pbeam = 15 GeV/c, NInt=2x107 s-1

.

HPTDC working mode with free running clock

•1 MHz trigger clock

• 1 s matching window (1,2 s searching window) (T.latency=match.window)

• Multiplicty of hit/channel 0.4 (in window) by 400 kHz /wire

• hit losses neglegible (concern for >3 MHz/channel)

• TDC data: leading & trailing edge : 32 bits(header: TDC id, Event ID, Bunch Id)

32 bits data : TDC id, channel, data 19 bits

(pairing mode: 12 bits trailing + 7 bits width)

32 bits(trailer)

clock (1MHz)

time

match. window

T

Data flow estimate (example)• 128 channels/wire plane :4 FEE(32 channels each) - 1 TRB card (4x32 channels HPTDC)

• 2.0 Gbit/s link (250 MByte/s )- total max load (4 links) =1.0 GByte/s

• average maximal load/TRB (1 HPTDC): 13 MHit/s ( 13 hits per trigger/TDC) @ 400 kHz rate/wire

• 13 MHits*10 Bytes(hit=trailing + falling edge) = 130 MByte/s

x 8 (wire planes)

FEE

TRB4 links (1 GByte/s) to Compute Nodes

wire plane

O degree plane Left (L)

O degree plane

Right (R)

• back-up slides

Characteristics : Amplitude as a function of injected charge: LumiCal (AGH) ASIC

gain ~ 13 mV/fC

Pulses from detector in LUMIVAL (Rf mode)X- ray source 55Fe

• HV = 1200 V • HV = 1350 V

Pulses from iron source 55Fe, in gas mixture 90% Ar 10% CO2

Visible differences between pulses from escape peak and main peak, At picture on the right side pulses saturation of large pulses is visible

shape changes because of amplitude saturation

after X-ray escape

full absorption

Cosmic rays: straw tube with LumiCal chip and ADC with gate signal from scintillating detector

HV =1300 V, gas mixture 90% Ar 10% CO2

noise peak , generated because of larger scintillator area as compared to straw tube

Detector and DAT requirements

• interaction rate: 20 MHz

• raw data flow: 40 - 80 GB/s

• typ. event size: 4 – 8 kB

• lack of ONE SPECIFIC hardware trigger signal

• continuously sampling FE (time stamps)

• flexibility in the choice of triggering algorithms

PANDA DAT architecture (one possible choice)

2 alternative optionsconsidered so far(K. Korcyl )1.push and pull2.„push only”

24

The HADES DAQ (>100 TRBs!)

CTS

...TRB for RPC

TRB +MDC AddOn

TRB +RICH AddOn

TRB + Shower AddOn

LVL1 Trigger box

TRB for Time

Wall,Start,Veto

TRB +TOF AddOn

Parallel Parallel Event Event

BuildingBuilding(computers)(computers)

Ethernet

to t

he

fr

on

t e

nd

ele

ctr

on

ics

TRB + HUB AddOn

TRB + General purpose AddOn

TRBnet

VME CPU

HPTDC features Used in many HEP experiments. Developed at CERN, produced in IBM technology 0.25 m CMOS (ibm)

32 channels multihit TDC with variable resolution: 785ps, 195ps, 98ps, 25ps (LSB) - measurement wrt. free running clock, self calibration, double pulse resolution typ. 5 ns

Max hit rate/channel 2 MHz, Trigger rates up to 1MHz @40MHz clock

Internal buffer to story hits (max 256 hits/8 channel)- buffer BUT with 4 deep derandomizer in each channel

individual registration of leading and trailing edges inside internal chip buffers- Time over Threshold

Two operation modes:

A: TRIGGER MATCHING disabled. The raw time measurements from input channels are passed unchanged to the read-out fifo and can be readout to external buffers. 40 MHz read-out

B. TRIGGER MATCHING enabled. Hits inside pre-programmed window are filtered. Latencies <50 s

High rates->low latencies

HPTDC hit losses

25 ns dead time reduces loss by factor 10 at 3 MHz rate

hit rate