Groups: G1 G2 G3 G5

Member1 Oesting, Matthew Boggs, Thomas Ivester, Julius Kim, Choongsoon

email1 moesting3 tboggs3 jivester3 ckim96

Grade1

Member2 Jaoudi, Joseph Giles, David Larsen, Dennis McMenamin, Peter

email2 jjaoudi3 dgiles3 dlarsen8 pmcmenamin3

Grade 2

Member3 Collins, Michelle Lumish, Jeffrey Zhang, Yining

email3 mcollins44 jlumish3 yzhang611

Grade 3

BGR and BMR Specifications:

CMOS Process Baker 50 nm Table Baker 1-um Table TSMC-0.18 TSMC-0.18

Supply (V) 1.2 3.7 1.2 2.4

Vref (V) 0.6 2.5 0.7 1

Max Supply Sensitivity (ppm) within 10% of VDD 2000 1000 1000 2000

Max Temp Sensitivity (ppm @ 'C) 100 @ 37 100 @ 37 10 @ 37 50 @ 26

Max Power consumption (uW) 10 20 10 10

Iref (uA) 0.4 3 2 2.5

Iref with VTHn = 10%

Iref with VTHp = 10%

Iref with R= 10%

Vref with VTHn = 10%

Vref with VTHp = 10%

Vref with R= 10%

Minumum/Maximum Supply Voltage

TCIref (ppm)

TCVref (ppm)

Power Consumption (uW)

Resistor Value (Ohm) and TCR1

Vref and Iref within temp sweep (-20 to 100 'C)

Vref and Iref within supply sweep (10% to 150%)

Power Supply Rejection Ratio (PSRR) for Vref and Iref

Startup delay

Groups: G6 G7 G9 G10

Member1 Kani, Nickvash Li, Man Ravichandran, Adithya Biesiadecki, Todd

email1 nkani3 mli76 aravichandran7 tbiesiadecki3

Grade1

Member2 Kumar, Vachan Montoya, Andrew Song, Jack Murali, Kowshik

email2 vkumar38 amontoya8 jsong44 kmurali8

Grade 2

Member3 Malinowski, Andrew Paladugu, Eswar

email3 amalinowsk3 epaladugu3

Grade 3

BGR and BMR Specifications:

Process AMI-0.5 AMI-0.5 Baker 1-um Table AMI-0.35

Supply (V) 5 3.3 5 2.4

Vref (V) 2.5 1.26 1.26 0.6

Max Supply Sensitivity (ppm) within 10% of VDD 1000 1000 1000 500

Max Temp Sensitivity (ppm @ 'C) 50 @ 26 50 @ 50 100 @ 37 100 @ 26

Max Power consumption (uW) 15 5 10 10

Iref (uA) 1 0.25 1 2.5

Iref with VTHn = 10%

Iref with VTHp = 10%

Iref with R= 10%

Vref with VTHn = 10%

Vref with VTHp = 10%

Vref with R= 10%

Minumum/Maximum Supply Voltage

TCIref (ppm)

TCVref (ppm)

Power Consumption (uW)

Resistor Value (Ohm) and TCR1

Vref and Iref within temp sweep (-20 to 100 'C)

Vref and Iref within supply sweep (10% to 150%)

Power Supply Rejection Ratio (PSRR) for Vref and Iref

Startup delay

Instructions:

Design a beta multiplier reference (BMR) and a bandgap reference (BGR) in the fabrication processes that are indicated for your

group and try to achieve as many requested specifications as possible, or even better performance than what is specified.

Briefly show your hand calculations and design procedure in your slides.

If you cannot meet one or more of the specifications, you should explain the reason in your slides and try to get as close as possible.

Particularly for the power consumption, you should try to consume as little as possible (even better than the specs if ppossible).

Summmarize the other specifications that have been requested in a table in your slides with brief indication of the simulation method.

Every group sends in only one set of slides.

Each member of the group shoud individually send the above filled table in this Excel sheet with any additional detail that might fit.

Use this file naming convention (group x): Gx_Lastname1_Lastname2_Lastname3_Project1_ECE4430_F11.ppt

In the first slide include the name of all group members.

In the individual Excel sheet, in the space below the name of each of your group memebers, give them a grade from 1

(did not cooperate at all) to 10 (did a great job and was very effective). Feel free to add any further comments about group cooperation.

All group members are responsible for answering questions about both reference generators during the presentation.

Additional Notes:

To find temperature variation of the resistor layer that you use, either refer to the proces information or use Table 4.1 in Baker P88.