PROJECT REPORT

Title: 4-bit binary sequential multiplier

4-bit binary combinational multiplier

Group Members:

Muhammad Aslam 1420-fet/bsee/f10

Munawwar Ali abbasi 1417-fet/bsee/f10

Malik Tauqeer 1406-fet/bsee/f10

Husnain Hakim 1344-fet/bsee/f10

Instructor :

Engr, Hassan Murtaza

Faculity OF Engineering And Technology

INTERNATIONAL ISLAMIC UNIVERSITY,ISLAMABAD

Obstract

We design 4 bit multiplier which takes two four bits inputs and multiply them sequential and give prouduct of two in binary form

Block diagram

Sequential multiplier design procedure

The method for designing a sequential binary multiplier has two main steps:

(1) choose a datapath architecture

(2) design a state machine to control the datapath.

For a given datapath architecture, the state machine must generate the appropriate sequence

of control signals to direct the movement of data to produce the desired product.

datapath

The first datapath architecture we will consider is shown in Figure ,for an 8-bit datapath. Along with a single adder,shift registers are allocated for the multiplicand and multiplier,and a fixed register is alloca-ted for the product. The multiplicand register is sized to the length of the Product register to accommod-ate the shifting operations at each cycle. The controller must assert Ready and then wait for an external

Controller

The controller asserts ready and then wait for an external agent to signal Start. When Start is asserted, the controller de-assert Ready, load the registers, direct the shifting and adding of data to form the product, and finally re-assert the signal Ready. The bits of the multiplier register control the shifting and adding operations that form the accumulated product.

Complete Diagram

State Diagram

Coding

TOP MODULE

module Multiplier_STG_0 (product, Ready, word1 , word2, Start, clock, reset);

parameter L_word = 4; output [2*L_word -1: 0]product;

output Ready; input [L_word-1:0]word1 , word2;

input Start, clock, reset; wire mO, Load_words, Shift;

Datapath M1 (product, mO, word1 , word2, Load_words, Shift, Add, clock, reset);

Controller M2 (Load_words, Shift, Add, Ready, mO, Start, clock, reset); endmodule

DATAPATH

module Datapath (product, mO, word1 , word2, Load_words, Shift, Add, clock,reset);

parameter L_word = 4; output [2*L_word -1: 0] product;

output mO; input [L_word-1:0] word1 , word2;

input Load_words, Shift, Add, clock, reset; reg [2*L_word-1: 0] product, multiplicand;

reg [L_word-1:0] multiplier; wire mO = multiplier[0];

always @ (posedge clock or posedge reset) begin

if (reset) begin multiplier <= 0; multiplicand <= 0; product <= 0; end

else if (Load_words) begin multiplicand <= word1; multiplier <= word2; product <= 0; end

else if (Shift) begin multiplier <= multiplier>>1; multiplicand <= multiplicand <<1; end

else if (Add) product <= product + multiplicand; end

endmodule

CONTROLLER

module Controller (Load_words, Shift, Add, Ready, mO, Start, clock, reset);

parameter L_word = 4; parameter L_state = 4;

output Load_words, Shift, Add, Ready; input mO, Start, clock, reset;

reg[L_state -1: 0]state, next_state; parameter S_idle = 0, S_1 = 1, S_2 = 2;

parameter S_3 = 3, S_4=4, S_5 = 5, S_6 = 6; parameter S_7 = 7, S_8 = 8;

reg Load_words, Shift, Add; wire Ready = ((state == S_idle) && !reset)||(state == S_8);

always @ (posedge clock or posedge reset)

if (reset) state <= S_idle; else state <= next_state;

always @ (state or Start or mO) begin Load_words = 0; Shift = 0; Add = 0;

case (state)

S_idle: if (Start) begin Load_words = 1; next_state = S_1; end else next_state = S_idle;

S_1: if (mO) begin Add = 1; next_state = 8_2; end else begin Shift = 1; next_state = S_3; end

S_2: begin Shift = 1; next_state = S_3; end

S_3: if (mO) begin Add = 1; next_state = S_4; end else begin Shift = 1; next_state = S_5; end

S_4: begin Shift = 1; next_state = S_5; end

S_5: if (mO) begin Add = 1; next_state = S_6; end else begin Shift = 1; next_state = S_7; end

S_6: begin Shift = 1; next_state = S_7; end

S_7: if (mO) begin Add = 1; next_state = S_8; end else begin Shift = 1; next_state = S_8; end

S_8: if (Start) begin Load_words = 1; next_state = S_1; end else next_state = S_8;

default: next_state = S_idle; endcase end endmodule

4-bit binary combinational multiplier

Introduction

A combinational multiplier is a good example of how simple logic functions (gates, half adders and full adders) can be combined to construct a much more complex function. In particular, it is possible to construct a 4x4 combinational multiplier from an array of AND gates, half-adders and full-adders

In the course of multiplying two binary numbers, each bit in the multiplier is multiplied with the multiplicand. Each of the four products is aligned (shifted left) according to the position of the bit in the multiplier that is being multiplied with the multiplicand. The four resulting products are added to form the final product.

Since we are dealing with binary numbers, forming the products is particularly easy. If the multiplier bit is a 1, then the corresponding product is simply an appropriately shifted copy of the multiplicand. If the multiplier bit is a zero, then the product is zero. 1-bit binary multiplication is thus just an AND operation

METHOD Consider computing the product of two 4-bit integer numbers given by A3A2A1A0 (multiplicand) and

B3B2B1B0 (multiplier). The product of these two numbers can be formed as shown below.

Each of the ANDed terms is referred to as a partial product. The final product (the result) is formed by accumulating (summing) down each column of partial products. Any carries must be propagated from the right to the left across the columns.

Design procedure

This multiplier is constructed from an array of building blocks, shown in the first figure below. Each building block consists of an AND gate for computing locally the corresponding partial product (XYg), an input passed into the block from above (Sum In), and a carry (Cin) passed from a block diagonally above. It generates a carry out bit (COUT) and a new sum out bit (Sum Out). The second figure illustrates the interconnection of these building blocks to construct a 4x4 combinational multiplier.

Block diagram

Code

TOP MODULE

module Top(P,A,B);

output [7:0]P; input[3:0]A,B; wire [15:0]s,c;

ceell a(s[0],c[0],0,0,A[0],B[0]); ceell b(s[1],c[1],0,0,A[1],B[0]);

ceell ce(s[2],c[2],0,0,A[2],B[0]); ceell d(s[3],c[3],0,0,A[3],B[0]);

ceell e(s[4],c[4],s[1],c[0],A[0],B[1]); ceell f(s[5],c[5],s[2],c[1],A[1],B[1]);

ceell g(s[6],c[6],s[3],c[2],A[2],B[1]); ceell h(s[7],c[7],0,c[3],A[3],B[1]);///

ceell i(s[8],c[8],s[5],c[4],A[0],B[2]); ceell j(s[9],c[9],s[6],c[5],A[1],B[2]);

ceell k(s[10],c[10],s[7],c[6],A[2],B[2]); ceell l(s[11],c[11],0,c[7],A[3],B[2]);

ceell m(s[12],c[12],s[9],c[8],A[0],B[3]); ceell n(s[13],c[13],s[10],c[9],A[1],B[3]);

ceell c_e(s[14],c[14],s[11],c[10],A[2],B[3]); ceell ps(s[15],c[15],0,c[11],A[3],B[3]);

assign P={c[15],s[15],s[14],s[13],s[12],s[8],s[4],s[0]}; endmodule

CELL MODULE

module ceell(sum,cout,sum_in,cin,A,B);

output sum,cout; input sum_in,cin,A,B; wire inter; assign inter=A&B;

full_add ab(sum,cout,cin,inter,sum_in); endmodule

FULL ADDER MODULE

module full_add(sum,cout,cin,A,B);

output sum,cout; input A,B,cin; wire s,c,c2;

assign {c,s}=A+B; assign {c2,sum}=s+cin; assign cout=c||c2; endmodule