Progress report of new PHENIX pilot chip

Hiroyuki Kano (RIKEN)

1. Overview

2. Digital pilot ASIC and test board

3. Functionalities and test result

4. GOL test

4x BUS

Pilot Module Overview

Pilot module (on-detector)

Readout chip control signals

4x32bit@10MHz data Optical

data link

DAQ (counting room)

CLK

Command

Sen

sor

Rea

dout

chi

p

Digital pilot ASIC

GOL

AA CLK

Digital pilot

GG

ctrl

data

32b

data

A. ALICE original

bus opt

AA

Digital pilot

GG

ctrl

datadata

Digital pilot

GG

ctrl

Digital pilot

GG

ctrl

data

data

CLK

Digital pilot

GG

ctrl

data

B. For PHENIX 4x bus

bus

GG

ctrl

data

opt

AACLK

GG

ctrl

data

2x32b

C. PHENIX pilot w/ new chip

32b

32b

32b

32b

1.6Gbpsmode

Why New Digital pilot ASIC?

OE/EO OE/EO

OE/EO

OE/EO

OE/EO

OE/EO

OE/EO

2x32b

G = Gigabit Optical Link (GOL)GG

Digital pilot

Digital pilot

New chip

= Analog monitor chipGGAA

Digital pilot ASIC, Packaging, and Test board

Bare-chips were delivered from CERN(IBM). [11 Oct.]

Bare-chips ware packaged for the test purpose by Fujitsu. (QFP256, 23packages) [19 Oct.]

ASIC test board with chip was delivered. [22 Nov.]

8mm

6mm

QFP256 package

28m

m

Packaged ASIC Bare chip Digital pilot ASCI test board

PHENIX Pilot Chip Overview

Serial control stream

L1 L2y L2n rst

JTAG(GOL)

JTAG(RO)

CE

Shreg

clev

nevr

strobe

FO

DATA_1

DATA_0

Feedback

JTAG

Readout-chip

control

Pixel data input

(10MHz) pixel data output

(40MHz)

Pilot Chip has three main blocks

1. Multiplexer

converts readout data; 4x32bit@10MHz to 1x32bit@40MHz.

2. Readout chip controller

make readout sequence.

3. Command decoder

decodes commands from serial stream.

MUX32bit bus width

Readout chip

Controller

Command Decoder

Probing

Test pattern generating

Test board

Test setup for the new digital pilot ASIC

Command Decoder

Command decoder

Serial control stream

Commands, JTAG, etc

commands Code binary

reset_control_receiver 00000000

reset_global 11101000

reset_gol 11100100

reset_pixel 11100010

trst_pixel 11100001

trse_standard_on 10110100

trse_standard_off 10110010

l1 01010110

l2y 01011010

l2n 01010101

testpulse 11011000

jtag 1010(TMS,~TMS,TDI,~TDI)

idle 11001100

GOL reset command by new chip [1-DEC-04]

testpulse command by new chip [1-DEC-04]

serial stream

reset_gol

testpulse

serial stream

out

out

in

in

inBelow 2 pictures shows

you that command signal corresponding to serial stream is probed.

Readout chip Controller

nevr_i

ce_0

ce_1

ce_9

Readout sequence by new chip [1-DEC-04]

This picture shows the readout sequence;

The nevr_i and ce_n are generated from L1 and L2.

Wave form of readout sequence (ALICE digital pilot document)

Reference :http://a.home.cern.ch/a/akluge/www/work/alice/spd/spd_documents/ops2003book.pdf

MUXCLK40 and output data by new chip [9-DEC-

04]

This picture shows that the original data bus (BUS A31-0) and additional data bus (BUS B31-0) can be processed correctly.

This test pattern is; BUS A31-0 pattern = up counter;

00000000,11111111,22222222,… BUS B31-0 pattern = down counter;

FFFFFFFF,EEEEEEEE,DDDDDDDD,…

…..slot0 slot1 slot2 slot3 slot0 slot1 slot2 slot3

Reference :http://a.home.cern.ch/a/akluge/www/work/alice/spd/spd_documents/ops2003book.pdfProbing

Test pattern generating

Test board

Summary of ASIC test

• Packaging and test board assembly are finished.

• Result of functionality test seems fine, but not completed yet.

• Functionality test will be finished in this month.

GOL test setup

GOL test board:

It can be mounted on Vertex2-pro board via PMC connector

Vertex2-pro evaluation board:

=Vertex2-pro interface board Vertex2-pro has integrated hi-speed deserializer.

OE/EO converter:

Agilent evaluation board

GOL test full setup

GOL

Vertex2pro

EO converter

Optical fiver

FPGA program overview

• GOL test program is based on the xilinx evaluation source.

• Vertex2-pro generates test vector, serializes, and comparisons between generated vector and GOL output vector.

generating test signal

comparisonserialize (integrated)

display (LED&LCD)

deserializer (GOL)

Vertex2-pro program

Test step

3Gbps→1.6Gbps (cupper wire)

V2PRocketIO

Vertex2pro

TED Vertex2-pro test Board

1.6Gbps (optical fiver)

V2P Agilent EO board

Agilent OE board

1.6Gbps (optical fiver)

V2P GOL test board

Agilent OE board

1.

2.

3.

1. Cupper wire setup [26 Oct.] System test, Developing GB-ethernet protocol, Changing the link speed*

2. Optical fiver setup [12 Nov.] Optical component test

3. GOL test

*Changing the link speed

Vertex2-pro test board has 156MHz crystal for the V2-pro maximum speed. In our case, we need 1.6Gbps.

Summary of GOL test

• Test setup is ready now.

• Gigabit Ethernet protocol for GOL is developed.