programmable/stoppable oscillator based on self-timed rings eslam yahya 1,4, oussama elissati 1,3,...
TRANSCRIPT
Programmable/Stoppable Oscillator Based on Self-Timed
Rings
Eslam Yahya1,4, Oussama Elissati1,3, Hatem Zakaria1,4 , Laurent Fesquet1 and Marc Renaudin2
1TIMA Laboratory, Grenoble, France2TIEMPO, Montbonnot, France
3ST-Ericsson, Grenoble, France4Banha High Institute of Technology, Banha, Egypt
ASYNC 2009, UNC Chapel hill
ASYNC 2009, UNC Chapel Hill 2
Context and Motivation
Process variability increases drastically in the 45 nm technologies and beyond.
Application of DVFS techniques is essential.
Programmable oscillators are needed
Self –Timed Rings are promising solutions for: Reconfigurability. Process Variation.
However, no programmable oscillators based on Self-Timed Rings are introduced in the literature.
ASYNC 2009, UNC Chapel Hill 3
Outline
Self-timed rings Oscillation Frequency Modeling and Calculation Architecture of Programmable Self-Timed Ring Programmable-Stoppable Oscillator Implementation and results Conclusion and Future Work
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C C C C
Dff
Drr
Self-Timed Ring
1 iii CCTokenStage
1 iii CCBubbleStage
•Tokens and bubbles •Propagation rules
1 ( 1)% ( 1)%
token
i i i L i i LbubbleStage Stage C C C
T1
T B1 1
T B0
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Two Oscillation Modes
• Burst mode
• Evenly Spaced Mode
Oscillation modes
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Timed VHDL Model• Programmable Ring So many simulations.
• Contradiction between digital simulation and analog simulation.
• Simulating the same ring with the same number of tokens and bubbles, with tow different spatial token distributions.
Analog : same steady state waveform. Digital : different steady state waveform.
11 stage 4 Tokens/7 Bubbles
TTTTBBBBBBB TBBBBTTBBBT
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Charlie effect•An explanation of this difference between digital and analog simulation is needed.• Charlie effect!!??•The closer the input events; the longer the propagation time, causing the separation of the tokens in the ring.
2D Charlie Diagram
2min
2 ssDDsCharlie Charliemean
2ffrr
mean
DDD
2min
ffrr DDs
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Timed VHDL Model
11 stage 4 Tokens/7 Bubbles
TTTTBBBBBBB TBBBBTTBBBT
11 stage 4 Tokens/7 Bubbles
TTTTBBBBBBB TBBBBTTBBBT
Without Charlie Effect
With Charlie Effect
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Outline
Self-timed rings Oscillation Frequency Modeling and Calculation Architecture of programmable Self-Timed Ring Programmable-Stoppable Oscillator Implementation and results Conclusion and Future Work
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Estimating the oscillation period in Inverter Ring:
Estimating the oscillation period in Self-Timed Rings:
Where: s is the separation time between input events
Deriving an equation: T = 4 . Charlie(R) = f (Drr , Dff , R)
Charlie(R) is derived.
Modeling and Calculation
T = 2N . DInv
T = f (Drr, Dff, s)
s = f (NT/NB)
T = 4 . Charlie(s)
R = NT/NB s = f (R)
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Charlie(R)
2min
2 ssDDsCharlie Charliemean
rr
ff
B
T
D
D
N
N
2
2
2 rr
ffrrCharliemean D
DR
DDDRCharlie
rr
ff
B
T
D
D
N
N
2
2 1
2 ff
rrffCharliemean D
D
R
DDDRCharlie
If
If
Charlie from Charlie(s)
Charlie from Charlie(R)
Error < 1%
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Comparison with analog simulation
CaseNumber
of Stages
NT/NB R=NT/NB
Frequency(Electrical
simulation) MHz
Frequency(Model)
MHzError
A 11 10T/1B 10 796 797 0.12%
B 11 8T/3B 2.66 2417 2386 1.28%
C 11 6T/5B 1.2 3908 3914 0.15%
D 11 4T/7B 0.57 3802 3737 1.70%
E 11 2T/9B 0.2 1879 1891 0.63%
F 10 8T/2B 4 1751 1752 0.05%
G 10 6T/4B 1.5 3441 3476 1.01%
H 10 4T/6B 0.67 4143 4064 1.9%
I 10 2T/8B 0.5 2082 2081 0.04%
J 5 4T/1B 4 1747 1752 0.28%
K 5 2T/3B 0.67 4133 4064 1.67%
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Outline
Self-timed rings Oscillation Frequency Modeling and Calculation Architecture of programmable Self-Timed Ring Programmable-Stoppable Oscillator Implementation and results Conclusion and Future Work
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• Fixed No. of stages.
• Frequency is controlled by changing (NT/NB).
PSTR : Programmable Self-Timed RingStrategy 1 (Token/bubble configuration)
C1
Set Reset
C2
Stage 1
Set Reset
Stage 2
Token Control Word
Cn
Set Reset
Stage n
From Stage (3)
From Stage (n-1)
To Stage (n-1)
Req
Ack
Req
Ack
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PSTR : Strategy 2• Variable No. of stages with controllable NVariable No. of stages with controllable NTT/N/NBB..
C1M1
Set Reset
C2
Stage 1
M2
Set Reset
Stage 2
Stage Control Word
Token Control Word
T1D1
SCW0 SCW1
Cn
Set Reset
Stage n
From Stage (3)
From Stage (n-1)
To AND of Stage (3)
To Stage (n-1)
Req
Ack
SCW2
T2
b
a
b
a
Req
Ack
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Outline
Self-timed rings Oscillation Frequency Modeling and Calculation Architecture of programmable Self-Timed Ring
(PSTR) Programmable-Stoppable Oscillator Implementation and results Conclusion and Future Work
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• A complete architecture of PSO is designed and implemented.
Asynchronous communication protocol between the processor and the PSO.
• The processor can Pause/Reprogram the PSO output.
• The protocol is taking into consideration Metastability and racings.
Programmable/ Stoppable Oscillator (PSO)
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Interface between µ-Processor and PSO
Top Control +
Micro-Processor
Programmable/Stoppable Oscillator“PSO”
CF
PC
PCCF
Reset
Reset
FC
FC
CLK
CFD
PCD
FC … Frequency Code
CF … Change Frequency
CFD … Change Frequency Done Signal
PC … Pause Clock
PCD … Pause Clock Done Signal
Interface between µ-Processor and PSO
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Control UnitTCW SCW StopR_out
FC PC
Programmable Self-Timed Ring“PSTR”
CR_out
CFD
+
Reset
CFDCLK
Reset
FC CF Reset
PCD
PCD
PC
CF
Programmable/ Stoppable Oscillator (PSO)
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LUT 1
Reset Stop
FC CF Reset
LUT 2
Com
para
torCounter
TCW SCW
Count_Ref
EQCF D-FF
R_Out
D
Reset
Delay 1
CFD
Q
PC
Delay 2
Stop
PCD
CF
Rese
t (A
sy.)
Rese
t (A
sy.)
Reset
Stop
EQ
TCW … Token Control Word
SCW … Stage Control Word
R_Out … PSTR Ring Output
Control Unit
Stop
Control Unit
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Outline
Self-timed rings Oscillation Frequency Modeling and Calculation Architecture of programmable Self-Timed
Ring(PSTR) Programmable-Stoppable Oscillator Implementation and results Conclusion and Future Work
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A
CB
D
F
G
H
Timing Diagram of the PSO
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Low Frequency … 10Tokens/1Bubble
High Frequency … 6Tokens/5 Bubbles
Analog Results of the PSO Implemented Using 45 nm
STMicroelectronics Technology
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11 Stages RingStrategy
1Strategy
2Strategy
3
Frequency Range
500MHz – 3GHz
400 MHz – 1.7 GHz
450 MHz –
2 GHzNo. of
Frequencies5 13 9
Step Size Irregular 100 MHz Irregular
Static Power 8.7 nW 37.5 nW15.94 nW
Dynamic Power(for 1 Bubble)
63.68 µW
145 µW 82.3 µW
Results for Different Strategies
Strategy 3: is a partial control on the number of stages
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• Ring could not oscillate under 0.5V.• A linear change of frequency from 0.8V to 1.1V.
Frequency vs. Supply Voltage
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• Montecarlo Simulation 1000 Iterations
•Average value of 2.6 GHz
• Process variability effect on the clock period:
• 1% Within Die• 7,6% Die to Die
Den
sit
y
Frequency
250
200
150
100
50.0
0.01.75 2.0 2.25 2.5 2.75 3.0 3.25 3.5 3.75
mu = 2.69757sd = 205.025M N = 1000
Process Variability of the PSTR
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Outline
Self-timed rings Oscillation Frequency Modeling and Calculation Architecture of programmable Self-Timed
Ring(PSTR) Programmable-Stoppable Oscillator Implementation and results Conclusion and Future Work
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• Self Timed Ring is used as a core of programmable oscillator.
• For facilitating accurate and fast design environment, timed VHDL models and Charlie(R) are introduced.
• Programmability is introduced to Self-Timed Rings using different strategies.
• PSO is designed and implemented using STMicroelectronics 45nm CMOS technology.
• Asynchronous handshaking protocol between the processor and the oscillator is proposed.
• PSO shows glitch free and no truncated clocks at its output.
• The implemented chip is characterized for its speed, power consumption and sensitivity to process variability.
Conclusions
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• Adding a voltage controller to the power supply.
• Some special implementations for high-speed C-Elements.
• More investigation on the phase noise.
• Comparing the use of PSTR and some other alternatives.
Future Work
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Thank YouThank You