programmable smps and usb type-c controller...rt7205a integrate s an mcu to ha ndle various...

RT7205A®

DS7205A-00 February 2018 www.richtek.com

©Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

Applicationsl Travel Adaptors with Fast Charge Protocols (e.g., FCP,

SCP and AFC)

l Travel Adaptors with USB Type-C Control (e.g., 5V/1.5A

and 5V/3A)

Programmable SMPS and USB Type-C Controller

Featureslllll Protocols Supported

SCP, FCP, AFC and Proprietary Protocols

USB Type-C

lllll Highly Integrated

Embedded MCU with an Mask-ROM of 16kB, an

OTP-ROM of 8kB, and an SRAM of 0.75kB

Built-in Synchronous Rectifier Driver and

Controller

Built-in Charge Pump for a Wide VDD Operation

Range of 3V to 12V

Built-in Shunt Regulator for Programmable

Constant-Voltage and Constant-Current Control

Programmable Cable Compensation

BLD Pin for Quick Discharge of Output Capacitor

USBP Pin for Direct Drive of External Blocking

N-MOSFET

Power-Saving Mode in Standby Mode

lllll Protection

Adaptive Over-Voltage Protection

Adaptive Under-Voltage Protection

Firmware-Programmable Over-Current Protection

Firmware-Programmable Over-Temperature

Protection

General DescriptionThe RT7205A is a highly integrated and programmable

SMPS controller at the secondary side. It provides the

necessary functions and protections for high efficient and

high power density off-line AC-DC converter designs. The

RT7205A integrates an MCU to handle various proprietary

protocols (e.g., FCP, SCP and AFC) through D+/D-

interface and also support USB Type-C via CC1/CC2 pins.

An internal synchronous rectifier controller can optimize

efficiency and provide safe operate in both continuous-

conduction mode (CCM) and discontinuous-conduction

mode (DCM) even in the condition of a wide output voltage

range of 3V to 12V. Dual operational amplifiers with

respectively programmable reference voltages are included

for voltage-loop and current-loop regulation to provide

programmable constant-voltage (CV) and constant-current

(CC) regulation in high precision.

Ordering Information

Note :

Richtek products are :

RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.

RT7205A

Package TypeQW : WQFN-24L 4x4 (W-Type) (Exposed Pad-Option 2)

Lead Plating SystemG : Green (Halogen Free and Pb Free)

RT7205A Version(Refer to Version Table)

-Programmed Firmware Code AABBXAA : Application CodeBB : Model CodeX : Customer Approved Version Code

Marking InformationFor marking information, contact our sales representative

directly or through a Richtek distributor located in your

area.

RT7205A

2DS7205A-00 February 2018www.richtek.com


RT7205A Version TableVersion RT7205A RT7205AL

Maximum Output Voltage 12V 5V

VDS SCALE RVDS2 / (RVDS1 + RVDS2)

1/26 1/13

VOUT SCALE RFB2 / (RFB1 + RFB2)

1/5 1/2.5

Built-in FB Resistors O O

Blocking MOSFET Driver N-MOSFET N-MOSFET

WQFN-24L 4x4

(TOP VIEW)Pin Configuration

V_TRCS+CS-

D-D+

CC_GND

OP

TO

CC

1C

C2

RT

VF

BIF

B

V2AGND

VDDUSBPOVP

VDD

V9

V5

BLD

PG

ND

VG

VC

P

GND

1

2

3

4

5

6

7 8 9 10 1211

18

17

16

15

14

13

21 20 1924 2223

25

RT7205A

3DS7205A-00 February 2018 www.richtek.com


Simplified Application Circuit

2

1

AGNDO

PT

O

V_TR

CS+

CS-

D-

D+

CC_GND

V2

VDD

VDD

USBP

CC

1

CC

2

RT

IFB

VF

B

BLD

PG

ND

VG V9

VC

P V5

OVP

RT7205A

N-MOSFET

+

VBUS

GND

CC1

CC2

D+

D-

RT7205A



Functional Pin Description

Pin No. Pin Name Type Pin Function

1 V_TR AI Transformer voltage sense node.

2 CS+ AI Positive input of a current-sense amplifier for output current sensing.

3 CS- AI Negative input of a current-sense amplifier for output current sensing.

4 D- A/D IO USB D- channel.

5 D+ A/D IO USB D+ channel.

6 CC_GND GND Alternative ground for CC1 and CC2.

7 CC1 A/D IO Type-C connector Configuration Channel (CC) 1, used to detect a cable plug event and determine the cable orientation.

8 CC2 A/D IO Type-C connector Configuration Channel (CC) 2, used to detect a cable plug event and determine the cable orientation.

9 RT A/D I Remote thermal sensor connection node for over-temperature protection.

10 IFB AI Feedback input for the constant-current loop.

11 VFB AI Feedback input for the constant-voltage loop.

12 OPTO AO Current sink output for optocoupler connection.

13 OVP AO Over-voltage fault indication output, used to pull low an optocoupler.

14 USBP D IO Control signal of the blocking N-MOSFET

15 VDD PWR Supply input voltage.

16 VDD PWR Supply input voltage.

17 AGND GND Analog ground.

18 V2 PWR Regulated DC bias to supply for the MCU.

19 V5 PWR Regulated DC bias to supply for internal circuitry.

20 VCP AO Charge pump driver output.

21 V9 PWR Regulated DC bias to supply for the synchronous rectifier driver.

22 VG AO Gate driver output for the SR MOSFET.

23 PGND GND Power ground.

24 BLD D IO Bleeder connection node to provide another path to discharge the output capacitor.

25 (Exposed Pad)

GND GND Power ground. The exposed pad must be connected to GND and well soldered to a large PCB copper area for maximum power dissipation.

RT7205A



OperationThe RT7205A is a highly integrated secondary-side

programmable SMPS and USB Type-C controller with

various functions and protections for off-line AC-DC

converters.

Power Structure

Biased by the VDD pin, the RT7205A has two regulated

DC output voltages, V5 and V2, to supply the internal circuit

and the internal microprocessor (MCU). The bypass

capacitors at the V2 and V5 pins are required to improve

stability of the internal LDO and to minimize regulated

ripple voltages. The RT7205A also integrates a charge

pump to generate a boost voltage V9 from V5 with VCP

pin for capacitor connection so that the V9 voltage can be

nearly 2 times of the V5 voltage and the VG pin can directly

drive the SR MOSFET. Besides, the charge pump allows

the controller to operate under low supply voltage condition

as long as the output voltage is not below the programmed

UVP level.

Functional Block Diagram

Constant-Voltage and Constant-Current (CV/CC)

Regulators

Two regulators are paralleled and connected to an open-

drain output, OPTO pin. The operation of each feedback

loop is similar to that of the traditional TL431 shunt

regulator except that VOPTO operating range is wider, from

0.3V to 16.5V, which enables easy design of converters

with a wider output range. The OPTO pin will be in high-

impedance state, if the VDD voltage is still below a UVLO

threshold VVDD_ON, which ensures a smooth power-on

sequence. The reference voltages, VREF_CV and VREF_CC,

for the voltage and current feedback loops, respectively,

are analog output voltages from the embedded DAC, and

their digital counterparts are from the MCU. The analog

output range of the 10-bit DAC is from 0 to VDAC_MAX (typical

2.7V), which makes output voltage resolution as small as

13.2mV and 6.6mV for the RT7205A and RT7205AL,

respectively, to achieve high-precision CV regulation.

10-bit DAC

Synchronize RectifierController

CC&CVShunt Regulator

Charge Pump Power Green Alarm OSC Protection

MCU

Mask-ROM

SRAM

TMR

IO

WDT

10-bit ADC

I2C

Program / Test

CS Amplifier

RT

DPDM

BLD

USBP

OVP

CC1CC2

V_TR

VDD

VREF_CC

VREF_CV

VD

DV5

V2

VCP

V9

VG

V_TR

IFBVFB

OPTO

RT

CS+

CS-

D+

D-

BLD

USBP

CC1

CC2

CC_GND

PGND

AGND

OVP

VD

D

OTP-ROMOPTO

CC1

CC2

RT7205A



Figure 1. CV and CC Loops

Interface of D+ and D-

The D+ and D- pins are used for BC1.2 compliance or for

communication with other proprietary protocols. The D+

and D- pins, connected to the MCU via an ADC, can be

reprogrammed for other purposes since they can be used

as an analog/digital input or output.

Figure 2. External Temperature Sensing

DOL

DI RT

IBIAS_RT

MCU

RNTC

RT BIAS

10-bit ADC

3.6V

Current-Sense Amplifier

To minimize power loss of the current sense resistor in

the converter, the RT7205A includes an amplifier with

virtually zero input offset voltage and with a voltage gain of

40. The sensed output current is amplified by the current-

sense amplifier, shown as “Io_signal ” in Figure 1, which

is then sent to the current-loop regulator for constant-

current regulation and also sent to the MCU, by way of an

10-bit ADC for analog-to-digital conversion, to update the

output current status for the MCU.

External Temperature Sensing

The RT7205A provides the RT pin, as a register-

programmable current source to bias a remote thermal

sensor, such as a thermistor (NTC), as shown in Figure

2. If the RT voltage is below an over-temperature protection

(OTP) threshold and the condition sustains for a

programmed time delay, the OTP will be triggered.

Figure 3. Interface of D+ and D-

DPMDO_LEV

DPOE

DPO

DPPE

DPPO

DPI

RH_DPDMAIN

MCU

10-bit ADC

SHORT SWITCHsDPM_SHORT

D+/D-

1.8V 3.3V 4.2V

RL_DPDM

Interface of CC1 and CC2

The CC1 and CC2 pins are used for compliance with USB

Type-C specification. When configured as a Downstream

Facing Port (DFP), three current capabilities of 80µA,

180µA, and 330µA, provided by each of the CC pins, will

ROPTO_VDD

VOFFSET_CS = 0.5V

VREF_CC10-bit DAC

ROPTO_GND

VDDVFBIFB OPTOCS+CS-

CS Gain = 40

+-

A

Io_signal

+

-

VDD UVLO

VDD UVLO

+

-

VREF_CV10-bit DAC

RFB1

RFB2

RT7205A



Figure 5. Interface of BLD and OVP Pins

Figure 4. Interface of CC1 and CC2

Open-Drain Drivers for BLD and OVP Pins

The BLD and OVP pins with their specific functions are

driven by open-drain drivers, as shown in Figure 5 and

explained below.

The BLD pin is used as a bleeder to help discharge the

output capacitor to Vsafe5V upon the detachment of a

connected device, or to a lower desired output voltage

level upon a UFP request, such as from 12V to 5V. A

resistor is connected between VOUT and the BLD pin and

a power resistor can be used for better power dissipation

capability.

be advertised to an Upstream Facing Port (UFP) as default

USB current, 1.5A, and 3.0A, respectively.

CC1I

CC1/CC2MCU 10-bit ADC

5V

DOL

DI

BLD/OVPDIEN

SR Control

To improve the AC-DC converter's efficiency, the RT7205A

includes a SR controller, which has proprietary auto-

tracking function to minimize dead time between the

conduction intervals of the SR MOSFET and the main

switch MOSFET, while it can still ensure safe operation

in both DCM and CCM conditions and even in a wide output

range. To prevent the on-time overlap of the main switch

MOSFET and the SR MOSFET, the SR controller will be

temporarily turned off under conditions of load transition,

output voltage transition, output short circuit, or low output

or input voltages with programmable thresholds. At light

load or no load condition, the SR controller will also be

disabled to reduce power consumption.

The OVP pin is pulled low when output over-voltage

condition (register-programmable : 115%, 120%, 125%)

occurs. By way of an optocoupler, it can shut down the

primary-side controller (for example, RT7752).

RT7205A



Parameter Symbol Test Conditions Min Typ Max Unit

VDD Section

VDD Turn-On Threshold Voltage

VVDD_ON

2.9 3.0 3.1 V

VDD Turn-Off Threshold Voltage

VVDD_OFF

2.55 2.7 2.85 V

VDD Turn-On/-Off Hysteresis VVDD_HYS -- 0.3 -- V

VDD Start-Up Current IDD_START VDD = 2.6V -- 200 300 µA

VDD Operating Current IDD_OP SR driver is disabled -- 10 -- mA

VDD Sleep-Mode Current IDD_SLEEP In sleep mode -- 900 -- µA

VDD Over-Voltage Protection Threshold Voltage

VVDD_OVP

14.5 15.5 16.5 V

VDD Over-Voltage Protection Threshold Voltage for Disable SR Driver

VVDD_OVP_SR With respect to VREF_CV 104.5 110 115.5 %

VDD Over-Voltage Protection Deglitch Time

tD_VDDOVP (Note 5) -- 50 -- µs

MCU Operating Frequency fOSC_MCU VDD = 5V 20.5 21.6 22.7 MHz

(TA = 25°C, unless otherwise specified)Electrical Characteristics

Recommended Operating Conditions (Note 4)

l Supply Input Voltage, VDD --------------------------------------------------------------------------------------------- 3V to 13V

l Junction Temperature Range------------------------------------------------------------------------------------------- −40°C to 125°Cl Ambient Temperature Range------------------------------------------------------------------------------------------- −40°C to 85°C

Absolute Maximum Ratings (Note 1)

l USBP to GND ------------------------------------------------------------------------------------------------------------- −0.3V to 25V

l VDD, OPTO, BLD, OVP to GND -------------------------------------------------------------------------------------- −0.3V to 16.5V

l V9, VG to GND ------------------------------------------------------------------------------------------------------------ −0.3V to 13V

l V5, VCP, VFB, IFB, V_TR, RT, CC1, CC2, D+, D-, CS+, CS- to GND--------------------------------------- −0.3V to 6.5V

l V2 to GND ------------------------------------------------------------------------------------------------------------------ −0.3V to 2.5V

l Power Dissipation, PD @ TA = 25°C WQFN-24L 4x4 ----------------------------------------------------------------------------------------------------------- 3.57W

l Package Thermal Resistance (Note 2)

WQFN-24L 4x4, θJA ------------------------------------------------------------------------------------------------------ 28°C/W

WQFN-24L 4x4, θJC ----------------------------------------------------------------------------------------------------- 7.1°C/W

l Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------ 260°Cl Junction Temperature ---------------------------------------------------------------------------------------------------- 150°Cl Storage Temperature Range ------------------------------------------------------------------------------------------- −65°C to 150°Cl ESD Susceptibility (Note 3)

HBM (Human Body Model) --------------------------------------------------------------------------------------------- 2kV

RT7205A



Parameter Symbol Conditions Min Typ Max Unit

Internal Bias

V5 Bias VBIAS_V5 6V < VDD < 16.5V 4.75 5 5.25 V

V5 Load Regulation 1mA < IBIAS_V5 < 30mA -- -- 150 mV

V5 Output Short Circuit Current IV5_SC 60 90 120 mA

V2 Bias VBIAS_V2 3V < VDD < 16.5V 1.71 1.8 1.89 V

V2 Load Regulation 1mA < IBIAS_V2 < 20mA -- -- 20 mV

V2 Output Short Circuit Current IV2_SC 30 50 70 mA

Regulator Section

Internal Resistor between VFB and VDD

RFB1 For RT7205A 64 80 96

kΩ For RT7205AL 24 30 36

Internal Resistor between VFB and GND

RFB2 16 20 24 kΩ

VOUT Scaling Factor KVOUT

(RFB1 + RFB2) / RFB2 For RT7205A

4.95 5 5.05

-- (RFB1 + RFB2) / RFB2

For RT7205AL 2.475 2.5 2.525

Default Reference Voltage for CV Regulators VREF_CV_ST

For RT7205A 0.97 1 1.03 V

For RT7205AL 1.94 2 2.06

Register -Programmable Default Reference Voltage for CC Regulators

VREF_CC_ST 0 0.72 0.8 0.88

V 1 0.99 1.1 1.21

Maximum DAC Output Voltage for CV Regulators

VREF_CV_MAX With 10-bit Digital to Analog Converter

2.67 2.70 2.73 V

Maximum DAC Output Voltage for CC Regulators

VREF_CC_MAX With 10-bit Digital to Analog Converter

2.67 2.70 2.73 V

Maximum ADC Sense Voltage VADC_MAX 10-bit A/D conversion 2.67 2.70 2.73 V

Ratio of Change in Reference Input Voltage to Change in OPTO Voltage

REF

OPTO

VV∆

∆

∆VOPTO = 16.5V to VREF

(Note 5) −2.4 −1.2 -- mV/V

Reference Input Current IREF (Note 5) -- 0.1 -- µA

Off-State OPTO Current IOPTO_OFF OPTO pin is open-circuited (Note 5)

-- 230 500 nA

Dynamic Impedance |ZOPTO| VOPTO = VREF, IOPTO = 1mA, f < 1kHz (Note 5)

-- 0.22 0.5 Ω

OPTO Turn-On Impedance RON_OPTO IOPTO_SINK = 20mA -- -- 200 Ω

Maximum OPTO Sinking Current

IOPTO_MAX 2 -- 20 mA

Internal Resistor between OPTO and VDD

ROPTO_VDD 40.8 51 61.2 kΩ

Internal Resistor between OPTO and GND

ROPTO_GND 50 60 70 kΩ

RT7205A




Current Sense Amplifier

Current-Sense Voltage Gain KCS

-- 40 -- V/V

Current-Sense Amplifier Output Offset Voltage

VOFFSET_CS -- 0.5 -- V

Unit Gain Bandwidth (Note 5) 1000 -- -- kHz

Output Current (Note 5) -- 0.1 -- mA

Charge Pump Section

Charge Pump Operating Frequency

fCP 150 170 190 kHz

Rise Time tR_CP CL = 6nF, V5 = 5V, from 20% to 80%

70 140 210 ns

Fall Time tF_CP CL = 6nF, V5 = 5V, from 80% to 20%

60 110 160 ns

Charge Pump Driver Impedance

ROUT_CP (Note 5) -- -- 10 Ω

Debounce Time tD_V9 (Note 5) -- 50 -- µs

V9 Turn-On Threshold Voltage VV9_ON 3.1 3.3 3.5 V

V9 Turn-Off Threshold Voltage VV9_OFF If V9 < VV9_OFF, the V9 internal circuit will be inactivated.

2.9 3.1 3.3 V

RT Section

Open-Loop Voltage VRT_OP VDD = 5V 3.2 3.6 4 V

Register-Programmable Internal Bias Current

IBIAS_RT

00 90 100 110

µA 01 18 20 22

10 3.6 4 4.4

11 Open

OVP Section

Maximum OVP Sinking Current IOVP_MAX 2 -- 20 mA

Pull-Low Impedance RL_OVP IOVP_MAX = 20mA -- -- 200 Ω

Register-Programmable Over-Voltage Protection Threshold

VVOUT_OVP With respect to VREF_CV

00 109.25 115 120.75

% 01 114 120 126

10 118.75 125 131.25

11 Disable

Debounce Time tD_VOUTOVP OVP pin is latched till VDD is below VVDD_OFF

-- 50 -- µs

BLD Section

Maximum BLD Sinking Current IBLD_MAX VBLD = 12V, In 300ms (Note 5)

0.2 -- 0.7 A

Pull-Low Impedance RL_BLD IBLD = 50mA -- -- 30 Ω

RT7205A




D+, D- Section

Pull-High Resistance RH_DPDM

10 12.5 15 kΩ

Pull-Low Resistance RL_DMDM 15 20 25 kΩ

Register-Programmable Output High Voltage

VOH_OP

VDD = 5V, RL = 15kΩ

00 Open Drain

V VOH_3.3V 01 2.97 3.3 3.63

VOH_1.8V 10 1.62 1.8 1.98

VOH_4.2V 11 3.78 4.2 4.62

Output Low Voltage

VOL_OP

RL = 15kΩ -- -- 0.2 V VOL_3.3V

VOL_1.8V

VOL_4.2V

Register-Programmable DP and DM Input Level VIN_LEV

0 -- 0 -- V

1 -- 0.4 --

Register-Programmable Input High Trip Voltage

VIH_DPDM

00 1.1 +

VIN_LEV 1.2 +

VIN_LEV 1.3 +

VIN_LEV

V

01 1.2 +

VIN_LEV 1.3 +

VIN_LEV 1.4 +

VIN_LEV

10 1.3 +

VIN_LEV 1.4 +

VIN_LEV 1.5 +

VIN_LEV

11 1.4 +

VIN_LEV 1.5 +

VIN_LEV 1.6 +

VIN_LEV

Register-Programmable Input Low Trip Voltage

VIL_ DPDM

00 0.8 +

VIN_LEV 0.9 +

VIN_LEV 1.0 +

VIN_LEV

V 01

0.9 + VIN_LEV

1.0 + VIN_LEV

1.1 + VIN_LEV

10 1.0 +

VIN_LEV 1.1 +

VIN_LEV 1.2 +

VIN_LEV

11 1.1 +

VIN_LEV 1.2 +

VIN_LEV 1.3 +

VIN_LEV

DPDM Switch On-Resistance RON_DPDM

-- -- 40 Ω

DP Comparison Threshold for Cable Detection

VTH_DP_CD Send an interrupt to MCU when cable detached

0.2 0.3 0.4 V

Register-Programmable Cable Detection Debounce Time

tDP_CD Debounce Time = tDP_CD x KtDP_CD

(Note 5)

00 -- 1 --

µs 01 -- 2 --

10 -- 4 --

11 -- 8 --

RT7205A




Register-Programmable Cable Detection Debounce Time Scale

KtDP_CD (Note 5)

00 -- 1 --

-- 01 -- 8 --

10 -- 64 --

11 -- 512 --

CC1, CC2 Section

Register-Programmable Input High Trip Voltage VIH_CC

00 0.7 0.8 0.9

V 01 0.6 0.7 0.8

10 0.5 0.6 0.7

11 0.4 0.5 0.6

Register-Programmable Input Low Trip Voltage VIL_CC

00 0.4 0.5 0.6

V 01 0.3 0.4 0.5

10 0.2 0.3 0.4

11 0.1 0.2 0.3

Register-Programmable Sourcing Current ICC_SRC

00 High Impedance

µA 01 72 80 88

10 166 180 194

11 304 330 356

CC1/CC2 Comparison Threshold for Cable Detection VCC_OP 2.5 2.6 2.7 V

USBP Section

Output High Voltage VOH_USBP VDD + 6

VDD + 8

VDD + 10

V

Register-Programmable Rise Time tR_USBP

CL = 4nF, VDD = 5V, from 20% to 80%

00 3840 4800 5760

µs 01 1920 2400 2880

10 980 1200 1440

11 480 600 720

Fall Time tF_USBP CL = 4nF, VDD = 5V, from 90% to 10%

-- -- 2 µs

Output Low Voltage VOL_USBP VDD = 2V, IUSBP = 100µA before start-up

-- -- 1 V

SR Driver Section

Output High Voltage VOH_VG ISOURE = 50mA, V9 = 9V 8.5 -- -- V

Output Low Voltage VOL_VG ISINK = 50mA, V9 = 9V -- -- 0.5 V

Rise Time tR_VG CL = 6nF, V9 = 9V, from 20% to 80%

-- 75 125 ns

Fall Time tF_VG CL = 6nF, V9 = 9V, from 80% to 20%

-- 35 85 ns

Propagation Time tP -- 100 -- ns

RT7205A




Initial Output Low Clamping Voltage before Start-up

VOL_VG_INI VDD = 2.5V, ISINK = 50mA -- -- 1 V

Internal Pull-Low Resistor RGS_LOW -- 20 -- kΩ

V_TR Section

V_TR Internal Resistance RVDS2 4.56 4.80 5.04 kΩ

V_TR Sample and Hold Error ESH_VTR (|VV_TR_HIGH - VVTR_SH| / VV_TR_HIGH) x 100

-- 5 -- %

V_TR Sample and Hold Threshold

KVTR_SH VTH_SH = KVTR_SH x VV_TR_HIGH[n-1]

-- 0.875 -- --

Mask Time tMASK VV_TR > VTH_SH -- 300 -- ns

Register-Programmable V_TR Blanking Time tBLANK_ VTR

VV_TR > VTH_SH

(Note 5)

000 0.4 0.5 0.6

µs

001 0.6 0.7 0.8

010 0.8 0.9 1.0

011 1.0 1.1 1.2

100 1.2 1.3 1.4

101 1.4 1.5 1.6

110 1.6 1.7 1.8

111 1.8 1.9 2

Register-Programmable V_TR Under Voltage Threshold VTH_VTR_UV

If VV_TR_HIGH - (VOUT x KVDS_SR) > VTH_VTR_UV, SR driver is active.

000 Disable

V

001 0.3 0.4 0.5

010 0.25 0.35 0.45

011 0.2 0.3 0.4

100 0.15 0.25 0.35

101 0.1 0.2 0.3

110 0.05 0.15 0.25

111 0 0.1 0.2

Low Level Threshold for Input Voltage

KVIN_LOW When VV_TR < KVIN_LOW x VOUT, It will send an interrupt to MCU.

2.0 2.2 2.4 --

V_TR Over-Voltage Threshold VTH_VTR_OV V9 = 4.5V 2.8 3.0 3.2 V

Low Level Threshold for V_TR Falling Edge Detection and Dead Time Comparison Threshold

VTH_VTR_DT 0.05 0.10 0.15 V

Dead Time Comparator Delay tD_DT (Note 5) -- -- 40 ns

Dead Time Comparator Blanking Time

tBLANK_DT Disable dead time comparator on VG rising edge

-- 700 -- ns

RT7205A




Register-Programmable V_TR Falling Time Threshold

tV_TR_FALLING If V_TR falling time < tV_TR_FALLING, VG will be triggered.

00 200 250 300

ns 01 150 200 250

10 100 150 200

11 50 100 150

Register-Programmable V_TR Falling Edge Debouce Time

tD_VTR 0 -- 0.15 --

µs 1 -- 0 --

V_TR Rising Edge Threshold for AC OFF Detection

VV_TR_EDGE 0.05 0.1 0.15 V

V_TR Rising Edge Debouce Time for AC OFF Detection

tV_TR_EDGE

If VV_TR in tV_TR_EDGE is lower than VV_TR_EDGE, It will send an AC OFF interrupt to MCU.

20 26 32 ms

SR Control Section

SR MOSFET VDS Scaling Factor

KVDS_SR

RVDS2 / (RVDS1 + RVDS2) For RT7205A (Note 5)

-- 1/26 --

-- RVDS2 / (RVDS1 + RVDS2) For RT7205AL (Note 5)

-- 1/13 --

Register-Programmable gm Ratio

V_TR

VOUT

gm

gm

0 3.84 4.17 4.50 --

1 3.22 3.57 3.92

Maximum VG Pulse Width Expansion Limit tSRON_MAX

tSR_ON[n] < tSR_ON[n-1] x tSRON_MAX (Note 5)

-- 106 -- %

Register-Programmable V_TR Pulse Width Expansion/Shrink Limit

tPWLMT_VTR

If tV_TR[n] > tV_TR[n-1]

+ tPWLMT_VTR or tV_TR[n] < tV_TR[n-1] - tPWLMT_VTR, reset automatic tracking counter (Note 5)

00 -- 0.3 --

µs 01 -- 0.5 --

10 -- 0.7 --

11 -- 0.9 --

Register-Programmable Minimum Period tPERIOD_MIN

Interval limit from V_TR rising edge to VG falling edge. The clock period is based on fOSC_MCU and can be set by the 12-bit register. (Note 5)

-- 190 -- µs

Register-Programmable VG Inhibit Time

tINHIBIT_SR

Interval limit from VG rising edge to next VG rising edge The clock period is based on fOSC_MCU and can be set by the 9-bit register. (Note 5)

-- 24 -- µs

RT7205A



Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-

thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the

exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. Guaranteed by design.


PLL Function Section

Register-Programmable PLL Dead Time tDEAD_PLL

If VG falling edge to VTH_VTR_DT interval < tDEAD_PLL, reset automatic tracking counter (Note 5)

00 -- 1100 --

ns 01 -- 600 --

10 -- 300 --

11 Disable

Register-Programmable Fault PLL Ratio KFAULT_PLL

If tPW M[n] > KFAULT_PLL x tPW M[n-1], VG will skipped two cycles and reset automatic tracking counter (Note 5)

0 -- 1.5 --

--

1 Disable

Automatic Tracking Section

Register-Programmable Auto-Tracking Dead Time tDEAD_TRACK

VG falling edge to VTH_VTR_DT interval (Note 5)

00 -- 1500 --

ns 01 -- 1000 --

10 -- 700 --

11 -- 400 --

Maximum Step Time for Tracking Up/Down With respect to VREF_CV 0.5 -- 1 %

RT7205A



Typical Application CircuitL N

34

Opt

iona

l

GA

TE

CS

/O

TP

GN

D

DM

AG

CO

MP

4

1 32

6R

T77

52 VD

D5

+

21

AG

ND

OPTO

V_T

R

CS

+

CS

-

D-

D+

CC

_GN

D

V2

VD

D

VD

D

US

BP

CC1

CC2

RT

IFB

VFB

BLD

PGND

VG

V9

VCP

V5

OV

P

RT

7205

A

N-M

OS

FE

T

+

VB

US

GN

D

CC

1

CC

2

D+

D-

Opt

iona

l

1 2 3 4 5 6

78

910

1112

131415161718

1920

2122

2324

RT7205A



Typical Operating Characteristics

VVDD_ON vs. Temperature

2.99

3.00

3.01

3.02

3.03

-50 -25 0 25 50 75 100 125Temperature (°C)

VV

DD

_ON (V

)

VVDD_OFF vs. Temperature

2.69

2.70

2.71

2.72

2.73

-50 -25 0 25 50 75 100 125Temperature (°C)

VV

DD

_OF

F (

V)

VVDD_HYS vs. Temperature

0.27

0.28

0.29

0.30

0.31

-50 -25 0 25 50 75 100 125Temperature (°C)

VV

DD

_HY

S (V

)

IDD_START vs. Temperature

150

175

200

225

250

-50 -25 0 25 50 75 100 125Temperature (°C)

I DD

_ST

AR

T (µ

A)

IDD_OP vs. Temperature

9.0

9.5

10.0

10.5

11.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

I DD

_OP (m

A)

IDD_SLEEP vs. Temperature

600

750

900

1050

1200

-50 -25 0 25 50 75 100 125

Temperature (°C)

I DD

_SLE

EP (µ

A)

RT7205A



VVDD_OVP vs. Temperature

14.5

15.0

15.5

16.0

16.5

-50 -25 0 25 50 75 100 125Temperature (°C)

VV

DD

_OV

P (V

)

VVDD_OVP_SR vs. Temperature

100

105

110

115

120

-50 -25 0 25 50 75 100 125

Temperature (°C)

VV

DD

_OV

P_S

R (

%)

fOSC_MCU vs. Temperature

20.00

20.75

21.50

22.25

23.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

f OS

C_M

SU

(MH

z)

VBIAS_V5 vs. Temperature

4.8

4.9

5.0

5.1

5.2

-50 -25 0 25 50 75 100 125

Temperature (°C)

VB

IAS

_V5

(V)

V5 Load Regulation vs. Temperature

50

60

70

80

90

-50 -25 0 25 50 75 100 125

Temperature (°C)

V5

Loa

d R

egu

latio

n (m

V)

IV5_SC vs. Temperature

60

75

90

105

120

-50 -25 0 25 50 75 100 125Temperature (°C)

I V5_

SC (m

A)

RT7205A



VBIAS_V2 vs. Temperature

1.70

1.75

1.80

1.85

1.90

-50 -25 0 25 50 75 100 125

Temperature (°C)

VB

IAS

_V2

(V)

V2 Load Regulation vs. Temperature

0.00

1.25

2.50

3.75

5.00

-50 -25 0 25 50 75 100 125Temperature (°C)

V2

Lo

ad

Re

gu

latio

n (

mV

)IV2_SC vs. Temperature

30

35

40

45

50

-50 -25 0 25 50 75 100 125Temperature (°C)

I V2_

SC (m

A)

RFB1 vs. Temperature

0

20

40

60

80

100

120

-50 -25 0 25 50 75 100 125

Temperature (°C)

RF

B1

(kΩ

)

RFB2 vs. Temperature

18

19

20

21

22

-50 -25 0 25 50 75 100 125

Temperature (°C)

RF

B2

(kΩ

)

KVOUT vs. Temperature

2

3

4

5

6

-50 -25 0 25 50 75 100 125

Temperature (°C)

KV

OU

T

RT7205A

RT7205AL

RT7205A

RT7205AL

RT7205A



VREF_CV_ST vs. Temperature

0.5

1.0

1.5

2.0

2.5

-50 -25 0 25 50 75 100 125Temperature (°C)

VR

EF

_CV

_ST (V

)

VREF_CC_ST vs. Temperature

0.6

0.8

1.0

1.2

1.4

-50 -25 0 25 50 75 100 125

Temperature (°C)

VR

EF

_CC

_ST (V

)VREF_CV_MAX vs. Temperature

2.60

2.65

2.70

2.75

2.80

-50 -25 0 25 50 75 100 125Temperature (°C)

VR

EF

_CV

_MA

X (V

)

VREF_CC_MAX vs. Temperature

2.60

2.65

2.70

2.75

2.80

-50 -25 0 25 50 75 100 125

Temperature (°C)

VR

EF

_CC

_MA

X (V

)

VADC_MAX vs. Temperature

2.60

2.65

2.70

2.75

2.80

-50 -25 0 25 50 75 100 125

Temperature (°C)

VA

DC

_MA

X (V

)

RON_OPTO vs. Temperature

110

130

150

170

190

-50 -25 0 25 50 75 100 125

Temperature (°C)

RO

N_O

PT

O (Ω

)

RT7205A

RT7205AL

0 : 0.8V

1 : 1.1V

RT7205A



ROPTO_VDD vs. Temperature

47

49

51

53

55

-50 -25 0 25 50 75 100 125Temperature (°C)

RO

PT

O_V

DD (kΩ

)

ROPTO_GND vs. Temperature

57

59

61

63

65

-50 -25 0 25 50 75 100 125Temperature (°C)

RO

PT

O_G

ND (kΩ

)CS Gain vs. Temperature

36

37

38

39

40

41

42

43

44

-50 -25 0 25 50 75 100 125

Temperature (°C)

CS

Ga

in

VOFFSET_CS vs. Temperature

0.525

0.550

0.575

0.600

0.625

-50 -25 0 25 50 75 100 125Temperature (°C)

VO

FF

SE

T_C

S (V

)

fCP vs. Temperature

160

165

170

175

180

-50 -25 0 25 50 75 100 125

Temperature (°C)

f CP (k

Hz)

tR_CP vs. Temperature

110

130

150

170

190

-50 -25 0 25 50 75 100 125Temperature (°C)

t R_C

P (n

s)

RT7205A



tF_CP vs. Temperature

80

100

120

140

160

-50 -25 0 25 50 75 100 125

Temperature (°C)

t F_C

P (

ns)

VV9_ON vs. Temperature

3.20

3.25

3.30

3.35

3.40

-50 -25 0 25 50 75 100 125Temperature (°C)

VV

9_O

N (V

)VV9_OFF vs. Temperature

3.05

3.10

3.15

3.20

3.25

-50 -25 0 25 50 75 100 125Temperature (°C)

VV

9_O

FF (V

)

VRT_OP vs. Temperature

3.4

3.5

3.6

3.7

3.8

-50 -25 0 25 50 75 100 125

Temperature (°C)

VR

T_O

P (

V)

IBIAS_RT vs. Temperature

0

20

40

60

80

100

120

-50 -25 0 25 50 75 100 125Temperature (°C)

I BIA

S_R

T (µ

A)

RL_OVP vs. Temperature

120

135

150

165

180

-50 -25 0 25 50 75 100 125Temperature (°C)

RL_

OV

P (Ω

)

00 : 100µA

01 : 20µA

10 : 4µA

RT7205A



VVOUT_OVP vs. Temperature

110

115

120

125

130

-50 -25 0 25 50 75 100 125

Temperature (°C)

VV

OU

T_O

VP

(%)

RL_BLD vs. Temperature

14

18

22

26

30

-50 -25 0 25 50 75 100 125Temperature (°C)

RL_

BLD

(Ω

)RH_DPDM vs. Temperature

12.00

12.25

12.50

12.75

13.00

-50 -25 0 25 50 75 100 125Temperature (°C)

RH

_DP

DM (kΩ

)

RL_DPDM vs. Temperature

18

19

20

21

22

-50 -25 0 25 50 75 100 125

Temperature (°C)

RL_

DP

DM

(kΩ

)

VOH_DPDM vs. Temperature

1.50

2.00

2.50

3.00

3.50

4.00

4.50

5.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

VO

H_D

PD

M (V

)

VOL_DPDM vs. Temperature

35

40

45

50

55

-50 -25 0 25 50 75 100 125

Temperature (°C)

VO

L_D

PD

M (

mV

)

00 : 115%

01 : 120%

10 : 125%

11 : VOH_4.2V

01 : VOH_3.0V

10 : VOH_1.8V

VOL_1.8VVOL_3.0VVOL_4.2V

RT7205A



VIH_DPDM vs. Temperature

1.1

1.2

1.3

1.4

1.5

1.6

-50 -25 0 25 50 75 100 125

Temperature (°C)

VIH

_DP

DM (

V)

VIH_DPDM vs. Temperature

1.5

1.6

1.7

1.8

1.9

2.0

-50 -25 0 25 50 75 100 125Temperature (°C)

VIH

_DP

DM (V

)VIL_DPDM vs. Temperature

0.8

0.9

1.0

1.1

1.2

1.3

-50 -25 0 25 50 75 100 125Temperature (°C)

VIL

_DP

DM (V

)

VIL_DPDM vs. Temperature

1.2

1.3

1.4

1.5

1.6

1.7

-50 -25 0 25 50 75 100 125

Temperature (°C)

VIL

_DP

DM (V

)

RON_DPDM vs. Temperature

29

30

31

32

33

-50 -25 0 25 50 75 100 125Temperature (°C)

RO

N_D

PD

M (Ω

)

VTH_DP_CD vs. Temperature

0.20

0.25

0.30

0.35

0.40

-50 -25 0 25 50 75 100 125

Temperature (°C)

VT

H_D

P_C

D (

V)

11 : 1.5V

10 : 1.4V

01 : 1.3V

00 : 1.2V

11 : 1.5V + 0.4V

10 : 1.4V + 0.4V

01 : 1.3V + 0.4V

00 : 1.2V + 0.4V

11 : 1.2V

10 : 1.1V

01 : 1.0V

00 : 0.9V

11 : 1.2V + 0.4V

10 : 1.1V + 0.4V

01 : 1.0V + 0.4V

00 : 0.9V + 0.4V

RT7205A



VIH_CC vs. Temperature

0.4

0.5

0.6

0.7

0.8

0.9

-50 -25 0 25 50 75 100 125

Temperature (°C)

VIH

_CC

(V)

VIL_CC vs. Temperature

0.1

0.2

0.3

0.4

0.5

0.6

-50 -25 0 25 50 75 100 125

Temperature (°C)

VIL

_CC (V

)ICC_SRC vs. Temperature

60

90

120

150

180

210

240

270

300

330

360

-50 -25 0 25 50 75 100 125

Temperature (°C)

I CC

_SR

C (µ

A)

VCC_OP vs. Temperature

2.45

2.50

2.55

2.60

2.65

-50 -25 0 25 50 75 100 125Temperature (°C)

VC

C_O

P (V

)

VOH_USBP vs. Temperature

11

12

13

14

15

-50 -25 0 25 50 75 100 125Temperature (°C)

VO

H_U

SB

P (V

)

tR_USBP vs. Temperature

0

600

1200

1800

2400

3000

3600

4200

4800

5400

-50 -25 0 25 50 75 100 125

Temperature (°C)

t R_U

SB

P (µ

s)

11 : 0.5V

10 : 0.6V

01 : 0.7V

00 : 0.8V

11 : 0.2V

10 : 0.3V

01 : 0.4V

00 : 0.5V

01 : 80µA

10 : 180µA

11 : 330µA

00 : 4800µs

01 : 2400µs

10 : 1200µs

11 : 600µs

RT7205A



tF_USBP vs. Temperature

0.50

0.75

1.00

1.25

1.50

-50 -25 0 25 50 75 100 125Temperature (°C)

t F_U

SB

P (µ

s)

VOL_USBP vs. Temperature

0.5

0.6

0.7

0.8

0.9

1.0

-50 -25 0 25 50 75 100 125Temperature (°C)

VO

L_U

SB

P (V

)tR_VG vs. Temperature

50

70

90

110

130

-50 -25 0 25 50 75 100 125Temperature (°C)

t R_V

G (n

s)

tF_VG vs. Temperature

40.0

42.5

45.0

47.5

50.0

-50 -25 0 25 50 75 100 125Temperature (°C)

t F_V

G (n

s)

VOL_VG_INI vs. Temperature

0.00

0.25

0.50

0.75

1.00

-50 -25 0 25 50 75 100 125

Temperature (°C)

VO

L_V

G_I

NI (

V)

RGS_LOW vs. Temperature

0

10

20

30

40

-50 -25 0 25 50 75 100 125Temperature (°C)

RG

S_L

OW

(kΩ

)

RT7205A



RVDS2 vs. Temperature

4.6

4.7

4.8

4.9

5.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

RV

DS

2 (kΩ

)

ESH_VTR vs. Temperature

-3

-2

-1

0

1

-50 -25 0 25 50 75 100 125

Temperature (°C)

ES

H_V

TR (

%)

KVTR_SH vs. Temperature

0.86

0.87

0.88

0.89

0.9

-50 -25 0 25 50 75 100 125Temperature (°C)

KV

TR

_SH

tMASK vs. Temperature

280

290

300

310

320

-50 -25 0 25 50 75 100 125

Temperature (°C)

t MA

SK

(ns)

VTH_VTR_UV vs. Temperature

50

100

150

200

250

300

350

400

450

-50 -25 0 25 50 75 100 125

Temperature (°C)

VT

H_V

TR

_UV

(mV

)

KVIN_LOW vs. Temperature

2.1

2.2

2.3

2.4

2.5

-50 -25 0 25 50 75 100 125Temperature (°C)

KV

IN_L

OW100 : 0.25V

110 : 0.15V

101 : 0.2V

011 : 0.3V

111 : 0.1V

001 : 0.4V

010 : 0.35V

RT7205A



VTH_VTR_OV vs. Temperature

2.8

2.9

3.0

3.1

3.2

-50 -25 0 25 50 75 100 125

Temperature (°C)

VT

H_V

TR

_OV

(V)

VTH_VTR_DT vs. Temperature

0.00

0.05

0.10

0.15

0.20

-50 -25 0 25 50 75 100 125

Temperature (°C)

VT

H_V

TR

_DT

(V)

tBLANK_DT vs. Temperature

600

700

800

900

1000

-50 -25 0 25 50 75 100 125

Temperature (°C)

t BLA

NK

_DT

(ns)

tV_TR_FALLING vs. Temperature

50

100

150

200

250

300

-50 -25 0 25 50 75 100 125Temperature (°C)

t V_T

R_F

ALL

ING (

ns)

VV_TR_EDGE vs. Temperature

0.09

0.10

0.11

0.12

0.13

-50 -25 0 25 50 75 100 125Temperature (°C)

VV

_TR

_ED

GE (V

)

tV_TR_EDGE vs. Temperature

23

24

25

26

27

-50 -25 0 25 50 75 100 125

Temperature (°C)

t V_T

R_E

DG

E (

ms)

00 : 250ns

01 : 200ns

10 : 150ns

11 : 100ns

RT7205A



gmV_TR / gmVOUT vs. Temperature

3.0

3.3

3.6

3.9

4.2

4.5

-50 -25 0 25 50 75 100 125Temperature (°C)

gm

V_T

R /

gm

VO

UT

Maximum Step Tracking vs. Temperature

0.5

0.6

0.7

0.8

0.9

-50 -25 0 25 50 75 100 125

Temperature (°C)

Max

imum

Ste

p T

rack

ing

(%) 1

0 : 4.17

1 : 3.57

RT7205A



programmed by chargers' requirements.

Both the constant-voltage and constant-current

compensation loops are connected together at the OPTO

pin. The OPTO driver sinks current through an optocoupler

and an external resistor RD from output voltage, and the

optocoupler isolates the secondary side from the primary

side and also provide the feedback compensation signal

for the primary side. Note that for better linearity of the

loop compensation range, RD should be designed to cover

for operation at the minimum output voltage.

CTR : Current transfer ratio of the optocoupler

VF : Forward voltage of the optocoupler

0.3V : The minimum OPTO voltage for the OPTO driver to

sink 2mA.

ICOMP_MAX : The maximum COMP sourcing current of a

traditional PWM controller in the primary side. It is a current

sourced from an internal bias through a built-in pull-high

resistor connected the COMP pin in the PWM controller.

Figure 6. CV Loop and Current-Sense Amplifier

Application Information

Constant-Voltage (CV) Loop

The RT7205A incorporates 2 error amplifiers (EA) to

regulate output voltage and current, respectively. The output

voltage is determined as :

VOUT = KVOUT x VREF_CV

Where

For the RT7205A, KVOUT = (RFB1 + RFB2) / RFB2 = 5 (typ)

For the RT7205AL, KVOUT = (RFB1 + RFB2) / RFB2 = 2.5 (typ)

Therefore, the VOUT is determined by VREF_CV, the analog

output from the DAC, and its digital counterpart, which is

controlled by the MCU, as shown in Functional Block

Diagram.

Constant-Current (CC) Loop and Current-Sense

Amplifier

The RT7205A integrates a virtually-zero input-offset-voltage

current-sense amplifier with differential-mode inputs to

minimize noise interference. The amplified output current

sense signal, sent to an ADC for A/D conversion, is

monitored and processed by the MCU, and is also sent

to the CC loop. The reference voltage of the CC loop is

determined by VREF_CC (from the DAC), which is

OUT_MIN FCOMP_MAX

D

V V 0.3VCTR I

R

− −× ≥

ROPTO_VDD

VOFFSET_CS = 0.5V

VREF_CC10-bit DAC

ROPTO_GND

IFB

CS Gain = 40

+-

A

Io_signal

+

-

VDD UVLO

VDD UVLO

+

-

VREF_CV10-bit DAC

RFB1

RFB2

VDDVFBOPTOCS+CS-

RD

RVCV

CCS

RSENSE

RCS+RCS-

VOUTGND

RCCC

RT7205A



Figure 7. The Bias Voltages Sequence during Start-Up

Power-Up Sequence

Once a Type-C cable is attached, the UFP will deliver

voltage and current settings to the RT7205A for the MCU

to decode and to program reference voltages, VREF_CV

and VREF_CC, for the CV and CC loops, which are the

analog outputs converted by the DAC. If the Type-C cable

is detached, or the output current is lower than the power-

saving mode threshold, which is typically programmed as

200mA, the RT7205A will enter power-saving mode, under

which the RT7205A operates at ultra-low operating current

and thus the total input power can be saved. If the output

current increases and exceeds the power-saving mode

threshold, or any input/output signal is toggled, the

RT7205A will exit power-saving mode.

Internal Biases and Charge Pump

The RT7205A provides three regulated bias voltages, V5,

V2, and V9. The V5 bias voltage is the output of a linear

regulator powered by VDD, and supplies the internal analog

circuit and the charge pump driver. The V2 bias voltage is

the output of a linear regulator powered by V5, and supplies

the MCU. As shown in Figure 8, the RT7205A also

integrates a charge pump circuit to generate V9 to supply

for the SR driver when VDD is at lower levels, such as 3V

Figure 8. Charge Pump Circuit

Output Voltage Rises and Falls

When the protocol is detected, the reference voltage

VREF_CV can be set by the request of the UFP. Both the

rise time and fall time of output voltages should be less

than define specification, as shown in Figure 9.

(a) Output Voltage Rising

VOUT

(VDD)

t

t

5V

12V

1V

2.4V

< tRise

VREF_CV Slope (2.4V-1V) / tRise≥

CCP

DCP1 DCP2

ROUT_CPfCP

SR Gate

CV2

V5 LDO

V2 LDO

VCP V9V5V2

VGVDD

CV5 CV9

VDD

tIOUT

t

5V

VVDD_ON

Power-saving mode threshold

V5

t

Debounce time to enter power-saving mode

V2

t

Power-Saving Mode

t

V9

t

to 5V. If the RT7205A enters power-saving mode, the

charge pump driver will be disabled.

The minimum source/sink capability of the charge pump

driver is around 10mA at 170kHz of charge pump operating

frequency fCP. Bypass capacitors on the V5, V2 and V9

pins are required to minimize output ripples of the biases.

V9 = V5 x 2 - VF_DCP1 - VF_DCP2 - IV9 x ROUT_CP

When output voltage is set at lower levels (< 5V), V5 will

be lower, following VDD by a voltage drop of a dropout

voltage of the LDO. For higher V9, a lower forward voltage

for the Schottky diodes, DCP1 and DCP2, is required.

The RT7205A provides V5 short-circuit protection against

the condition that the V5, V2, or VCP pin is shorted to

GND, and also provides under-voltage protection for V9. If

the V9 voltage is below VV9_SRON (typical 4.5V), the SR

driver will be turned off by firmware, that is, VG will be

inactivated.

RT7205A



Figure 10. Application Circuit of an Active Dummy Load

Figure 9. Output Voltage Transient Waveforms

(b) Output Voltage Falling

During the time of VOUT falling, as shown in Figure 10, the

BLD driver will be turned on as a dummy load to provide

an extra discharging path for the output capacitor so that

VOUT can be settled in a shorter duration. The resistance

of RDUMMY can be calculated as below :

2 x COUT x (RDUMMY + RL_BLD) < tFall

DOL

DI

BLD

DIEN

+

CO

+

-

VOUTRDUMMY

During the time of VOUT rising or falling, the SR driver will

be turned off. After a firmware programmable delay time

300ms, the RT7205A will sense the load condition and

may reactivate the SR driver.

Temperature Sensing and Thermal Protection

The RT7205A provides the RT pin for over-temperature

protection or thermal monitoring. As shown in Figure 2,

the RT pin sources a constant bias current for a remote

thermal sensor of an NTC thermistor, connected from the

RT pin to GND, for temperature sensing. If the RT voltage

is below a programmable threshold voltage and the

condition sustains for a programmable deglitch time, over-

temperature protection will be triggered.

The bias current through the RT pin can be programmed

as 100µA, 20µA, or 4µA by setting the internal register.

With the appropriate bias current setting, linearity of

temperature sensing over the temperature range of 25°C

to 100°C can be improved. The RT7205A can deliver the

sensed RT voltage data back to the UFP via the protocol

(Vendor Defined Message), if necessary. Figure 11 shows

the RT voltages vary with temperature at three different

bias currents with an NTC thermistor TTC104 as an

example.

2.5V

0.4V

1V

2V

100°C50°C0°C

20µA4µA 100µA

VRT

Temperature

Figure 11. The RT Voltages vs. Temperature at Three

Bias Currents

Blocking N-MOSFET Control (USBP)

RT7205A provides a push-pull driver for controlling external

blocking N-MOSFET as shown in the Figure 12. The push-

pull driver not only can control N-MOSFET smooth turn-

on to avoid VOUT drops in the capacitive load condition

but also provide quickly turn-off in any fault condition.

VOUT(VDD)

tVREF_CV

t

5V

12V

1V

2.4V

< tFallSR EN

tVBLD

t

300ms (Programmable)

200µs

≤

≈

Slope (1V-2.4V) / tFall

RT7205A



Figure 12. Blocking N-MOSFET Control

Output Over-Voltage Protection

As shown in the Figure 13 and Figure 14, the RT7205A

provides the OVP pin as a backup VOUT over-voltage

protection, in case the optocoupler of the feedback loop

is malfunction due to aging. If the internal voltage related

to VDD is higher by the programmable threshold VVOUT_OVP,

the OVP pin will be pulled low. The OVP pin voltage will

be latched low until the VDD voltage drops below the VDD

turn-off threshold VVDD_OFF.

Figure 13. Timing Sequence of the OVP Function

Figure 14. OVP Pin Block Diagram

Once the communication is set up with an UFP, or a 5.1kΩresistor at the CC1/CC2 pin of a Type-C connector of the

UFP is detected, the N-MOSFET will be turned on. If VOUT

over-voltage condition occurs, the blocking N-MOSFET

will be turned off to prevent the UFP from being damaged

by the VOUT over-voltage condition. If VOUT is shorted to

GND, the N-MOSFET will also be turned off automatically

so that output power can be limited.

RFB1

RFB2

ROPTO_VDD

RVCV

RD

R1

R2

ROVP

10-bit ADC

00 : 115%01 : 120%10 : 125%

VDDVFBOPTO OVP

VDD UVLO

MCU

INT_VDDOV+

-

AVREF_CV10-bit DAC

+

-

VOUT

BLD_EN

S

R

Q

Q

ControlFault

VDD

VDD- V

USBP

VBUSVOUT

∆

VOUT

(VDD)

t

tD_VOUTOVP

VOVP

t

INT_VDDOV

t

VVDD_OFF

OV Hysteresis

The debounce time of latched OPTO by MCU is around 50µs

RT7205A



Figure 14. Derating Curve of Maximum Power

Dissipation

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0 25 50 75 100 125

Ambient Temperature (°C)

Ma

xim

um

Po

we

r D

issi

pa

tion

(W) 1 Four-Layer PCB

Thermal Considerations

The junction temperature should never exceed the

absolute maximum junction temperature TJ(MAX), listed

under Absolute Maximum Ratings, to avoid permanent

damage to the device. The maximum allowable power

dissipation depends on the thermal resistance of the IC

package, the PCB layout, the rate of surrounding airflow,

and the difference between the junction and ambient

temperatures. The maximum power dissipation can be

calculated using the following formula :

PD(MAX) = (TJ(MAX) − TA) / θJA

where TJ(MAX) is the maximum junction temperature, TA is

the ambient temperature, and θJA is the junction-to-ambient

thermal resistance.

For continuous operation, the maximum operating junction

temperature indicated under Recommended Operating

Conditions is 125°C. The junction-to-ambient thermal

resistance, θJA, is highly package dependent. For a

WQFN-24L 4x4 package, the thermal resistance, θJA, is

28°C/W on a standard JEDEC 51-7 high effective-thermal-

conductivity four-layer test board. The maximum power

dissipation at TA = 25°C can be calculated as below :

PD(MAX) = (125°C − 25°C) / (28°C/W) = 3.57W for a

WQFN-24L 4x4 package.

The maximum power dissipation depends on the operating

ambient temperature for the fixed TJ(MAX) and the thermal

resistance, θJA. The derating curves in Figure 14 allows

the designer to see the effect of rising ambient temperature

on the maximum power dissipation.

RT7205A



Outline Dimension

A

A1

A3

D

E

D2

E2

L

be

1

SEE DETAIL A

W-Type 24L QFN 4x4 Package

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

DETAIL A

Pin #1 ID and Tie Bar Mark Options

11

2 2

Symbol Dimensions In Millimeters Dimensions In Inches

Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 3.950 4.050 0.156 0.159

D2 Option 1 2.400 2.500 0.094 0.098

Option 2 2.650 2.750 0.104 0.108

E 3.950 4.050 0.156 0.159

E2 Option 1 2.400 2.500 0.094 0.098

Option 2 2.650 2.750 0.104 0.108

e 0.500 0.020

L 0.350 0.450 0.014 0.018

RT7205AX


Richtek Technology Corporation14F, No. 8, Tai Yuen 1st Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

Footprint Information

P Ax Ay Bx By C D Sx Sy

Option1 2.55 2.55

Option2 2.60 2.604.80

ToleranceFootprint Dimension (mm)Number of

PinPackage

±0.05V/W/U/XQFN4*4-24 3.10 3.10 0.85 0.3024 0.50 4.80

programmable smps and usb type-c controller...rt7205a integrate s an mcu to ha ndle various...

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