programmable logic devices and architectures: a nano-course r. katz grunt engineer nasa
TRANSCRIPT
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Programmable Logic Devices and Architectures:
A Nano-Course
R. Katz
Grunt Engineer
NASA
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What We Will Cover
• Various programmable logic types
• Device architectures
• Device performance
• Packaging
• Reliability
• Some radiation considerations
• Lessons learned
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What You Will Not Learn
You will not learn much. This course is only a brief introduction to key concepts and issues, not a comprehensive and in-depth tutorial.
Because of time limitations, sections have been either scaled back or eliminated.
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References
References are available for most slides
• Original work– available on http://rk.gsfc.nasa.gov
• Manufacturers’ data sheets, application notes
• Papers and reports– Many from MAPLD 1998, 1999, 2000
• Standard logic design textbooks
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Lessons Learned (1)
Barto's Law: Every circuit is considered guilty until proven innocent.
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Lessons Learned (2)
Launched: March 4, 1999Failed: March 4, 1999
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Applications Some Application Types
• Existing SSI/MSI Integration• Obsolete/"Non-Space-Qualified" Component
Replacement• Bus Controllers/Interfaces• Memory Controller/Scrubber• High-Performance DSP• Processors• Systems on Chip• Many Other Digital Circuits
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SSI/MSI Logic Integration
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Non-Space Qual Microcontroller
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Complex System-on-Chip
SSTL CoreESA Core
Debug
CAN Network >100Mbps
170MbyteMicrodrive
TX
TCSP1M*64 SRAM
CAN BUS LVDS
RX2RX1RX0
Linear Regulator
POR
+3.3V
EDACDECDED
ROM LUTBootstrap
AMBA AHB
CANInterface
AMBA AHB
LEON Sparc V8 CORDICCoprocessor
AMBA AHB
AMBA AHB
HDLC TXController
AMBA AHB
HDLC RXController
FIFO
AMBA AHB
HDLC RXController
FIFO
AMBA AHB
HDLC RXController
FIFO
System Bus
CF+ I/FTrue IDE
FIFO
Parallel PortInterface
UART
AMBA AHB
PIO
FIFO
AMBA AHB
+2.5V +3.3V
CLK CLK CLK CLK
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Programmable Elements Overview• Antifuse
– ONO and Metal-to-Metal (M2M)– Construction– Resistance
• SRAM– Structure– Quantity
• EEPROM/Flash• Ferroelectric Memory• Summary of Properties
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Antifuse Technology
ONO Antifuse (Actel)Poly/ONO/N++Heavy As doped Poly/N++Thickness controlled by CVD nitridePrograms ~ 18VTypical Toxono ~ 85 ÅHardened Toxono ~ 95 ÅR = 200 - 500 ohms
thermal oxide
CVD nitride
thermal oxide
FOX
N++
PolysiliconONO
Metal-to-Metal Antifuse (Actel, UTMC, Quicklogic)‘Pancake’ Stack Between Metal LayersUsed in 3.3V Operation in Sea Of Gates FPGAOther devices (as shown later)Program at ~ 10VTypical thickness ~ 500 - 1000 Å
R = 20 - 100 ohms
Metal - 3 Top Electrode
Amorphous Silicon
Dielectric (optional)
Metal - 2 Bottom Electrode
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Antifuse Cross-Sections
Amorphous Silicon(Vialink)
ONO(Act 1)
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M2M = Metal-to-metal
M2M Antifuse inMulti-layer Metal Process
SX, SX-A, and SX-S Vialink
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Programmed Antifuse Resistance Distributions
The resistance of programmed antifuses is stable with temperature,varying less than 15 percent per 100°C.
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SRAM Switch Technology
Read or Write
Data
Configuration Memory Cell
Routing Connections
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Summary of Current Technology
Type Re-programmable Volatile Technology Radiation Hardness
Fuse No No Bipolar Hard
EPROM Yes No UVCMOS Moderate
EEPROM YES, ICP No EECMOS Moderate
SRAM YES, ICP Yes CMOS Soft
Antifuse No No CMOS+ Hard
FRAM Yes, ICP No Perovskite Hard1
Ferroelectric Crystal
1Get Bennedetto paper to verify.
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FPGA Architecture• Assembly of Fundamental Blocks
– Hierarchical
– Integration of Different Building Blocks• Logic (Combinational and Sequential)
• Dedicated Arithmetic Logic
• Clocks
• Input/Ouput
• Delay Locked Loop
• RAM
• Routing (Interconnections) – Channeled Architecture
– Sea-of-Module Architecture
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Channel Architecture
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Channeled Routing Structure
ProgrammedAntifuse
HorizontalTrack
Vertical Track
Modules
UnprogrammedAntifuse
Modules
Horizontal Control
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Act 3 Architecture Detail
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Sea-of-Modules Structure
• Some programmable elements require silicon resources– SRAM flip-flops– ONO antifuse
• Metal-to-metal antifuses are built above the logic– No routing channels– Higher density– Faster
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UT4090 Architecture
RAM Blocks
Logic Array
RAM Blocks
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Virtex Architecture Overview
IOB = I/O BlockDLL = Delay-locked loopBRAM = Block RAM (4,096 bits ea.)CLB = Configurable Logic Block
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Two Slice Virtex CLB
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Logic Modules
• Actel (Act 1,2,3, SX)– Basics
– Flip-flop Construction
• UTMC/Quicklogic (i.e., UT4090)– RAM blocks
• Xilinx (i.e., CQR40xxXL, Virtex)– LUTs/RAM
– Carry Logic/Chain
• Mission Research Corp. (MRC) - Orion• Atmel - AT6010
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Act 2 Logic Module: C-Mod
8-Input Combinational function
766 possible combinationalmacros1
1”Antifuse Field Programmable Gate Arrays,” J. Greene, E. Hamdy, and S. Beal,Proceedings of the IEEE, Vol. 91, No. 7, July 1993, pp. 1042-1056
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Act 2 Flip-flop Implementation
Hard-wired Flip-flop
Feedback goes throughantifuses (R) and routing
segments (C)
Routed or “C-C Flip-flop”
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SX-S R-Cell Implementation
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UT4090 Logic Module
• Antifuse Configuration Memory
• Mux-based
• Multiple Outputs
• Wide logic functions
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UT4090 RAM Module
• Dual-port
• 1152 bits per cell
• Four configurations– 64 X 18– 128 X 9– 256 X 4– 512 X 2
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XC4000 Series CLBSimplified CLB - Carry Logic Not Shown
RAM LUTsfor Logic orsmall SRAM Two Flip-flops
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XQR4000XL Carry Path
General interconnect
Placement is important for performance.
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Carry Logic Operation
Effective Carry Logic for a Typical Addition - XQR4000XL
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MRC Orion Logic Module
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AT60xx Logic Module
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Memory Architecture
• Radiation-hardened PROM
• Configuration memory
• EEPROM
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Rad-Hard PROM Architecture
No latches in this architecture
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Configuration PROM Example
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W28C64 EEPROMSimplified Block Diagram
RowAddressLatches
ColumnAddressLatches
A6-12
A0-5
RowAddressDecoder
ColumnAddressDecoder
EdgeDetect &Latches
ControlLatch
ControlLogic
CE*
WE*
OE*
64 BytePage
Buffer
Timer
CLK
E2
MemoryArray
I/O Buffer/Data Polling
I/O0-7
Latch Enable
PE RSTB VW
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Input/Output ModulesA Brief Overview
• Basic Input/Output (I/O) Module
• Some Features– Slew Rate Control– Different I/O Standards– Input Delays– Banks
• Deterministic Powerup
• Cold Sparing
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Act 1
• Many families have slew rate control to limit signal reflections and ground bounce.
• Different families drive their outputs to different levels.
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Different I/O Standards Virtex 2.5V Example
I/O Standard Input Ref Output Board 5V Voltage Source Termination Tolerant (VREF) Voltage Voltage (VCCO) (VTT)
LVTTL 2–24 mA N/A 3.3 N/A YesLVCMOS2 N/A 2.5 N/A YesPCI, 5 V N/A 3.3 N/A YesPCI, 3.3 V N/A 3.3 N/A NoGTL 0.8 N/A 1.2 NoGTL+ 1.0 N/A 1.5 NoHSTL Class I 0.75 1.5 0.75 NoHSTL Class III 0.9 1.5 1.5 NoHSTL Class IV 0.9 1.5 1.5 NoSSTL3 Class I &II 1.5 3.3 1.5 NoSSTL2 Class I & II 1.25 2.5 1.25 NoCTT 1.5 3.3 1.5 NoAGP 1.32 3.3 N/A No
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Virtex 2.5V
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Deterministic Power-upSX-S Example
PRE
CLR
VCCI
RTSX-S
Input Driven low or external POR Signal
Pull-down enabled
Pull-up enabled
• Pull-ups /downs are selectable on an individual I/O basis
• Pull-up follows VCCI
• Pull-downs and pull-ups are dis- abled 50 ns after VCCA reaches 2.5V and therefore do not draw current during regular operation.
• Once VCCA is powered-up, 50ns is required for a valid signal to propagate to the outputs before the pull-ups /downs are disabled
VCCA
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Cold Sparing - SX-S
RTSX-S
VCCI
GND
0 VoltsRTSX-S
VCCI
GND
3.3/5 Volts
Active Bus or Backplane
Powered-downBoard
Powered-upBoard
I/O w/ ” Hot-Swap”Enabled does not
sink current
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Packaging and Mechanical Aspects
• Package Types– Dual In-line Package (DIPs)
– Flatpacks
– Pin Grid Arrays (PGAs)
– Ceramic Quad Flat Packs (CQFP)
– Plastic Quad Flat Pack (PQFP)
• Plastic Package Qualification• Lead/Ball Pitch• Mass Characteristics• Shielding
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Flat PackNorthrop-Grumman 256k EEPROM
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Shielded Packages - Rad-Pak™
• This package, with tie bar, 24 grams• Shielding thickness may vary between lots• Shield is 10-90/copper-tungsten• Density of shield is ~ 18 g/cm3 (need to verify)• EEPROMs and other devices also packaged similarly
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Spot Shielding Qualification Board - Maximum Thickness
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PGA Packages (cont'd)
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PQFP Package
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Nominal Lead/Ball Pitch
CQ84 0.025"
CQ132 0.025"
CQ172 0.025"
CQ196 0.025"
CQ208 0.50 mm
PQ208 0.50 mm
CQ256 0.05 mm
CG560 1.27 mm
Note: Pin spacing for PGAs is typically 0.1"
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Mass CharacteristicsApproximate values (in grams)
CQ84 2.2
CQ132 5.8
CQ172 8.8
CQ196 11.1
CQ208 8.8CQ208 18.5PQ208 5.2 CB228 17.6CQ256 13.0CQ256 20.21With heat sink. Over the years, there has been a lot of variation as to which parts have heat sinks. Check each package.
PG84 8.0
PG133 11.0
PG176 19.0
PG207 24.5
PG257 27.3
1
1
BG560 11.5CG560 11.5
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Reliability
• Introduction to Reliability
• Historical Perspective
• Current Devices
• Trends
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The Bathtub Curve
Time
Failurerate,
Constant
Useful life Wear outInfant
Mortality
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Introduction to Reliability
• Failure in time (FIT)Failures per 109 hours
( ~ 104 hours/year )
• Acceleration Factors– Temperature– Voltage
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Introduction to Reliability (cont'd)
Most failure mechanisms can be modeled using the Arrhenius equation.
ttf - time to failure (hours)
C - constant (hours)
EA - activation energy (eV)
k - Boltzman's constant (8.616 x 10-5eV/°K)
T - temperature (ºK)
ttf = C • eEA/kT
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Integrated Circuit ReliabilityHistorical Perspective
Application Reliability
• Apollo Guidance Computer < 10 FITs• Commercial (1971) 500 Hours• Military (1971) 2,000 Hours• High Reliability (1971) 10,000 Hours• SSI/MSI/PROM 38510 (1976) 44-344 FITs• MSI/LSI CICD Hi-Rel (1987) 43 FITs
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Actel FPGAs
Technology FITS # Failures Device-Hours (m)
2.0/1.2 33 2 9.4 x 107
1.0 9.0 6 6.1 x 108
0.8 10.9 1 1.9 x 108
0.6 4.9 0 1.9 x 108
0.45 12.6 0 7.3 x 107
0.35 19.3 0 4.8 x 107
RTSX 0.6 33.7 0 2.7 x 107
0.25 88.9 0 1.0 x 107
0.22 78.6 0 1.2 x 107
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Xilinx FPGAs
• XC40xxXL– Static: 9 FIT, 60% UCL– Dynamic: 29 FIT, 60% UCL
• XCVxxx– Static: 34 FIT, 60% UCL– Dynamic: 443 FIT, 60% UCL
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UTMC and Quicklogic• FPGA
– < 10 FITS (planned)– Quicklogic reports 12 FIT, 60% UCL
• UT22VP10UTER Technology, 0 failures, 0.3 [double check]
• Antifuse PROM– 64K: 19 FIT, 60% UCL– 256K: 76 FIT, 60% UCL
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Actel FIT Rate Trends
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Thermal
• Thermal Analysis Basics
• Summary of Package Characteristics
• Package Considerations– Cavity Up/Down– Heat Sinks
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Thermal Performance• Package modeled as a resistance
• Junction temperature the critical parameter– Often derated to ~ 100 ºC
• tJ = P • J-C
tJ = Junction temperature in ºC
P = Power in watts
J-C = thermal resistance, junction to case, in ºC/watt
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Thermal Performance - DevicesJ-C for Flight Devices in ºC/watt
Ceramic Pin Grid ArrayPG84 6.0PG133 4.8PG176 4.6PG207 3.51
PG257 2.81
Notes:1These packages are cavity down.2With embedded heat spreader3Estimated4Typical
Ceramic Quad Flat PackCQ84 7.8CQ132 7.2CQ172 6.8CQ196 6.4CQ208 6.3CQ256 6.2
OtherPQ208 8.0/3.82
PQ240 2.84
HQ240 1.54
CG560 0.83
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Die Up or Down?
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CQFP256 w/ Heat Sink
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Speed/Performance
• Basic Delay Model and Components
• Sample Delays– Examples from different families
• Hard-wired Structures– Routing– Arithmetic Logic
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Antifuse Delay Model
Tau = Resistance * Capacitance
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Note: These numbers are approximate and work on better numbers is in progress. UTMC, for PAL and PROM, has about 8 to 10 fF.
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Hardwired StructuresActel Routing
Model Direct Connect Fast Connect
(ns) (ns)
RT54SX-1 0.2 1.1
RT54SXS-1 0.1 0.4
Virtex Carry Chain
TBYP (CIN to COUT) 200 ps, max
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Power Consumption
• Power Basics
• Quiescent (Static) Current
• Dynamic Current– Per logic module– Clock tree
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Power - Basics
• Power = Voltage * current = V i
• Voltage is constant
• Current = Static + Dynamic
• Static current: leakage, pullup resistors, DC loads
• Dynamic Power = kv2fk: constant often referred to as CEQ
f: frequency
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Device (Array) Quiescent Current1
Device Voltage Typical Spec Level Type (V) ICC (mA) ICCMAX(mA)
A500K050 2.5 < 1 102
Orion-4K 5.0RT1020 5.0 < 1 20RT1280A 5.0 < 1 20RT14100A 5.0 < 1 20RT54SX32 3.3 < 1 25RT54SX32S 2.5 < 1 25UT4090 3.3 5XQR40xxXL 3.3 20XQV100 2.5 50XQV300 2.5 75XQV600 2.5 100XQV1000 2.5 100AT6010
1No DC Loads2Commercial Specification
XQV600 Lot Data (mA)1
lot # min mean max
1157448 4.72 6.41 8.131152401 6.26 8.37 11.401139803 3.75 5.57 12.85
1commercial or industrial worst-case, checking
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PROM Device Current1
Device Voltage Standby Dynamic @F (MHz) Type (V) ICC (mA) ICCMAX(mA)
UT28F64 5.0 0.5 100 28.62
UT28F256 5.0 < 2 125 28.62
197A8073 5.0 2.0 200 22.2
1Specification levels2Derates @ 2.5 mA/MHz3BAE Systems (formerly Lockmart) 32kx8 PROM
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Representative Dynamic Power Numbers
A1280/A1280XL Power (mW)
F(MHz) Module Input Output Clock Total
1 11 13 21 27 72 2 23 25 42 54 144 5 57 63 105 136 360 10 113 125 210 272 720 20 227 250 419 544 1,440 30 340 375 629 815 2,159 40 453 500 839 1,087 2,879
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Preliminary
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A Brief Introduction to Radiation and Programmable Devices
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Types of Radiation Effects• Total Dose• Single Event Effects (SEE)
– Single Event Upset (SEU)• Multiple Bit Upset (MBU)
– Single Event Latchup (SEL)
– Single Event Transient (SET)
– Antifuse and Rupture
– Loss of Functionality
– Snap back
• Protons• Miscellaneous
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Total Dose
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Recombination, Transport, and Trapping of Carries
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A1425A/MEC TID TESTD/C 9819 - UCJ014X
6 kRads (Si) / DayNASA/GSFC
August 14, 1998
krads (Si)
0 5 10 15 20 25
I CC (
mA
)
0
5
10
15
S/N LAN202S/N LAN203S/N LAN204S/N LAN205
Typical TID Run
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TID Run - RunawayQL3025-2 ESPQ208R TID TEST
D/C 9913CA18.6 krad (Si) / Day
NASA/GSFCApril 14, 1999
krad (Si)
0 5 10 15 20 25 30 35 40
De
lta I C
C (
mA
)
0
200
400
600
800
1000
S/N WONE001 ICC5.0V
S/N WONE001 ICC3.3V
Power Supply Limit = 800 mA
Notes:
1. DUT in Pb-Al box per 1019.52. Experimental Device
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TID Capability vs. Feature SizeSubmicron FPGA TID Tolerance
0.35 m to 0.6 m
kRads (Si)
10 20 30 40 50 60 70 80 90 100
I CC (
mA
)
0
10
20
30
40
50
RT54SX16 Proto, 0.6 m, 3.3V, MECA54SX16 Proto, 0.35 m, 3.3V, CSMA42MX09, 0.45 m, 5.0V, CSMQL3025, 0.35 m, 3.3V, TSMC
QL3025
A54SX16
RT54SX16
A42MX09
XQR4000XL Proto, 0.35 m, 3.3V, 60 kRads (Si)
RH54SX16 Proto, 0.6 m, 3.3V, > 200 kRads (Si)
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Process Mods - 0.25 mA54SX32A (Prototype) TID TEST
D/C 9924P04 Wafer 12 and 20
NASA/GSFCSeptember 24, 1999
krads (Si)
0 50 100 150 200 250
De
lta I
CC
(mA
)
0
20
40
60
80
100
120
Wafer 12Wafer 20
Notes
1. Bias levels are 5.0VDC, 2.5VDC2. Parts are in Pb/Al box per 1019.53. Dose rates between 15.7 and 16.6 rad(Si)/min
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Single Event Upset(SEU)
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From Aerospace
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Cross Section versus LET Curve
From Aerospace
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Act 2 SEU Flip-Flop Data
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XQR4036XL SEU Cross Section
From Lum
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Single Event Latchup(SEL)
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Latchup Basics
From Harris
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SEL - QL3025 0.35 m
BNL 02/98S/N QL1 Run T2VBIAS = 5.0V, 3.3VTitanium @ 0 DegLET = 18.8 MeV-cm2/mg
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Antifuse and Rupture
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ONO Antifuse
Technology Development Vehicle
Comparison of Rupture Currents
Amorphous SiliconAntifuse Rupture
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Mag = 5X Mag = 20X Mag = 100X
ONO Antifuse Breakdown - FA
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Protons
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ICC Damage During Proton TestingASIC and Antifuse FPGA
Note: Different scales for each run.
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RH1280 Proton Upsets
From Lockheed-Martin/Actel
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Summaryand
Some “Words of Wisdom”
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FRAM Memory Functionality Loss During Heavy Ion Test
Strip chart of FM1608 (research fab) current during heavy ion irradiation. The device lost functionality during the test while the current decreased from it's normal dynamic levels of approximately 6.3 mA to it's quiescent value, near zero. The device recovered functionally and operated normally throughout the latter part of the test. This effect was seen at least three times during the limited testing of this device.