Programmable Array Logic Programmable Array Logic (PAL)(PAL)

Fixed OR array programmable AND Fixed OR array programmable AND arrayarray

Easy to programEasy to program Poor flexibility Poor flexibility Boolean function must be simplified to Boolean function must be simplified to

fit into each sectionfit into each section Unlike, PLA product term cannot be Unlike, PLA product term cannot be

shared among two or more OR gatesshared among two or more OR gates

PAL with 4-input 4-output 3-wide AND-OR structurePAL with 4-input 4-output 3-wide AND-OR structure

Use PAL to design Use PAL to design combinational logic circuit combinational logic circuit

Boolean functionBoolean function

simplifiedsimplified

PAL programming table is similar to that PAL programming table is similar to that of PLA except that only inputs of AND of PLA except that only inputs of AND gates need to be programmed. gates need to be programmed.

)13,12,8,2,1(),,,(

)15,11,10,8,7,6,5,4,3,2,0(),,,(

)15,14,13,12,11,10,9,8,7(D)C,B,x(A,

)13,12,2(),,,(

DCBAz

DCBAy

DCBAw

DCBADCAw

DCBADCADCBACABz

DBCDBAy

BCDAx

DCBACABw

PAL programming tablePAL programming tableAND inputs product

term A B C D W

1 1 1 - - -

2 0 0 1 0 -

3 - - - - -

DCBACABw

4 1 - - - -

5 - 1 1 1 -

6 - - - - -

BCDAx

7 0 1 - - -

8 - - 1 1 -

9 - 0 - 0 -

DBCDBAy

10 - - - - 1

11 0 - 0 0 -

12

1 0 0 1 -

DCBADCAwz

Fuse map of PALFuse map of PAL

Sequential Programmable Sequential Programmable DeviceDevice

Digital systems are designed using flip-flop Digital systems are designed using flip-flop and gatesand gates

PLD contains only gatesPLD contains only gates Sequential Programmable Device include Sequential Programmable Device include

both flip-flop and gatesboth flip-flop and gates Three major types:Three major types:

1. Sequential (simple) programmable logic 1. Sequential (simple) programmable logic device (SPLD)device (SPLD)

2. Sequential programmable logic device (CPLD)2. Sequential programmable logic device (CPLD)3. Field programmable gate array (FPGA)3. Field programmable gate array (FPGA)

SPLD SPLD

SPLD: AND-OR array + F.F. (See Fig. 7-18)SPLD: AND-OR array + F.F. (See Fig. 7-18) Output can be taken from OR gates or output Output can be taken from OR gates or output

of F.F.of F.F. F.F. can be D or JK F.F. can be D or JK Each section is called macrocell include sum-Each section is called macrocell include sum-

of-product combinational logic and a F.F. of-product combinational logic and a F.F. Typically include 8-10 macrocell in a chip (ITypically include 8-10 macrocell in a chip (I

C) C)

SPLDSPLD

Field-programmable logic Field-programmable logic sequential (FPLS)sequential (FPLS)

First programmable device developed to suppoFirst programmable device developed to support sequential circuits rt sequential circuits

PLA + several F.F. (programmable to D or JK)PLA + several F.F. (programmable to D or JK) Did not succeed commercially because it has tDid not succeed commercially because it has t

o many programmable connection o many programmable connection

Complex PLD (CPLD)Complex PLD (CPLD)

Collection of several individual PLD Collection of several individual PLD Fig. 7-20 shows a general configuration of CPLDFig. 7-20 shows a general configuration of CPLD PLD is interconnected through programmable switch PLD is interconnected through programmable switch

matrixmatrix I/O blocks provide the connection to IC pinI/O blocks provide the connection to IC pin Each I/O is driven by 3-state buffer and can be prograEach I/O is driven by 3-state buffer and can be progra

mmed to act as input or outputmmed to act as input or output The programmable switch matrix receives input from The programmable switch matrix receives input from

I/O block and directs it to the individual macrocell I/O block and directs it to the individual macrocell

CPLDCPLD

Field Programmable Gate Array Field Programmable Gate Array (FPGA)(FPGA)

VLSI VLSI Elementary element is logic block Elementary element is logic block Consists hundreds or thousands logic blockConsists hundreds or thousands logic block Logic block consists of Logic block consists of look-up tablelook-up table, multiplexers, g, multiplexers, g

ates and F.F.ates and F.F. Look-up table is a truth table stored in a Look-up table is a truth table stored in a SRAMSRAM and provid and provid

es the combinational function for the logic blockes the combinational function for the logic block Remember that PAL or PLA is used for macrocell in CPLDRemember that PAL or PLA is used for macrocell in CPLD

FPGAFPGA

Use RAM instead of ROMUse RAM instead of ROM Advantage: programmableAdvantage: programmable Disadvantage: volatile Disadvantage: volatile

PLD, CPLD, FPGA requires CADPLD, CPLD, FPGA requires CAD SchematicSchematic HDLHDL

VHDLVHDL Verilog HDLVerilog HDL

ExerciseExercise

7-1, 7-2, 7-4, 7-6, 7-8, 7-9, 7-15, 7-7-1, 7-2, 7-4, 7-6, 7-8, 7-9, 7-15, 7-17, 7-18, 7-19, 7-20, 7-21, 7-24, 7-2517, 7-18, 7-19, 7-20, 7-21, 7-24, 7-25