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PROCESSORS

USED IN

SOCS

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REDUCED INSTRUCTION SET COMPUTER

The acronym RISC, for reduced instruction

set computer, represents a CPU design strategy

emphasizing the insight that simplified

instructions that "do less" may still provide for

higher performance if this simplicity can beutilized to make instructions execute very

quickly.

Well known RISC families include Alpha, Am29k, ARC, ARM, AVR, MIPS, PA-RISC,

Power Architecture (including PowerPC

),

SuperH, and SPARC.

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CHARACTERISTICS OF RISC

For any given level of general performance, a RISC chipwill typically have far fewer transistors dedicated to thecore logic which originally allowed designers to increase thesize of the register set and increase internal parallelism.

Other features, which are typically found in RISC

architectures are: Uniform instruction format, using a single word with the

opcode in the same bit positions in every instruction,demanding less decoding;

Identical general purpose registers, allowing any register to beused in any context, simplifying compiler design (although

normally there are separate floating point registers); Simple addressing modes. Complex addressing performed via

sequences of arithmetic and/or load-store operations;

Few data types in hardware, some CISCs have byte stringinstructions, or support complex numbers; this is so farunlikely to be found on a RISC.

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RISC

RISC designs are also more likely to feature aHarvard memory model, where the instruction streamand the data stream are conceptually separated; thismeans that modifying the memory where code is heldmight not have any effect on the instructionsexecuted by the processor (because the CPU has aseparate instruction and data cache

), at least until aspecial synchronization instruction is issued.

On the upside, this allows both caches to be accessedsimultaneously, which can often improve

performance.

Many early RISC designs also shared thecharacteristic of having a branch delay slot. A branchdelay slot is an instruction space immediatelyfollowing a jump or branch.

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E ARLY RISC

The first system that would today be known as RISCwas the CDC 6600 supercomputer, designed in 1964,a decade before the term was invented.

The CDC 6600 had a load-store architecture with onlytwo addressing modes and 74 opcodes.

The most public RISC designs, however, were theresults of university research programs run withfunding from the DARPA VLSI Program.

UC Berkeley's RISC project started in 1980.

The RISC project delivered the RISC-I processor in

1982. Consisting of only 44,420 transistors RISC-Ihad only 32 instructions, and yet completelyoutperformed any other single-chip design.

They followed this up with the 40,760 transistor, 39instruction RISC-II in 1983, which ran over threetimes as fast as RISC-I.

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 V ON NEUMANN ARCHITECTURE

Mr. John Von Neumann

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 V ON NEUMANN ARCHITECTURE

The von Neumannarchitecture is a designmodel for a stored-programdigital computer that uses a

processing unit and a singleseparate storage structure tohold both instructions anddata.

It is named after themathematician and earlycomputer scientist John vonNeumann.

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 V ON NEUMANN BOTTLENECK

The separation between the CPU and memory leadsto the von Neumann bottleneck, the limitedthroughput (data transfer rate) between the CPU andmemory compared to the amount of memory. In mostmodern computers, throughput is much smaller than

the rate at which the CPU can work.

The performance problem can be alleviated (to someextent) by several mechanisms. Providing a cachebetween the CPU and the main memory, providingseparate caches with separate access paths for data

and instructions. The problem can also be sidestepped somewhat by

using parallel computing, using for example theNUMA  architecture — this approach is commonlyemployed by supercomputers.

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E ARLY VON NEUMANN- ARCHITECTURE

COMPUTERS

ORDVAC (U-Illinois) at Aberdeen Proving Ground,Maryland (completed Nov 1951[13])

IAS machine at Princeton University (Jan 1952)

MANIAC I at Los Alamos Scientific Laboratory (Mar 1952)

ILLIAC at the University of Illinois, (Sept 1952) AVIDAC at Argonne National Laboratory (1953)

ORACLE at Oak Ridge National Laboratory (Jun 1953)

JOHNNIAC at RAND Corporation (Jan 1954)

BESK in Stockholm (1953)

BESM-1 in Moscow (1952) DASK in Denmark (1955)

PERM in Munich (1956?)

SILLIAC in Sydney (1956)

WEIZAC in Rehovoth (1955)

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E  ARLY STORED-PROGRAM COMPUTERS

The IBM SSEC was a stored-program electromechanical computer and was

publicly demonstrated on January 27, 1948. The Manchester SSEM was the first fully electronic computer to run a

stored program. It ran a factoring program for 52 minutes on June 21, 1948.

The ENIAC was modified to run as a primitive read-only stored-programcomputer and was demonstrated as such on September 16, 1948.

The BINAC ran some test programs in February, March, and April 1949,although it wasn't completed until September 1949.

The Manchester Mark 1 developed from the SSEM project. It wasn'tcompleted until October 1949.

The EDSAC ran its first program on May 6, 1949.

The EDVAC was delivered in August 1949, but it had problems that kept itfrom being put into regular operation until 1951.

The CSIR Mk I ran its first program in November 1949.

The SEAC was demonstrated in April 1950. The Pilot ACE ran its first program on May 10, 1950 and was demonstrated

in December 1950.

The SWAC was completed in July 1950.

The Whirlwind was completed in December 1950 and was in actual use in April 1951.

The first ERA Atlas (later the commercial ERA 1101/UNIVAC 1101) wasinstalled in December 1950.

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H ARVARD ARCHITECTURE

The Harvard architecture is a computer architecture withphysically separate storage and signal pathways forinstructions and data.

The term originated from the Harvard Mark I relay-based

computer, which stored instructions on punched tape (24 bitswide) and data in electro-mechanical counters. These earlymachines had limited data storage, entirely contained withinthe central processing unit, and provided no access to theinstruction storage as data.

Today, most processors implement such separate signalpathways for performance reasons but actually implement aModified Harvard architecture, so they can support tasks likeloading a program from disk storage as data and thenexecuting it.

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MEMORY DETAILS

In a Harvard architecture, there is no need to make thetwo memories share characteristics.

In particular, the word width, timing, implementation

technology, and memory address structure can differ.

In some systems, instructions can be stored in read-onlymemory while data memory generally requires read-write memory.

In some systems, there is much more instructionmemory than data memory so instruction addresses arewider than data addresses.

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CONTRAST WITH VON NEUMANN

 ARCHITECTURES

In a computer with the contrasting von Neumannarchitecture, the CPU can be either reading aninstruction or reading/writing data from/to the memory.

Both cannot occur at the same time since theinstructions and data use the same bus system.

In a computer using the Harvard architecture, the CPUcan both read an instruction and perform a datamemory access at the same time, even without a cache.

A Harvard architecture computer can thus be faster fora given circuit complexity because instruction fetchesand data access do not contend for a single memorypathway.

Also, a Harvard architecture machine has distinct codeand data address spaces: instruction address zero is notthe same as data address zero. Instruction address zeromight identify a twenty-four bit value, while data

address zero might indicate an eight bit byte that isn'tpart of that twenty-four bit value.

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