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Introduction toIntroduction to Processor SDK RTOS Part 1

Agenda• Processor RTOS SDK Overview• TI‐RTOS KernelTI RTOS Kernel• Inter‐Processor Communication (IPC)• Network Development Kit (NDK)Network Development Kit (NDK)• Diagnostic Software• Algorithm Libraries• Algorithm Libraries• Drivers (Covered in Part 2)

Processor RTOS SDK Overview

Introduction to Processor SDK RTOS

Processor SDK RTOS Development Ecosystem Eclipse IDE

Processor SDK RTOS Code Composer

TMThird Party

StudioTM (CCS) Plug‐Ins

For CCS Training: processors.wiki.ti.com/index.php/Category:CCS_

TrainingTraining

Host Computer Target Board/SimulatorEmulator

p g /

Processor SDK RTOS Install• Each TI part has its own install page. For example:

AM335x: http://www ti com/tool/processor sdk am335x―AM335x: http://www.ti.com/tool/processor‐sdk‐am335x

―AM57x: http://www.ti.com/tool/processor‐sdk‐am57x

• Click on the Get Software link and it will take you to install page like the one in the next slideinstall page like the one in the next slide.

• The Getting Started Guide and the Developer Guide show how to start developing Processor SDK RTOS‐based applications.

Part of Processor SDK RTOS Install Page

Processor SDK RTOS: OverviewThe RTOS (Real Time Operating System) perspective of the TI Processor SDK (Software Development Kit):

• Provides a set of software building blocks that facilitate development of (real‐time) applications

• Consists of SOC (device) and platform dependent modules, Core dependent software, TI‐RTOS kernel and utilities and application examples

• Includes source code and prebuilt librariesp

• Embedded OS: TI‐RTOS kernel for DSP, ARM, and M4

• De elopment OS Windo s and Lin PC s pport• Development OS: Windows and Linux PC support

• Available as a free download with all components in one i t llinstaller

Processor SDK ElementsApplications

Implemented on top of the operating system and may be architecture dependent.

Operating System Dependent Components

TI‐RTOS kernel, Tools, Utilities, Drivers, , ,

Core‐Specific / OS‐Independent Components

Optimized Libraries, Compiler Tools

SOC Dependent / OS Independent ComponentsSOC ‐Dependent / OS‐Independent Components

device and platform drivers

Processor SDK RTOS Software (Superset)

Application OOB Demos

RTOS ‐ NetworkSoftware Framework Components

InfotainmentVisionIndustrialSmall CellAudioVideoHPC

TI‐RTOS XDCtools

RTOS Network

TCP/IPNetworking

(NDK)

Software Framework Components

Inter‐Processor Communication

(IPC)

Framework Components

OS AbstractionLayer (OSAL)

Network I/FMgmt Unit(NIMU)

Algorithm Libraries

DSPLIB IMGLIB MATHLIB Code Generation

Platform/EVM Software

Secondary Bootloader FATFS

Tools forDifferentCores

(will move to CCS)

BoardLibraryLow Level Drivers (LLD)

EDMA3 ICSS‐EMAC PCIe PRUSS I2C EMAC CCS) Diagnostics

Chip Support Library (CSL)

SPI GPIO UART …USB SD/MMC

Hardware

p pp y ( )

Component used by core code developersDevice/platform‐dependent

OS‐dependent Applications

Processor SDK RTOS

Single prod ct s pports m ltiple SoCsSingle product supports multiple SoCs

Processor SDK RTOS Release (AM335)

Processor SDK RTOS Release (AM437)

Processor SDK RTOS Release (AM572X)Superset of Featuresp

Processor SDK RTOS Release (AM572X)

pdk_am57xx_1_0_0

edma3 lld 02 12 01 21edma3_lld_02_12_01_21

framework_components_3_40_00_02

The pdk folder contains the platform development kit

The edma folder includes multiple EDMA controllers

The framework components folder includes a set ofdevelopment kit,

which is a collection of CSL and low‐level drivers that configure

EDMA controllers, management drivers, and the resource manager

includes a set of utilities to manage the target board hardware, memories,drivers that configure

and manage the hardware.

resource manager. hardware, memories, interfaces, etc.


dsplib_c66x_3_4_0_0

imglib_c66x_3_2_0_1

mathlib_c66x_3_1_0_0

ti‐cgt‐c6000_8.0.3

xdais_7_24_00_04

The following folders contain optimized The xdais folder The ti‐cgt‐c6000 folder The following folders contain optimized libraries for DSP core applications:

• dsplib: FFT, Filters, etc.

The xdais folder includes a set of standard DSP interfaces that enable

contains code generation tools that enable code development on the

• imglib: Image processing

• mathlib: Standard math functions (sin, cosin, sqrt)

interfaces that enable easy integration of XDAIS‐compatible algorithms (voice and

target board.

NOTE: This tool will move (sin, cosin, sqrt)

NOTE: Many more libraries are available as source code outside of th l

algorithms (voice and video codecs) into applications.

to CCS with the other code generation tools.

the release.

Processor SDK RTOS Release (AM572X)bios_6_41_04_54

cg_xml

xdctools_3_31_02_38

ipc_3_36_01_11

processor_sdk_rtos_2_00_00_00

ndk_2_24_01_18

The bios folder includes the RTOS operating

The cg_xml and xdctoolsfolders contain sets of

The ipc folder contains a set of utilities used to

system kernel (scheduler and utilities).

h dk

utilities used to build and configure OS modules using a GUI interface or

fi i fil

facilitate inter‐processor communications internal and external the device.

The processor_sdk_rtosfolder contains collateral, documentation, and

l

ASCII configuration file .The ndk folder includes the TCP/IP stack.

examples.


ctoolslib 1 1 1 0ctoolslib_1_1_1_0

uia_2_00_03_43

The ctools folder is a collection of libraries

The uia (universal instrumentationcollection of libraries

that control real‐time debug and collect debug information

instrumentation architecture) folder contains utilities, which are used to processdebug information

(instrumentation) .are used to process, analyze, and display debug data from the hardware ( l )(visualization).

TI‐RTOS Kernel


TI‐RTOS: Generic Real Time Operating System

• TI‐RTOS is a scalable OS that is currently available for l i lmultiple cores:

– Tiva‐C (M4)Concerto (M3+C28x)– Concerto (M3+C28x)

– C28x– MSP430– C6000– Sitara

• TI‐RTOS is embedded within Processor SDK RTOS.• The RTOS kernel is a real‐time multi‐tasks scheduler. • Tools, utilities, and drivers are also included.

Real Time Multi‐Tasks Scheduler

By definition, real‐time is a controlled response time to (multiple) external events.• Able to accept multiple interruptsAble to accept multiple interrupts• Controls the maximum latency in responding to interruptNOTE: Deterministic latency is hard to achieveNOTE: Deterministic latency is hard to achieve

• Provides a strong priority scheme for tasks

TI‐RTOS Real Time Multi‐Tasks SchedulerE t d i ti t• Event‐driven operating systemNOTE: Event can be clock, but usually not.

V ll d ti f t i t• Very small adaptive footprint• Very efficient context switching

More Information About TI‐RTOS• Comprehensive TI RTOS online training:

http://processors.wiki.ti.com/index.php/Introduction_to_the_TI‐RTOS_Kernel_Workshop

d d– 10 video presentations cover TI‐RTOS and CCS in great detail.All lid il bl f d l d– All slides are available for download.

• Other URLs that contain RTOS training are http://processors wiki ti com/index php/SYS/BIOS Online Training andhttp://processors.wiki.ti.com/index.php/SYS/BIOS_Online_Training and http://processors.wiki.ti.com/index.php/Hands‐On_Training_for_TI_Embedded_Processors

• The back‐up slides attached to the end of this presentation (See Resources for PDF) provide a brief description of all TI‐RTOS thread types.

Inter‐Processor CommunicationInter‐Processor Communication (IPC)( )Introduction to Processor SDK RTOS

IPC PrinciplesIPC provides standard APIs to communicate bet een threadsbetween threads:• The same APIs for all SOCs• The same APIs regardless of what CPU is the sender and what CPU is the receiversender and what CPU is the receiver

• The same APIs regardless of the operating system

• The same APIs regardless of the transportThe same APIs regardless of the transport mechanism

IPC Challengesg• Cooperation between multiple cores requires a smart way to exchange data and messagesway to exchange data and messages.

• IPC must support any number of cores within a single SOC with the ability to connect multiple devicesSOC with the ability to connect multiple devices.

• An efficient scheme is required to avoid high cost in terms of CPU cyclesterms of CPU cycles.

• Implementations depend on the hardware, transport layer and operating systemlayer, and operating system.

• There are the usual trade‐offs: performance (speed, flexibility) versus cost (complexity, more resources).flexibility) versus cost (complexity, more resources).

SOC Architecture Support for IPCpp

• Depends on the SOC―Memories that can be shared between cores―Mailboxes or interrupt registers ―Multicore Navigator or other DMA mechanismMulticore Navigator or other DMA mechanism

• Uses peripherals for communication between devices

IPC Modulel l l• Current IPC implementation may use multiple transports:

– Core Core – Device Device (SoC peripheral interface)

• Chosen at configuration; Same code regardless of thread location.

Device 1ARM C66

Device 2ARM

• IPC Manager initializes IPC and ARM

hread 1

hread 2

C66x

hread 1

hread 2

ARM

hread 1

hread 2

initializes IPC and synchronization

API summary: ‐RTO

S

‐RTO

S

RTOS

Th

IPCIPC

Th Th

IPCIPC

Th Th

IPCIPC

ThAPI summary:Ipc_start reserves memory, create default gate and heapIpc_stop releases all resourcesIpc attach sets up transport

TI‐

TI‐

TI‐

MEMIpc_attach sets up transport between two processorsIpc_detach finalizes transport

SoC Peripheral SoC Peripheral

IPC Services• The IPC package is a set of standard APIs MessageQ is the• The IPC package is a set of standard APIs MessageQ is the

highest layer Th i l t ti i d i d ti t d d t• The implementation is device and operating system dependent

Application

MessageQ

Drivers

IPC Config And

Initialization

Transport layer (shared memory, Navigator, srio)Transport layer (shared memory, Navigator, srio)

MessageQ Highest Layer API (1/3)Core 2 READER

MessageQ_create(“myQ”, *synchronizer);

Core 2 ‐ READER

SINGLE reader, MessageQ_get(“myQ”, &msg, timeout);“myQ”multiple WRITERS

model (READER owns queue/mailbox)

• MessageQ transactions begin with READER creating a MessageQ.READER’ l i bl k ( l• READER’s attempt to get a message results in a block (unlesstimeout was specified), since no messages are in the queue yet.

Using MessageQ (2/3)Core 1 WRITER Core 2 READER

MessageQ_create(“myQ”, …);MessageQ_open (“myQ”, …);

Core 1 ‐WRITER Core 2 ‐ READER

“myQ” MessageQ_get(“myQ”, &msg…);msg = MessageQ_alloc (heap, size,…);

MessageQ_put(“myQ”, msg, …);

HeapHeap

• WRITER begins by opening MessageQ created by READER.• WRITER gets a message block from a heap and fills it, as desired.• WRITER puts the message into the MessageQ.

Using MessageQ (3/3)Core 1 WRITER Core 2 READER

MessageQ_create(“myQ”, …);MessageQ_open (“myQ”, …);

Core 1 ‐WRITER Core 2 ‐ READER

“myQ” MessageQ_get(“myQ”, &msg…);

*** PROCESS MSG ***

msg = MessageQ_alloc (heap, size,…);

MessageQ_put(“myQ”, msg, …);

MessageQ_free(“myQ”, …);

MessageQ_delete(“myQ”, …);

MessageQ_close(“myQ”, …);

HeapHeap

• Once WRITER puts msg in MessageQ, READER is unblocked.• READER can now read/process the received message.• READER frees message back to Heap.• READER can optionally delete the created MessageQ, if desired.

Network Developer’s Kit (NDK)


Network ServicesThe Network Developer’s Kit (NDK) serves as a rapid prototype platform for the development of network andprototype platform for the development of network and packet‐processing applications. NDK includes the following:following:• IPv6 and IPv4 compliant TCP/IP stack • Layer 3 & 4 network protocolsLayer 3 & 4 network protocols• High‐level network applications including HTTP server and

DHCP

NOTE: NDK was developed as a prototype code example. It is not aimed for high‐throughput networkingIt is not aimed for high throughput networking.

Network Services• The NDK is divided into two parts:parts:– NIMU (Network Interface Management Unit)Management Unit)

– User interface unit• For more information, refer to the NDK User’s Guide.

Algorithm Libraries


Optimized Algorithm Libraries• The Processor SDK release contains three algorithm libraries.

• Each release directory has a C66 DSP‐optimized code as well as a standard ANSI C implementation of all th f tithe functions.

• The standard ANSI C implementation is used to validate the results of the optimized libraryvalidate the results of the optimized library functions.

• Compiling the ANSI C source code using another core p g g(like M4 or A15) compiler provides (non‐optimized) libraries for non‐DSP core.

DSP Algorithm Libraries• Optimized algorithm libraries contain C66x C‐callable, C with intrinsic functions for specific usage.

• Few legacy functions are written using assembly code.

• The following three libraries are part of the Processor SDK release:Fundamental math & signal processing libraries:– Fundamental math & signal processing libraries: DSPLIB: Signal‐processing math and vector functions MathLIB: Floating‐point math functionsg p

– IMGLIB: Image/video processing functions• A complete set of libraries that are available as source code can be found here: http://processors.wiki.ti.com/index.php/Software_libraries

Diagnostics Software


CCS Diagnostic Elements• CCS‐based Debug

break points– break points– watch points– step/step into– resume

• CCS‐based Trace (Instrumentation)C fi l i– Configure trace logic

– Getting trace information back to host• CCS‐based data processing (Visualization)

Run‐Time Diagnostic ElementsPart of Processor SDKPart of Processor SDK

CToolsLib (Chip Tools Library) has multiple libraries that provide run‐time debug capabilities.

NOTE: Not all features are available for all devices. Usage is dependent on core and device hardware.

More details at http://processors.wiki.ti.com/index.php/CToolsLib

Run‐Time Diagnostic Elements• AET (Advanced Event Trigger Library) configures stateLibrary) configures state machines that control tracing.

• DSPTraceLib and ETBLib(Embedded Trace Buffer(Embedded Trace Buffer Library) provide a set of functions to control the DSPfunctions to control the DSP trace buffer operation and trace data transporttrace data transport.


Run‐Time Diagnostic Elements• ETMLib (Embedded Trace

Macrocell Library) controls theMacrocell Library) controls the ARM macrocell trace facilities.

• PMICMILib (Power and Clock Management InstrumentationManagement Instrumentation library) provides programming and control APIs for the PMI/CMI units, which provide power and clock state profiling.


Run‐Time Diagnostic Elements• SCILib (Statistic Collectors Library) collects statisticalLibrary) collects statistical data from hardware counters (core dependent)(core dependent).

b ( b )• STMLib (System Trace Library) provides a set of utilities to ll lcollect real‐time, non‐

intrusive system trace d i imessages during run‐time.


For More Information• TI‐RTOS Tool Folder• TI‐RTOS Wiki• TI‐RTOS Kernel WorkshopTI RTOS Kernel Workshop• Introduction to Processor SDK RTOS Part 2• For questions regarding topics covered in this training, visit the support forums at the TI E2E g, ppCommunity website.

Back‐Up Slides

TI‐RTOS Real Time Multi‐Tasks Scheduler

Four thread layers are prioritized as follo sas follows:1. Hardware Interrupts (HWI) are the

i iti l i t t i tiinitial interrupt service routines 2. Software Interrupts (SWI) are short and

light threads usually initiated by thelight threads usually initiated by the HWI

3 A Task is a “permanent” thread that Priority

3. A Task is a permanent thread that wakes up when it has data to process, goes to sleep after finishing processing

P

and continue until it is closed4. Idle – lowest priority task

TI‐RTOS HWI (Hardware Interrupt)• Starts as soon as interrupt occurs. But start can be delayed if either of the following occurs:– Another HWI executes– The application intervenes (limited time)pp ( )

• Interrupts can be blocked, latched, and/or nested,• Software controls:• Software controls:

– The maximum latency for the start of HWITh i it f HWI d b h i– The priority of HWI and behavior

• HWI always has higher priority than SWI.

CCS GUI Interface to Configure HWI

TI‐RTOS SWI (Software Interrupt)• Regarded as the processing part of an ISR (Interrupt Service Routine)( p )

• Short and light execution model with full priority scheme:priority scheme:– SWI is preempted when higher priority SWI is scheduled (and for all HWI)

– Fast‐switch context mechanism (small memory footprint)

• Software controls the priority of SWISoftware controls the priority of SWI.But SWI always has higher priority than Task

• All HWIs and SWIs share the same stack

CCS GUI Interface to Configure SWI

TI‐RTOS Tasks• Main processing parts of execution:

– Runs in infinite loopRuns in infinite loop– Sleeps until external event wakes it up.After finishing e ec tion goes back to sleep– After finishing execution, goes back to sleep.

• Full priority scheme:– Task is preempted when higher priority task is scheduled (for all HWI or SWI)( )

– Fast‐switch context mechanism: Each task has its own stackown stack.

• Software controls the priority of Task

CCS GUI Interface to Configure Task

TI‐RTOS Clock• Generate periodic “ticks” to follow periodic events

• Can be used for time slice operationh h d ( h l bl )• Uses the hardware times (when it is available)

• Easily configured either by the GUI or withEasily configured either by the GUI or with code

Clock Function

CCS GUI Interface

Modifies theModifies the cfg Script

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