processing digital and analog signals in satellite communications

Slide Number 1Rev -, July 2001

Technical Introduction to Geostationary Satellite Communication Systems Original Prepared by Telesat Canada


Technical Introduction to Geostationary Satellite Communication Systems Original Prepared by Telesat CanadaTechnical Introduction to Geostationary Satellite Communication Systems Original Prepared by Telesat Canada

3.5.1 Analog



Vol 3: Satellite Communication Principles, Sec 5: Processing Digital and Analog Signals

Part 1: Analog

3.5.1.1: Speech Activation for Voice

Speech Activation for VoiceIn FDMA mesh satellite communications networks the transponder is very often power dominated. This occurs because small dish antennas are commonly used to serve single channel remote serving areas. The small dish remotes normally homes into a large antenna gateway site, but sometimes home into another small dish remote further exacerbating the problem.

The EIRP levels into a gateway site is usually 4 to 6 dB lower than the EIRP levels into a small dish remote. The worst case scenario is when two remotes establish a mesh connection, therefore, further limiting the transponder capacity.



Speech Activation for VoiceIn order to alleviate this limitation voice activation technique is adopted to reduce the average transponder power. In a normal telephone conversation the speech activity lasts for about 30 to 40 percent of the time. If the RF carrier is activated only when speech is detected there could be a “two to one” gain advantage. This means more simultaneous calls can be supported for a given amount of transponder power.

The gain advantage assumes voice traffic between satellite terminals, not FAX or MODEM traffic.

Traditionally, voice-activated systems relied on hard threshold comparisons between the speech signal energy with some fixed preset level, which resulted in speech clipping.


Part 1: Analog




Speech Activation for VoiceModern voice-activation systems combine speech signal energy with short-term speech changes and the spectral characteristics of the speech signal in order to provide a more accurate and responsive detection of the speech signal. This detection process significantly minimizes speech clipping.

During idle speech periods a noise generator inserts Gaussian noise, which closely matches the noise heard during the conversation, therefore improving the overall quality of service.


Part 1: Analog




Compression and Expansion for VoiceIn PCM telephony applications -LAW and -LAW companders are used to compress the audio signal at the transmitting facility and expand the audio signal in the receiving facility.

North America and Japan use the -LAW standard. The rest of the world uses the -LAW standard.

The objective of the compander is to provide a more consistent S/Q level over the entire audio dynamic range, which is typically 0 to 35 dB.

If companders were not employed, low S/Q values (1 to 10 dB) would be superimposed at the low volume range, while high S/Q values ranging (20 to 40 dB) would be superimposed at the high volume range.


Part 1: Analog

3.5.1.2: Compression and Expansion for Voice



Pre-Emphasis and De-Emphasis for Voice and TelevisionIn SCPC/FM telephony applications a pre-emphasis de-emphasis network is used to provide a 6.3 dB S/N gain advantage.

The pre-emphasis characteristics are given in recommendation ITU-R S.464.

The pre-emphasis transfer characteristics plot is shown below.


Part 1: Analog

3.5.1.3: Pre-Emphasis and De-Emphasis for Voice and Television




Part 1: Analog


Figure 3.5.1.3 Normalized Frequency



Pre-Emphasis and De-Emphasis for Voice and TelevisionThe signal-to-weighted noise ratio of an SCPC/FM network is given by:

S/Nw = (C/N)IF + 10log10 3 (fd/fmax)2 + 10log10 (BIF/2Ba) + P + W + C

Where:Fd = peak test-tone deviation @ 0dBm0 (Hz)fmax = highest voice channel frequency (Hz)BIF = receiver IF bandwidth (Hz)Ba = audio noise bandwidthP = psophometric weighing improvement factor 2.5

dBW = emphasis improvement factor 6.3 dBC = companding advantage, if used 15 dB(C/N)IF = receiver IF carrier-to-noise ration (dB)S/Nw = signal-to-noise weightedVol 3: Satellite Communication Principles, Sec 5: Processing Digital and Analog

Signals

Part 1: Analog




Energy DispersalIn FM, when the modulation index of a frequency-modulated carrier is low, the power of the modulated carrier is concentrated in the narrow band. When there is no modulation, all of the power is concentrated at the carrier frequency. Under these circumstances the power spectral density of the RF signal (dBW/Hz) will become objectionably too high.

The principle of energy dispersal is to superimpose a low frequency triangular signal on the modulating signal before modulation. The signal frequency normally operates between 20 to 150 Hz. The signal is subsequently subtracted from the demodulated signal on reception. The un-modulated FM carrier is normally swept approximately 2 MHz peak-to-peak.


Part 1: Analog

3.5.1.4: Energy Dispersal



Energy DispersalIn FM satellite television networks the energy dispersion signal must be synchronized to the video frame rate or field rate frequency for the type of television transmission being used (NTSC, PAL, SECAM)

The overall objective is to limit the satellite power spectral density in order to prevent interference with terrestrial microwave networks that use the same RF frequencies.


Part 1: Analog

3.5.1.4: Energy Dispersal

Figure 3.5.1.4 Energy Dispersal



DigitalObjective

At the end of this section, the student should understand the use of error correction coding is digital satellite communications.

Vol 3: Satellite Communication Principles

Sec 5: Processing Digital and Analog Signals

3.5.2: Digital



Automatic Repeat RequestARQ uses an error detecting code together with an auxiliary feedback channel to initiate a retransmission of any blocks of bits received in error. It is obviously not suited for voice communications, but can be used for data transmission.

With ARQ, data messages are built up at the originating end on a packet or block basis. Each block or packet has appended to it a "Block Check Count" or Parity Tail.

At the receiving end, a similar processing technique is used and the locally derived parity symbols are compared to the received parity symbols. If they are the same, the message is said to be error free, and if not, the block or packet is in error.


Part 2: Digital

3.5.2.1: Automatic Repeat Request



Automatic Repeat RequestThere are three principal ARQ schemes:

1) Stop and Wait ARQ

2) Continuous ARQ

3) Selective Repeat ARQ

STOP AND WAIT ARQ

Stop and Wait ARQ is the simplest and the most widely used. After sending a block, the transmitting terminal waits for a positive or negative acknowledgment from the received terminal. If it is a positive acknowledgment (ACK), it sends the next block. If it is a negative acknowledgment (NACK), it sends the previous block.


Part 2: Digital




Automatic Repeat Request


Part 2: Digital


1 2 3 3 4 5 5

1 2 3 3 4 5 5

AC

K

AC

K

AC

K

AC

K

AC

K

AC

K NA

K

ERROR ERROR

TRANSMITTING TERMINAL

TRANSMISSION

RECEIVING TERMINAL

1. STOP-AND-WAIT ARQ ( HALF-DUPLEX LINE )

Figure 3.5.2.1a Stop-and-Wait ARQ



Automatic Repeat RequestCONTINUOUS ARQWith Continuous ARQ, the transmitting terminal does not wait for an acknowledgment after sending a block; it immediately sends the next block. While the blocks are being transmitted, the stream of acknowledgments is examined by the transmitting terminal (Ref 1).When the transmit terminal receives a NACK, or fails to receive an ACK, it must determine which block was incorrect. The acknowledgment will contain the number of the transmitted block it refers to so that the TX terminal can identify it.


Part 2: Digital




Automatic Repeat RequestCONTINUOUS ARQUpon receiving a NACK, the transmitter goes back and repeats the block detected in error and all the following blocks. Such a scheme is sometimes referred to as GO-BACK-N ARQ, where N refers to the number of blocks repeated.With this ARQ system, buffering must be provided at the TX terminal and the buffer size depends on the transmission rate and round-trip delay, with a minimum of two clock lengths.

Part 2: Digital





2. CONTINUOUS ARQ, WITH PULL-BACK ( FULL-DUPLEX LINE )

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

ACK(

1)

ACK(

2)

ACK(

4)AC

K(5)

ACK(

6)AC

K(7)

ACK(

8)AC

K(1)

ACK(

2)


TRANSMISSION :

RECEIVING TERMINAL

ACK(

3)

9 4 5 6 7 89

9 10 5

9 45 6 7 8

ACK(

4)

ERROR ERROR

NAK(

3)



Part 2: Digital


Figure 3.5.2.1b Continuous ARQ



Automatic Repeat RequestSELECTIVE REPEAT ARQ

A more efficient scheme is to transmit only the block with error and not those blocks which follow it. This single block re-transmission requires that the block be identified and needs more logic and buffering in the transmitting and receiving terminals. Furthermore, this selective repeat ARQ scheme requires more complex logic and larger buffers since the blocks are not always received in serial order (Ref 1).


Part 2: Digital






Part 2: Digital


3. CONTINUOUS ARQ, WITH RETRANSMISSION OF INDIVIDUAL BLOCK ( FULL-DUPLEX LINE) ( SOMETIMES CALLED SELECTIVE REPEAT ARQ )

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

Error

ACK(

1)

ACK(

2)

ACK(

3)

ACK(

4)AC

K(5)

ACK(

6)AC

K(7)

ACK(

8)AC

K(1)

ACK(

2)

3 9 10 11 12 13 14

3 9 10 11 12 13

Error


TRANSMISSION :

RECEIVING TERMINAL

ACK(

3)

ACK(

5)

NAK(

4)

Figure 3.5.2.1c Selective Repeat ARQ



Forward Error CorrectionFEC is a method of error control that employs the adding of systematic redundancy at the transmit end of a link such that errors caused by the medium can be corrected at the receiver by means of a decoding algorithm. Typically, an encoder and decoder are added to the digital data link. A simple block diagram is shown here.


Part 2: Digital

3.5.2.2: Forward Error Correction

data source encoder modulator

transmitterreceiver

demodulator decoder datauser

Figure 3.5.2.2 FEC



Forward Error CorrectionUsing FEC in satellite communications has two consequences:

More data bits must be transmitted in order to pass the same amount of information, which results in a larger amount of spectrum being used.

Less energy needs to be used on the satellite link in order to a achieve a given bit error rate (BER).

As a consequence, the use of coding increase the amount of spectrum used in order to reduce the amount of power used. Since both are valuable commodities on a satellite, the onus is on the system engineer to pick a level of error correction that will make the best use of a satellite's spectrum and power resources.


Part 2: Digital




Forward Error CorrectionA FEC code detects and corrects errors. This either improves the output error rate of a given channel or permits a reduction in the Eb/No needed to obtain a desired output error rate.

On the other hand, use of a code means that some energy must be shared between information and redundant digits. An error control code is efficient if, for a given code rate, the Eb/No advantage exceeds the redundancy loss. This overall advantage is called the coding gain of the code.

Note that, the lower the Eb/No, the lower the coding gain. Also, at low the Eb/No, the coding gain becomes negative. This threshold phenomenon is common to all coding schemes.


Part 2: Digital




Forward Error CorrectionNote also that powerful error correcting codes can be devised, but would need a special purpose, high speed computer at each end of the link to make them operable. Thus, a comparison is needed between degree of protection, information rate, and complexity of encoding.

There are two classes of Error Correcting Codes:

Block codes for which the input bit stream is broken into fixed-length blocks. Every block contains a fixed number of information bits and redundant bits.

Convolutional codes in which the input bit stream of bits is not broken up into independent blocks but processed continuously. The output code word is not only a function of the present input message but can also be influenced by previous input messages. Thus, a convolutional encoder has memory of previous input messages.


Part 2: Digital





Part 2: Digital

3.5.2.3: Block Coding

Block CodingA block code, as the name implies, groups the input data into blocks of k bits. For each input block of k bits, the encoder produces an output block of N bits. then, n-k additional bits are added. The rate of this code is thus R=k/n.

Block of k bits Block of n bits

There is no memory for block codes; that is, an output block is dependent only on its input block and not on any previous input blocks.

EncoderFigure 3.5.2.3a Block Coding




Part 2: Digital

Block CodingThe ability of the code to correct random errors depends on the minimum number of positions in which any pair of n-digit encoded blocks (Code Words) differ. This number is called the minimum or Hamming Distance of the code. For example, if the following two code words are compared, it can be seen that the Hamming distance between them is of three.

CW1 = { 1 0 1 1 1 0 0 }

CW2 = { 0 0 1 0 1 0 1 }

x x x => d = 3





Part 2: Digital

Block CodingIn general, a code can correct errors, where d is the hamming distance and t is the greatest integer.

Codes can also be used to detect errors, up to e, given by:

e = d-1Block codes are often described with the notation such as (15,11), meaning that n=15 and k=11. Here, the information bits are stored in k=11 storage devices and the device is made to shift n=15 times.

t = d-12


EQ. 3.5.2.3 Block Coding




Part 2: Digital

Block CodingA study of the mathematics of block codes shows that codewords in a block code can be considered to be vectors in a finite vector space (Galois Field Mathematics). As such, the properties of vector mathematics can be brought to bear on block codes.One such vector property is linearity. A code is said to be linear if all the valid codewords can be generated from a linear combination of a finite set of basis codewords. This operation defines a subspace within a larger universe by using a set of independent basis functions. The codewords within the smaller space represent the valid codewords in the universe of all possible codewords. An important property of a linear code is that the sum of any two codewords is also a code word. This property, along with other properties of linear codes, make them easier to decode (e.g. syndrome decoder) and they are thus almost exclusively used in ECC applications.





Part 2: Digital

Block CodingExample: A (7,3) Hamming Code with basis

Codewords: (1001011), (0101110), (0010111)

Gives the following codewords:

(0000000) (0111001)

(0010111) (1110010)

(0101110) (1100101)

(1011100) (1001011)





Part 2: Digital

Block CodingA simple decoder which decodes linear codes is called a Syndrome decoder. The “syndrome” is the portion of the received code word which is outside the vector space of all the valid code words.

If the syndrome is found to be zero, a valid code word has been received.

If the syndrome is not zero, an error has occurred. The syndrome is then used to predict where the error occurred and an error vector is added back to the received code word.

The use of the Syndrome Decoder will be explained in the following slide.





Part 2: Digital

Block CodingSyndrome Decoder


Figure 3.5.2.3b Syndrome Decoder




Part 2: Digital

Block CodingWithin the set of linear codes, there is a subset of codes which are said to be cyclic codes. These codes have the special property that a shift of the bits in any code word also gives a code words. Looking again at the previous example of a linear code will show that the code is also a cyclic code.

Cyclic codes make up the majority of the block codes commonly used in error control coding since they have special mathematical properties which permit the construction of decoders that operate faster than for ordinary linear codes (e.g. Meggit, Error Trapping decoders).





Part 2: Digital

Block CodingLooking at the codewords of the previous example, it can be seen that the code is cyclic.

The codewords from the previous example were:

(0000000) (0111001)

(0010111) (1110010)

(0101110) (1100101)

(1011100) (1001011)





Part 2: Digital

Block CodingThe properties of cyclic codes permit a simplification of the decoder.

In the case of the Meggitt decoder, the only syndrome which needs to be identified is the one indicating that the last bit is in error. If this is the case, the last bit is corrected. If not, the bit is left intact as it is decoded and the registers are roteted so that the next bit is at the output.

Again the process of verifying that the last bit is in error is repeated. The process is repeated until the entire codeword is decoded.





Part 2: Digital

Block CodingMeggit Decoder


Figure 3.5.2.3c Meggit Decoder




Part 2: Digital

Block Coding


Code EfficiencyCode Efficiency n k Code (or Code Rate)

3 1 (3, 1)4 1 (4, 1) 0.25

Single-error Correcting, t=1 5 2 (5, 2) 0.4Minimum Code Separation, 3 6 3 (6, 3) 0.5

7 4 (7, 4) 0.5715 11 (15, 11) 0.7331 26 (31, 26) 0.838

_______________________________________________________________

Triple-error Correcting, t=3 10 4 (10, 4) 0.4Minimum Code Separation, 7 15 8 (15, 8) 0.533_______________________________________________________________

Double-error Correcting, t=2 10 2 (10, 2) 0.2Minimum Code Separation, 5 15 5 (15, 5) 0.33

23 12 (23, 12) 0.52




Part 2: Digital

Block CodingWell known linear block codes include:

• Hamming codes which are single error correcting codes.

• Bose-Chaudhuri-Hocquenghem (BCH) codes which are large, powerful class of random-error correcting cyclic codes. Due to the method used in generating BCH codes, there is no simple expression which relates the m, K, and the number of errors that the code will correct.

• Reed-Solomon codes may be viewed as a non-binary subclass of the general BCH codes. They are useful principally for burst error correction.

• Golay codes are other cyclic binary codes that are capable of correcting up to three random errors in a block of 23 digits.





Part 2: Digital

Block CodingCases where block codes used in satellite communication:

• At high data rates where convolutional decoders are too slow

• In combination with convolutional codes so as to effect error burst suppression (RS concatenated encoders)

• To improve the BER for certain parts of the data flow that are especially sensitive to errors (e.g. ATM packet headers)





Part 2: Digital

Convolutional CodingConvolutional Codes

Convolutional codes, like block codes, produce an n-bit output code word for every m-bit input message.

For a convolutional code, however, the n-bit output code word is not only a function of the present m input bits but is also influenced by the k previous input messages.

Thus, a convolutional encoder has memory of k previous input messages, called the constraint length, which is, in fact, the total number of binary register stages in the encoder.

3.5.2.4: Convolutional Coding




Part 2: Digital


For convolutional codes, m and n are usually small.

Codes can be devised for correcting random errors, burst errors, or both.

Encoding is easily implemented by shift registers.

Most of the FEC techniques for digital communications by satellites use convolutional codes.

A convolutional encoder is composed of one or more K-stage shift registers and N linear algebraic function generators.





Part 2: Digital


The MODULO-2 adders are used to form the output coded symbols, each of which is a binary function of a particular subset of the information bits in the shift register. This can be seen in the following diagram.

Convolutional codes are generally refereed to as either rate=m/n codes or as (n,m,k) codes.





Part 2: Digital

Convolutional CodingConvolutional Encoder


Modulo-2

1 2 3Input

Information

+ + +

. . . . . . K

1 2 n

(bits)

adders

Shift register

SamplerOutput

(Coded symbols)Figure 3.5.2.4a Convolutional Encoder




Part 2: Digital

Convolutional CodingA method of describing a convolutional code is by a coding tree which shows the coded output for any possible sequence of data digits.

The following is a coder for 3-stage shift register and two module-2 adders.


S1Data in

+

A Convolutional Encoder

+Modulo-2

adders

Coded-sequence output

S2 S3

Figure 3.5.2.4b Convolutional Encoder




Part 2: Digital

Convolutional CodingCoding Tree

3.5.2.4: Convolutional Coding11100111000110001110011100011000111001110001100011100111000110

001110011100011011100111000110

00a

11b

10c

01d

11a

00b

01c

10d

01 10

0011

00

11

01

00

00011011

abcdabcdabcdabcd

abcdabcd

00

a =

b =

c =

d =The Code Tree of this Coder is:

Figure 3.5.2.4c Coding Tree




Part 2: Digital

Convolutional CodingCoding Tree

At each branch (node) of the tree, the input information bit determines which direction (i.e. which branch) will be taken, following the convention "up" for zero and "down" for one.

When the first digit is 0, the coder output is 00, and when it is 1, the output is 11.

At the terminal node of each of the two branches we follow a similar procedure corresponding to the "second data" digit. This continues until the Kth data digit on the block.

The path shown dotted is the coded output for input 11010. Also, the code tree becomes repetitive after the third branch.





Part 2: Digital

Convolutional CodingState Transition Diagram

Another method of describing the code is through a state transition diagram. Finite state machines can be characterized by such diagrams where each circle is one state of the machine and an arrow constitutes a valid path from one state to the next. The first number beside each arrow represent the input to the machine that caused it to change state. The second number represents the output of the machine as it changed state.


For the previous circuit, the state transition diagram is as follows:

STATE 00

STATE 01 STATE 10

STATE 11

0/00

0/11

0/01

1/11

1/10

1/01

1/00

0/10

Figure 3.5.2.4d State Transition Diagram




Part 2: Digital


State transition diagrams allow properties of the code to be displayed.

One important characteristic that can be found about a code is if it is a catastrophic code. Such codes have the undesirable property that a finite number of communication errors can force the decoder into a state in which it decodes an infinite number of erroneous bits.





Part 2: Digital


This state transition diagram illustrates the problem of catastrophic codes. Assume with this diagram that the receiver is at state zero and an all zero message is being sent. If a burst of errors in the communication path caused a 11 01 message to be received, the decoder would have moved from state 00 to state 11. If no additional errors were present in the communication stream, the bits received would lead the decoder to output 1’s instead of 0’s since it would stay stuck in State 11 instead of returning to State 00.


STATE 00

STA

TE10

STATE 01

STATE 11

0/00

0/01

0/11

1/11

1/00

1/01

1/10

0/10

Figure 3.5.2.4e State Transition Diagram




Part 2: Digital

Convolutional CodingDecoding a Convolutional Code

There are basically two decoding approaches:

• One approach relies only on the distance properties between codewords over the constraint length. A decoder of this type is a threshold decoder.

• The other approach relies on the tree structures of the code and estimates the original path taken by the encoder. Decoders of this type are maximum likelihood (VITERBI) decoders and sequential decoders .





Part 2: Digital

Convolutional CodingThreshold Decoding

With threshold decoding, the decoder finds the distance between the received sequence and all possible sequences of a certain length. The path which gives the best result is assumed to be the correct path and is thus decoded as such.

Using the tree structure on the next slide, assume that the sequence 00 00 10 00 was received. The metric for each path is marked on the slide as it would be calculated by the decoder. The lowest metric path is the 0 0 0 0 output which has a metric of 1.

This method is a brute force approach which yields poor results for a high number of calculations but which has an algorithm which is very simple to implement.





Part 2: Digital

Convolutional CodingThreshold Decoding


001110011100011011100111000110

0011100111000110

01 10

0011

00

11

01

00

6 6 3 5 5 465 5 5 2 4 2 2 3 1

Figure 3.5.2.4f Threshold Decoding




Part 2: Digital

Convolutional CodingVITERBI Decoding

Among various decoding methods for convolutional codes, VITERBI's maximum likelihood algorithm is one of the best techniques yet evolved for digital communications.

VITERBI decoding uses a specific path decoding algorithm for convolutional codes that significantly reduces the number of computations needed to choose the most probable path.

The algorithm will be shown using the trellis on the following slide. This trellis is a slight modification of the state transition diagram done previously by having consecutive vertical columns representing steps in time as the decoder moves one state to another.





Part 2: Digital

Convolutional CodingVITERBI Decoding Trellis (Example)


Figure 3.5.2.4g VITERBI Decoding Trellis (Example)




Part 2: Digital


VITERBI permits major equipment simplification while obtaining the full performance benefits of maximum-likelihood decoding. The decoder structure is relatively simple for short constraint length codes.

The complexity of VITERBI decoders increases exponentially with the constraint length k of the code, whereas the error probability decreases exponentially with its length.





Part 2: Digital


Any improvement on the error performance by increasing K is expensive in terms of computational effort and storage. Therefore, VITERBI decoders are limited to K < 8 constraint length code, and consequently are used where a moderate error probability is sufficient (10-4 to 10 -5).

Decoding delays are inescapable for VITERBI decoders. The delays corresponds to the path memory storage of each state. In a real time situation where a fixed time delay is required for delivering the data, the total number of computations required grows exponentially with K for VITERBI decoders.





Part 2: Digital

Convolutional CodingSequential Decoding

Sequential decoders are different from maximum likelihood decoders in that the path they decode is not always the best path. Sequential decoders use any of a variety of methods which move backward and forward in the tree to find an optimum path.

Algorithms such as the stack, ZJ, and FANO’s algorithm are all different ways of moving through the tree to find what might be the best path.

The simplest algorithm is the stack algorithm which will be explained in the next slide.





Part 2: Digital


To illustrate stack decoding, let us use the tree structure and the received data used in the previous example and do the following:

1. Both decode paths originating at the root with their metrics are placed on the stack.

2. The stack is sorted.

3. The top node is removed from the stack.

4. The two paths radiating from the removed node are added to the stack.

5. Steps (2) to (4) are repeated until a node reaches the top of the stack which is of the entire receive length.





Part 2: Digital


Path MetricIteration 1 0 0

1 2

Iteration 2 00 001 2

Iteration 3 001 1000 1

01 21 2

Iteration 4 000 10010 2

0011 201 2

12

Iteration 5 0000 1 <--successful path0010 2

0011 201 2

12

0001 3





Part 2: Digital


With VITERBI algorithm, storage and computational complexity are proportional to 2k. As stated before, it is very attractive for constraint length < 8.

To achieve very low probabilities, longer constraint lengths are required, and sequential decoding becomes attractive.

Sequential decoding finds application in severe environments such as deep space and satellite links requiring maximum coding gain.

The coding gain is theoretically in excess of 7 dB at a 10-5 bit error probability. The error performance of sequential decoder is exponentially decreasing with the constraint length K of the code, whereas the computational effort is almost independent of K.





In sequential decoders complexity increases linearly rather than exponentially, as is the case with the VITERBI decoders.

The decoding delay in sequential decoders is a direct consequence of the variability of the computational effort.

In a real-time situation where a fixed time delay is required for delivering the data, the total number of computations required in one time delay grows only linearly with the constraint length K.

The computational requirements of sequential decisions are variable and dependent on the severity of the channel noise.


Part 2: Digital





During periods of low noise, the decoder advances quickly through the tree, seldom following an incorrect branch. However, when the channel noise increases due to its probabilistic nature, the decoder will explore many incorrect paths before finding the correct path.

Because of variable speed with which the decoder advances through the tree, input and output buffers are required to keep the data flow continuous.


Part 2: Digital





There is a finite probability that the decoder will overflow the input buffer before a good path can be found. In this case, the coder is forced to reset itself. This action causes the data buffer to be output uncorrected and it is known as an erasure of the data bits.

To make storage requirements easier, the decoding speed has to be maintained at 10 to 20 times faster than the incoming data rate. This limits the maximum data rate capability.


Part 2: Digital




Convolutional CodingSoft Decision Decoding

The decoders explained so far assume that the demodulator has made a decision that the bit received was either a one or a zero. This type of decoding is referred to as hard-decision decoding. Hard decoding results in frequent ties between paths, which results in a longer and sometimes incorrectly decoded path.

To improve on the situation, certain modulators provide information as to the quality of the signal received. If the decoder is designed to make use of this data, it is referred to as a soft-decision decoder. Such decoders usually have a gain of about 3 dB as compared to a hard-decision decoder.


Part 2: Digital




Convolutional CodingCurrent Decoder Performance

The diagram on the following slide shows the performance of current satellite digital modems.

The first set of curves shows the performance of r=1/2, 3/4 and 7/8 coding. The next set of curves uses a Reed-Solomon (239,256) code in addition to the previous convolutional coding rates for rather impressive results.


Part 2: Digital




Figure 3.5.2.4h Current Decoder Performance



Convolutional CodingComparison Between Sequential and VITERBI Decoding

• VITERBI takes a fixed amount of processing time per symbol received.

• Sequential takes a variable amount of time to decode received symbols.

• In low noise situations, the sequential decoder is faster than VITERBI.

• VITERBI complexity increase exponentially with k while complexity increases linearly for sequential decoders.

• Block decoders are simple and fast.

• Convolutional decoders are more complex and slower.


Part 2: Digital




Convolutional CodingComparison Between Sequential and VITERBI Decoding

• For equivalent code rates, convolutional codes give superior performance.

• At high data rates, convolutional codes are unable to perform the necessary operations in the time available.

Comparison Between FEC and ARQ

• The steep response of the bit-error-rate (BER) to Eb/No makes FEC systems very sensitive to channel degradation such as fading and, unlike ARQ systems, FEC systems are not very robust to a wide range of channel performance variations.


Part 2: Digital




Convolutional CodingComparison Between FEC and ARQ

• Unlike ARQ systems, FEC systems do not require the use of a feedback link nor do they introduce interruptions or delay variations in transfer of the information to the users.

• FEC systems have a constant throughput.• Extensive buffering is not needed for FEC systems (except

for coding and decoding purposes).• ARQ systems have less complex hardware requirements for

error detection.• For satellite data links, due to relatively long round trip

transmission delay, FEC systems are more common than ARQ systems. Most terrestrial data transmission links use ARQ. Here, the throughput is good and large buffers may not be required.


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IDR/IBS LinksIDR and IBS are standards used when accessing the Intelsat satellite system.

Definitions:• IDR - Intermediate Data Rate• IBS - Intelsat Business Services

When a satellite system is installed, there are two possible options available: a closed or open system.

Closed System

In the case of a closed system, only equipment of the same manufacturer, or compatible type, at all nodes of the system will be able to communicate with each other. In reality this means that satellite modem types must be compatible since other equipment has far less influence on system performance.

3.5.2.5: IDR/IBS Links


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IDR/IBS LinksOpen System

In the case of an open system, all equipment must be compatible with a set standard. This standard for Intelsat is IDR/IBS. If the Earth Station equipment is designed to comply with this standard, then it can communicate with any other Intelsat Earth Station.

The requirements for this standard are detailed in Intelsat document series IESS-308 and IESS-309.

Satellite Modems

As mentioned previously, the main component determining compatibility to a standard is the satellite modem. The standard defines specific filtering and data structures.


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IDR/IBS LinksIn a closed system, the modem manufacturer has the flexibility to design equipment that can provide enhancements in performance and/or carrier spacing that may be beneficial to the user. However, it will not communicate with any other manufacturer’s modem.

Manufacturers will sometimes provide the option of selecting the mode of usage. For example, a California microwave modem may be selected to be compatible with a Comstream modem as one of its options.

The IDR/IBS standards specify the framing of the data by the satellite modem but this does not affect the users interface data. The standard in use, whether it be a closed system or IDR/IBS open system, has no affect on the users data structure and is fully transparent.


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IDR/IBS LinksOverhead Channels

The IDR/IBS standard defines the use of part of the aggregate data stream for functions other than the main data stream. This allows for alarm transmission and can also provide an engineering orderwire. Generally, closed system satellite modems do not provide extra overhead bits for these type of functions. Some modems are capable of closed or open system operation and may have the ability to use this overhead for a separate asynchronous channel when the closed system option is selected.



IDR/IBS LinksThe IDR and IBS standards differ slightly in the use of this overhead channel. IDR defines 96 kbps to be used, whereas IBS defines 1/15th of the terrestrial data rate will be added for overhead. For low data rates the IBS standard will of course be somewhat restrictive in what can be carried over the satellite link.

IDR

For information rates: 1.544, 2.048, 6.312, 8.448, 32.064, 34.368, and 44.736 Mbps, the overhead structure is defined to provision for Engineering Service Circuits (ESC) and maintenance alarms using 96 kb/s. This overhead increases the data rate of these carrier sizes by 96 kbit/s.

Whether the IDR or IBS option is selected on the modem, the alarms will allow users at either end of a satellite link to determine the status of the other end (backward alarms).


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