Process FlowProcess Flow StepsSteps

– Choose a substrateChoose a substrate Add epitaxial layers if neededAdd epitaxial layers if needed

– Form n and p regionsForm n and p regions– Deposit contacts and local interconnectsDeposit contacts and local interconnects– Deposit Multilevel metalization with isolating Deposit Multilevel metalization with isolating

dielectrics between layersdielectrics between layers– Backside processingBackside processing– Bonding pad depositionBonding pad deposition– Final testFinal test– Die separationDie separation– PackagingPackaging

IntroductionIntroduction

So far, we have studied each of the So far, we have studied each of the unit processes of IC fabrication unit processes of IC fabrication – The details of each process depend on The details of each process depend on

the context in which they are used—i.e., the context in which they are used—i.e., they depend on what comes before and they depend on what comes before and after each stepafter each step

CMOS Process FlowCMOS Process Flow

A simple CMOS circuit is the inverter A simple CMOS circuit is the inverter – A low on the input prevents the NMOS A low on the input prevents the NMOS

from conducting and allows the PMOS to from conducting and allows the PMOS to conduct, thus drawing the output highconduct, thus drawing the output high

– A high on the input allows the NMOS to A high on the input allows the NMOS to conduct and prevents the PMOS from conduct and prevents the PMOS from conducting, thus pulling the output lowconducting, thus pulling the output low

CMOS Inverter CircuitCMOS Inverter Circuit

CMOS Process FlowCMOS Process Flow Must be able to build both NMOS Must be able to build both NMOS

and PMOS together on the same and PMOS together on the same chipchip– In other circuits, components such as In other circuits, components such as

resistors and capacitors may be resistors and capacitors may be integrated on the chipintegrated on the chip

Choosing a SubstrateChoosing a Substrate

– Type (N or P)Type (N or P)– Resistivity (doping level)Resistivity (doping level)– Crystal orientationCrystal orientation– Wafer sizeWafer size– Wafer flatnessWafer flatness– Trace impuritiesTrace impurities

Most CMOS is built on P-type (100) of Most CMOS is built on P-type (100) of moderate resistivity (25-50 moderate resistivity (25-50 -cm)-cm)– This corresponds to a doping of about This corresponds to a doping of about

10101515 cm cm-3-3

Choosing a SubstrateChoosing a Substrate

The typical well doping is 10The typical well doping is 101616 – 10 – 101717 cm cm--

3 3 near the wafer surface near the wafer surface – This process is called the “twin well” or This process is called the “twin well” or

“twin tub” process and can be much better “twin tub” process and can be much better controlled by using a higher-doped controlled by using a higher-doped substratesubstrate

The crystal orientation (100) is The crystal orientation (100) is determined by the low defect determined by the low defect concentrations in the SiOconcentrations in the SiO22/Si interface in /Si interface in this orientationthis orientation

Modern CMOS chips have millions of Modern CMOS chips have millions of active devices (NMOS and PMOS) side active devices (NMOS and PMOS) side by side in a common silicon substrateby side in a common silicon substrate– These devices can not interact with each These devices can not interact with each

other except via their circuit other except via their circuit interconnectionsinterconnections

Isolation is obtained by growing a Isolation is obtained by growing a thick layer of SiOthick layer of SiO22 between each of between each of the active devices the active devices – LOCOS (LOCOS (LOCLOCal al OOxidation of xidation of SSilicon).ilicon).

Wafer After LOCOSWafer After LOCOS

Prior to LOCOS, a thin silicon oxide layer capped with Prior to LOCOS, a thin silicon oxide layer capped with silicon nitride (or a tri-layer of oxide, polysilicon, and silicon nitride (or a tri-layer of oxide, polysilicon, and nitride) was grown and patterned to prevent a thick oxide nitride) was grown and patterned to prevent a thick oxide from growing everywhere.from growing everywhere.

Device Isolation: Device Isolation: Shallow Trench IsolationShallow Trench Isolation

Etch trenches in the Si, which are Etch trenches in the Si, which are then fill with a deposited oxidethen fill with a deposited oxide– Process begins as with LOCOSProcess begins as with LOCOS– Fluorine-based etch is used to etch Fluorine-based etch is used to etch

through the nitride, the oxide, and into through the nitride, the oxide, and into the waferthe wafer The trenches are approximately 0.5 The trenches are approximately 0.5 m m

deepdeep

Shallow Trench IsolationShallow Trench Isolation

Shallow Trench IsolationShallow Trench Isolation This process eliminates the long time, This process eliminates the long time,

high temperature LOCOS oxidationhigh temperature LOCOS oxidation– Stresses are not so severe and the film Stresses are not so severe and the film

thicknesses do not have to be so tightly thicknesses do not have to be so tightly controlledcontrolled

– Walls of trenches need to be vertical or Walls of trenches need to be vertical or slightly sloped; there can be no undercuttingslightly sloped; there can be no undercutting

– Top and bottom corners of trenches need to Top and bottom corners of trenches need to be slightly rounded to avoid electrical effects be slightly rounded to avoid electrical effects associated with high fields at sharp cornersassociated with high fields at sharp corners

Shallow Trench Isolation Shallow Trench Isolation (STI)(STI)

A thick layer of SiOA thick layer of SiO22 is deposited by CVD is deposited by CVD– This process cannot leave gaps or voids in the trenchesThis process cannot leave gaps or voids in the trenches

Wafer surface is polished using chemical-Wafer surface is polished using chemical-mechanical polishing (CMP)mechanical polishing (CMP)– to remove the excess oxide and flatten surfaceto remove the excess oxide and flatten surface

Shallow Trench IsolationShallow Trench Isolation

Final Device StructureFinal Device Structure

Contact and Local Contact and Local InterconnectsInterconnects

Must be connected electrically Must be connected electrically togethertogether– The first level is called the local The first level is called the local

interconnectinterconnect The first step is to remove the oxide The first step is to remove the oxide

over the source and drainover the source and drain– This etch may be performed without a This etch may be performed without a

mask because the oxide to be removed mask because the oxide to be removed is very thinis very thin

Contacts and Local Contacts and Local InterconnectsInterconnects

Deposit 50 – 100 nm of Ti over the Deposit 50 – 100 nm of Ti over the entire waferentire wafer– This is usually done by sputtering This is usually done by sputtering

– The wafers are then heated in NThe wafers are then heated in N22 at 600 at 600 C for 1 minuteC for 1 minute Ti reacts with Si to form TiSiTi reacts with Si to form TiSi22 where they are where they are

in contactin contact This consumes some Si so the source and This consumes some Si so the source and

drain junctions made deeper than needed. drain junctions made deeper than needed.

Silicide FormationSilicide Formation

Contact and Local Contact and Local InterconnectsInterconnects TiSiTiSi22 is an excellent conductor and is an excellent conductor and

forms low resistance contacts with forms low resistance contacts with the Si and the poly-Sithe Si and the poly-Si

Ti also reacts with NTi also reacts with N22 to form TiN to form TiN (the dotted layer(the dotted layer– Also a conductor, but it is not as good Also a conductor, but it is not as good

as TiSias TiSi22. . – It is only used for local (short distance) It is only used for local (short distance)

interconnectsinterconnects Resistance of long lines made of TiN would Resistance of long lines made of TiN would

cause unacceptable RC delays in most cause unacceptable RC delays in most circuitscircuits

Contact and Local Contact and Local InterconnectsInterconnects

Wafer is then heated to 800 C for 1 Wafer is then heated to 800 C for 1 min to reduce the resistivity of the min to reduce the resistivity of the TiSiTiSi22 to its final value to its final value

Multilevel Metal FormationMultilevel Metal Formation

The final steps are the deposition and The final steps are the deposition and patterning of two layers of metal patterning of two layers of metal interconnectsinterconnects– At this stage the wafer is highly non-planar. At this stage the wafer is highly non-planar.

The many layers deposited and patterned The many layers deposited and patterned leave many hillocksleave many hillocks Problems with discontinuities at the steps and Problems with discontinuities at the steps and

because of thin regions where metal crosses the because of thin regions where metal crosses the stepssteps

photolithography is very difficult on non-planar photolithography is very difficult on non-planar surfacessurfaces

Multilevel Metal FormationMultilevel Metal Formation Many techniques have been Many techniques have been

devised to planarize the surface. devised to planarize the surface. – A fairly thick layer of SiOA fairly thick layer of SiO22 is deposited is deposited

on the wafer by CVD or LPCVD. on the wafer by CVD or LPCVD. Layer is thicker than the largest steps on Layer is thicker than the largest steps on

the surface (typically 1 the surface (typically 1 m)m) Often doped with either or both P and B Often doped with either or both P and B

to create a phosphosilicate (PSG) or to create a phosphosilicate (PSG) or borophosphosilicate glass (BPSG)borophosphosilicate glass (BPSG)

Multilevel Metal FormationMultilevel Metal Formation

Wafer is heated to 800 – 900 C to allow Wafer is heated to 800 – 900 C to allow the glass to flow to smooth the surfacethe glass to flow to smooth the surface– Glass reflow does not fully planarize the Glass reflow does not fully planarize the

surfacesurface Layer of photoresist was spun on to fill in Layer of photoresist was spun on to fill in

the valleysthe valleys– Wafer is then plasma etched under Wafer is then plasma etched under

conditions that etch the photoresist and the conditions that etch the photoresist and the SiOSiO22 equally equally

– Etch with no mask until resist (and some of Etch with no mask until resist (and some of the oxide) is gonethe oxide) is gone

Multilevel Metal FormationMultilevel Metal FormationOr planarize the surface using CMPOr planarize the surface using CMP

Multilevel Metal FormationMultilevel Metal Formation

Multilevel Metal FormationMultilevel Metal Formation

The wafer is now covered with a The wafer is now covered with a deposition of TiN or a Ti/TiN bilayer deposition of TiN or a Ti/TiN bilayer using either sputtering or CVDusing either sputtering or CVD– Layer is a few tens of nanometers thickLayer is a few tens of nanometers thick

Provides good adhesion to SiOProvides good adhesion to SiO22 and other and other underlying materialsunderlying materials

It also acts as a barrier between the upper It also acts as a barrier between the upper metal layers and the lower local metal layers and the lower local interconnect layersinterconnect layers

Tungsten (W) is deposited by CVDTungsten (W) is deposited by CVDHFWHWF 63 26

Multilevel Metal FormationMultilevel Metal Formation

Multilevel Metal FormationMultilevel Metal Formation

The surface is again planarized using The surface is again planarized using CMP to remove the TiN and W CMP to remove the TiN and W everywhere except in the contact everywhere except in the contact holesholes

This process of etching, filling an This process of etching, filling an planarizing the contact holes is called planarizing the contact holes is called the the damascenedamascene process process

Multilevel Metal FormationMultilevel Metal Formation

Multilevel Metal FormationMultilevel Metal Formation Metal 1 is deposited (usually) by using Metal 1 is deposited (usually) by using

sputteringsputtering– It is defined using resist and etchback It is defined using resist and etchback

processprocess– Al usually has a small amount of Si and CuAl usually has a small amount of Si and Cu

Cu is now replacing Al in these metal Cu is now replacing Al in these metal layerslayers– Ti and W layers prevent Cu indiffusion into Ti and W layers prevent Cu indiffusion into

Si wafer and protect Cu from harsh Si wafer and protect Cu from harsh chemicals used to open dielectrics chemicals used to open dielectrics deposited on top of metalizationdeposited on top of metalization

Multilevel Metal FormationMultilevel Metal Formation

Multiple metal levels are deposited Multiple metal levels are deposited by repeating these steps.by repeating these steps.– After the final metal layer is deposited, a After the final metal layer is deposited, a

capping protective layer of SiOcapping protective layer of SiO22 or Si or Si33NN44 is depositedis deposited

– Provides some protection needed for Provides some protection needed for handling during the packaging processhandling during the packaging process

Final anneal at 400-450 C in forming Final anneal at 400-450 C in forming gas gas – Alloy metal contacts to reduce contact Alloy metal contacts to reduce contact

resistance between metal and Siresistance between metal and Si– Reduce the electrical charges in the Reduce the electrical charges in the

Si/SiOSi/SiO22 interface interface

Multilevel Metal FormationMultilevel Metal Formation

Bonding padsBonding pads Thick layer of metalization Thick layer of metalization

where connections off-chip where connections off-chip are madeare made– Wire bondsWire bonds– Ball Grid Array (BGA)Ball Grid Array (BGA)– Flip-chip metalization (solder)Flip-chip metalization (solder)

http://www.standardics.nxp.com/packaging/lfbga/

http://www.answers.com/topic/bga

Wire is compressed into thick metal region on wafer. Ball bond is on the left; wedge bond in on the right. Wedge bonds have a smaller footprint than ball bonds.

http://www.westbond.com/pics/Bond7.jpg

http://www.caltexsci.com/CX-3000.htm

ElectroplatingElectroplating

Voltage drop between wafer and electrode Voltage drop between wafer and electrode drives metal ions in a solution to the wafer drives metal ions in a solution to the wafer surface.surface.

Exchange of charge causes ions to Exchange of charge causes ions to become neutral atoms and precipitate out become neutral atoms and precipitate out of solution on to wafer.of solution on to wafer.– Thickness of greater than 100 microns can be Thickness of greater than 100 microns can be

depositeddeposited– Some alloy compositions and low temperature Some alloy compositions and low temperature

solders can be plated.solders can be plated. Au/Sn, In Au/Sn, In

DicingDicing

Diamond edged saw blade.Diamond edged saw blade.– Wafer mounted on tacky tape, which will Wafer mounted on tacky tape, which will

be used to transport chips to final testbe used to transport chips to final test Wafer surface is protected from chips and Wafer surface is protected from chips and

debris generated during sawingdebris generated during sawing Width of saw cut is called a kerfWidth of saw cut is called a kerf

– Usually 2-3 times the width of the saw bladeUsually 2-3 times the width of the saw blade Damage along kerf can propagate into chip Damage along kerf can propagate into chip

during mechanical, electrical, and thermal during mechanical, electrical, and thermal stressstress

– Design rules incorporate a margin around area to Design rules incorporate a margin around area to be cut to minimize the electrical and thermal stressbe cut to minimize the electrical and thermal stress