process agnostic library migration...
TRANSCRIPT
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ECE6332 VLSI Design Class Project
Need for Speed: Process Agnostic Library
Migration Automation
Joseph MurrayLijun Li
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Outline
● Motivation
● Approach
● Comparison● Summary
ECE6332 VLSI Design Class Project
PyCell Studio
Cadence SKILL
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Why Process Agnostic Migration Automation
Project Purpose: 1. Demonstrate the concept2. Evaluation
ECE6332 VLSI Design Class Project
Need for Migration
Standard Cells(Library)
Need for Automation
High Cost of New Standard Cells
Need for OurOwn Automation
ASICDesign
Failure of GeometricShrinking
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PyCell Studio: Design OverviewECE6332 VLSI Design Class Project
PyCell: Based on PythonFree to use and multiplatformOpen Access databaseGeared towards parameterized cell designOur home-made PyCell recipe @ ECE Wiki
Parameterized Cell Methodology:
Parameterized Cell(P-Cell)
Technology File
Instantiated Cell
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PyCell Studio: MethodologyECE6332 VLSI Design Class Project
Python Script
(P-Cell)
Compiling
Error
LayoutDatabase File
PyCell API
Technology File
DRC
Pass
Final Layout
Fail
PassIn design...
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PyCell Studio: Inverter @130nmECE6332 VLSI Design Class Project
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PyCell Studio: Inverter @180nmECE6332 VLSI Design Class Project
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PyCell Studio: NAND @130nmECE6332 VLSI Design Class Project
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PyCell Studio: NAND @180nmECE6332 VLSI Design Class Project
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PyCell Studio: Pros & ConsECE6332 VLSI Design Class Project
Pros
DRC automatically met Relatively simple design (almost no more than geometry)
Cons
Every rule must be accounted for Newly developed technology may not be accounted for Heavy scripting (e.g.: 300 lines for an inverter)
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Cadence SKILL: Methodology 1Quality By Design (QbD)
ECE6332 VLSI Design Class Project
Layout Specification
TechnologyFile
LoadingLayout
Cadence Virtuoso
MigrateLayout
SKILLScript
DRC
Pass
Final Layout
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Cadence SKILL: InverterECE6332 VLSI Design Class Project
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Cadence SKILL: NANDECE6332 VLSI Design Class Project
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Cadence SKILL: NORECE6332 VLSI Design Class Project
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Cadence SKILL: Methodology 2Adaptive Migration and Constraint Relaxation
Hand-drawnStandard Cell
LoadLayout
Cadence Virtuoso
Partial MigrationOf Layout
Identify ErrorsDRC
Error
Migration Complete
Final Layout
Associate Errors With Layout
Shapes
Identify Error Type
Migration Not Complete
Relax positionOr Size
Constraint
Based on the work of Q. Tang, et al
ECE6332 VLSI Design Class Project
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Adaptive Migration
P-Tap 0.6ami P-Tap Simulated Technology Migration, Non-Adaptive.Error: Via must be 0.6um square.
P-Tap Simulated Technology Migration, Adaptive. Error resolved
ECE6332 VLSI Design Class Project
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Adaptive Migration: Pros & Cons
Pros
Requires no additional work. Mature literature on the subject. Adapts to new design rule requirements Same approach may be used for optimization. Built in SKILL functions (Not used here).
Cons
Adaptive is very complex. Large up front development.
ECE6332 VLSI Design Class Project
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Evaluation: Comparison of ToolsECE6332 VLSI Design Class Project
PyCell Studio Cadence SKILL
Scripting Language Python SKILL (LISP-like)
Cost Free to use but pay to get commercial support
Pay to use and get commercial support
Extension Almost none, have to interface with 3rd party
Good
Community support
Almost none Good
Emphasis Parameterized cell Generic
Database Open Access database CDSStart supporting OA
Cadence is a better candidate
* Cadence has a toolbox of doing layout compaction
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Evaluation: Methodology RecommendationQbD with Adaptive Migration and Constraint Relaxation
ECE6330 VLSI Design Class Project
Hand-drawnStandard Cell
TechnologyFile
LoadingLayout
Cadence Virtuoso
Partial MigrationOf Layout
Error Handling/
Optimization
DRCError
Migration Complete
Final Layout
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SummaryECE6332 VLSI Design Class Project
The motivation of this project
Two tools: PyCell and Cadence SKILL
Different approaches
Evaluation
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THANKS !
QUESTIONS ?
ECE6332 VLSI Design Class Project