proceedings ofthe ieee 1986
TRANSCRIPT
Proceedings of the
IEEE 1986
CUSTOM INTEGRATED CIRCUITS
CONFERENCE
Rochester Riverside Convention Center
Genesee Plaza-Holiday Inn
Rochester, New York May 12-15, 1986
UNIVERSITATSB1BLI0THEKHANNOVER
TECHNISCHESNFORMATIONSBIBLIOTHEKx
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The CICC '86 is sponsored by the IEEE Electron Devices Society, the IEEE Rochester Section,and the IEEE Solid-State Circuits Council. Its aim is to bring together designers, producers, and
users of custom IC's to discuss recent developments and future directions in custom integratedcircuits,
86CH2258-2
1*
CONTENTS
MONDAY MORNING Holiday Hall (ABCD) Holiday Inn PAGE
8:30 WELCOME/OPENING REMARKS
Lynn F. Fuller, General Chairman
Tom G. Foxall, Conference Chairman
8:50 "CICC '86-TECHNICAL PROGRAM"
Dick Bryant, Technical Program Committee Chairman
9:00 KEYNOTE ADDRESS
"ASIC—A Look Ahead"
Wilfred J. Corrlgan, Chairman & Chief Executive Officer, LSI Logic Corp., Milpitas, CA
HIGH PERFORMANCE CELL LIBRARIES 1
Chairman; K. Venkateswaran
Co-Chairman: Alan B. Grebene
9:45 A High Performance, Multlsourceable, Scalable CMOS Cell Family 2
Ft. Newton, M. Lantz, National Security Agency, Ft. Mead, MD
10:10 A CMOS Standard Cell Library for VHSIC Applications 6
D. Allen, S. Boon, J. Smith, VTC Inc., Bloomington, MN
10:35 A Bit-Modular Cell Library Optimized for Data-Path Applications 10
R. C. Mason, M. T. Fertsch, Raytheon Microelectronics Center, Andover, MA
11:00 Megacells: Augmenting Silicon Compilation for ASIC Chip Design 15
J. Lipman, D. McMillan, VLSI Technology, Inc., San Jose, CA
11:25 A 350 Picosecond ECL Standard Cell Library 18
J. M. Wisted*, B. Chang**, M. D. Richard**, N.T. Mavrogenis*, VTC Inc., Bloomington, MN*, Quadic Systems, South
Portland ME**
11:50 A High-Performance 3|xm CMOS Analog Standard Cell Library 21
C. Laber*, C. Rahlm*, S. Dreyer*, G. Uehara*, P. Kwok*, P. R. Gray**, Micro Linear Corp., San Jose, CA*, Univ. of
California, Berkeley, CA**
MONDAY MORNING Mini Ballroom (EFG) Holiday Inn PAGE
CUSTOM SENSOR CIRCUITS 25
Chairman: Jagdlsh TandonCo-Chairman: T. H, Lee
9:45 An Integrating Sense Amplifier for a Magnetic Bubble Memory System 26
W. C. Black, Jr.*, W. Questo**, Consultant, Cedar Rapids, IA*, Intel Corp., Folsum, CA**
CONTENTS
MONDAY MORNING Mini Ballroom (EFG) Holiday Inn PAGE
10:10 A Magnetically-Controlled Oscillator in CMOS Technology 30
I. A. McKay, A. Nathan, I. M. Filanovsky, H. P. Baltes, Univ. of Alberta, Edmonton, Alberta, Canada
10:35 CMOS Integrated Silicon Pressure Sensor 34
T. Ishihara, M, Hirata, K. Suzuki, H. Tanigawa, NEC Corp., Kawasaki, Japan
11:00 An Integrated Amplifier for a Vibrating String Oscillator 38
F. Doorenbosch, Mettler Instrumente AG, Greifensee, Switzerland
11:25 A Smart Motor Control IC Featuring: Motor Speed Control: Stall Sense: and Interval Timer 42
S. S. Yole, Cherry Semiconductor Corp., East Greenwich, Rl
MONDAY MORNING Lilac Ballroom North Convention Center PAGE
FABRICATION TECHNOLOGIES 45
Chairman: Marc Hartranft
Co-Chairman: Susumu Kohyama
9:45 Device Characterization of a LO^m CMOS Technology for Logic and Custom VLSI Applications 46
L, Tran, R. A. Ashton, B. R. Jones, C. W. Lawrence, D. A, McGillis, AT&T Bell Labs, Allentown, PA
10:10 A Compact CMOS Process for VLSI Fabrication 51
K. Y. Tsao*, H. A. Waggener**, AT&T Bell Labs, Skokie, IL*, AT&T Bell Labs, Murray Hill, NJ**
10:35 A Configurable CMOS SRAM Using a Seeded, Laser Recrystallized Polysilicon on Insulator Process 55
D. Ganousis, G. Collins, S. Sritharan, D. Cooper, Colorado State univ., Fort Collins, CO
11:00 A Single Poly EPROM For Custom CMOS Logic Applications 59
R. Kazerounlan, B. Eitan, WaferScale Integration, Inc., Fremont, CA
11:25 A Subnanosecond Bi-CMOS Gate-array Family 63
H. Nakashiba, K. Yamada, T. Hatano, A. Denda, N. Kusunose, E. Fuse, M. Sasaki, NEC Corp., Kawaski, Japan
11:50 GaAs Integrated Circuit Manufacturing Technology Comes of AgeB. M. Welch, D. Nelson, Y-D Shen, Giga Bit Logic, Newbury Park, CA
67
CONTENTS
MONDAY MORNING 101 Meeting Rooms Convention Center PAGE
BUILDING BLOCK ICs FOR DIGITAL SIGNAL PROCESSING SYSTEMS 73
Chairman: Lauren ChristopherCo-Chairman: Harold Scalf
9:45 A VLSI Pipeline Number Theoretic Transform Processor 74
H. Amir-Alikhanl, O. R. Hinton, R. A. Saleh, University of Ken, Canterbury, Kent, England
10:10 The Design of a DSP Datapath for Professional Digital Audio Systems 78
R. Woudsma, D. Chong, Philips Research Labs, Eindhoven, The Netherlands
10:35 Design of New High-Speed Digital Signal Processor 82
T. Jufuku, Y. Mori, A. Nomura, M. lida, N. Ichiura, H. Ishida, T. Nakamura, M. Kanou, OKI Electric Industry Co., Ltd.,Tokyo, Japan
11 -.00 A 25 MHz VLSI Signal Processor 86
M. T. Fertsch*, R. C. Mason*, P. Ludwig**, J. M. Fitzgerald***, Raytheon Co., Andover, MA*, Raytheon Co., Bedford,MA**, Honeywell, Inc., Clearwater, FL***
11:25 A Testable, Asynchronous Systolic Array Implementation of an IIR Filter 90
D. Rana*, S. P. Levitan*, D. A. Carlson*, C. E. Hutchinson**, Univ. of Massachusetts, Amherst, MA*, Dartmouth
College, Hanover, NH**
11:50 Extending Booth's Algorithm for N Cascaded Multipliers 94
L. Finegold, United Technologies Microelectronics Center, Colorado Springs, CO
12:15 Late Paper 97
A Sub 10ns Low Power Bipolar 16x16 Bit MultiplierB. E. Miller, R. E. Owen, Bipolar Intregrated Technology, Inc., Saratoga, CA
MONDAY AFTERNOON Holiday Hall (ABCD) Holiday Inn PAGE
SILICON COMPILERS 101
Chairman: Allan Goodman
Co-Chalrman: Don Black
1:40 TUTORIAL 102Silicon CompilationD. D. Gajski, N. D. Dutt, B. M. Pangrie, Univ. of Illinois, Urbana, IL
2:25 Automatic Layout Generation of Real-Time Digital Image Processing Circuits 111P. A. Ruetz, R. Jain, C. S. Shung, J. M. Rabey, G. M. Jacobs, R. W. Brodersen, Univ. of California, Berkeley, CA
CONTENTS
MONDAY AFTERNOON Holiday Hall (ABCD) Holiday Inn PAGE
2:50 An Expert Silicon Compiler 116
D. D. Gajski*, A. Orailoglu**, C. D. Bosco***, B. Kuhn****, Univ. of Illinois, Urbana, IL*, Gould Res. Center, RollingMeadows, IL**, Electronic Tech. & Device Lab, Fort Monmouth, NJ***, U.S. Army Laboratory Command****
3:15 A Standard-Cell Based Silicon Compiler 120
G. Kedem, K. Kozminski, Duke University, Durham, NC
3:40 A Switched Capacitor Filter Compiler 125
W. J. Helms*, K. C. Russell**, Univ. of Washington, Seattle, WA*. Seattle Silicon, Bellevue, WA**
4:05 A Two-Level Interactive Approach to Silicon Compilation 636
S. S. Patll, H. Ravindra, P. E. Black, R. Kapur, R. Singh, E. Laiman, Cirrus Logic, Inc., Milpitas, CA
4:30 Circuit Improvement Using Precedent Based Reasoning 129
R. H. Lathrop*, R. S. Kirk**, MIT Artificial Intelligence Lab, Cambridge, MA*, Gould AMI Semiconductors, Santa Clara,CA**
MONDAY AFTERNOON Mini Ballroom (EFG) Holiday Inn PAGE
INTEGRATED POWER AND INTERFACE TECHNIQUES 133
Chairman: Wesley A. Vincent
Co-Chairman: David E. Brown
2:00 INVITED 134
Recent Developments and Trends In Intelligent Power IC TechnologiesB. Murarl, SGS Microelecttronica SpA, Milano, Italy
2:25 BIMOS: A Merged Technology for Custom and "Semi-Standard" Power Interface ICs 138
P. R. Emerald, Sprague Electric Co., Worcester, MA
2:50 Open-Loop Gain Limitations for Push-Pull Off-Chip-Drivers 143
N. Raver, IBM Corp., Yorktown Heights, NY
3:15 Power Supply Voltage for Future VLSI 149
J. W. Mathews, C. K. Erdelyi, IBM General Technology Div., Essex Junction, VT
3:40 A Fully Integrated Digital Signalling Interface IC 153
D. M. Embree*, H. G. Ansell*, D. A. Lane**, C. R. Crue**, J. P. Hein*, AT&T Bell Labs, Reading, PA*, AT&T Bell Labs,North Andover, MA**
4:05 A 32-Mblt/s CMOS Integrated Transceiver with an Analog PLL for a Fiber Optic Data Link 157
H. Kraemer, H. Sporer, E. Wolter, T. Zellerhoff, SIE-MENS AG, Munchen, West Germany
CONTENTS
MONDAY AFTERNOON Mini Ballroom (EFG) Holiday Inn PAGE
4:30 Transmitter and Receiver Integrated Circuits for a 200 Mbit/s Optical Data Link 161
O. G. Petersen, P. C. Davis, M. A. Novotny, AT&T Bell Labs, Reading, PA
MONDAY AFTERNOON Lilac Ballroom North Convention Center PAGE
DIGITAL SIGNAL PROCESSING IN CUSTOM ICs 165
Chairman: Fathy Yassa
Co-Chairman: Tom Foxall
2:00 A Low Cost Custom IC for Real Time Image Median Filtering 166
N. Demassieux, F. Jutand, M. Dana, E.N.S.T. Paris, France
2:25 Integrated FIR Median Hybrid Filter 170
O. Vainio, P. Heinonen, Y. Neuvo, Tampere Univ. of Technology, Tampere, Finland
2:50 Gate Array Implementation of a Wldrow-Hoff Least Mean Squared (LMS) Error Filter 173
P. Phillips*, G. Saulnier**, P. Das***, IBM, Hopewell Junction, NY*, GE Corp., Schenectady, NY**, Rensselaer
Poltech. Inst., Troy, NY***
3:15 A VLSI Reed Solomon Encoder: An Engineering Approach 177
G. K. Maki, P. A. Owsley, K. B. Cameron, J. C. Shovic, Univ. of Idaho, Moscow, ID
3:40 Custom ICs for the Ray-Casting Machine 182G. Kedem, J. L Ellis, K. E. Bartsch, R. Subrahmanyan, M. Tate, K. Kozminski, W. Krakow, Duke Univ., Durham, NC
4:05 PCM Conference and Attenuation/Noise Suppression Circuit 186C. Nguyen, A. Pariani, SGS Microelecttronica, Milano, Italy
4:30 Speech Detector for a DSI System 189
H. J. F. Malavazi, J. R. G. Santos, A. S. Pires, E. F. J. Castro, J. S. Yamamoto, D. J. S. Conti, G. Kanno, A. R. Vivaldi,TELEBRAS/CPqD, Campinas, Brazil
MONDAY AFTERNOON 101 Meeting Rooms Convention Center PAGE
DEVICE AND CIRCUIT MODELING 195
Chairman: Peter LloydCo-Chairman: David Embree
CONTENTS
MONDAY AFTERNOON 101 Meeting Rooms Convention Center PAGE
1:40 TUTORIAL 196
Integration of Device and Circuit Simulations
H. K. Dirks, University of Aachen, Aachen, West Germany
2:25 A Unified Physical Device Modeling Environment 203
K. Doganls, S. Hailey, Meta-Software, Inc., Campbell, CA
2:50 Hot Electron Effect on MOSFET Terminal Capacitances 208
C. T. Yao*, M. Peckerar*, D. Friedman**, H. Hughes*, Naval Research Lab., Washington, DC*, Harvard Univ.,Cambridge, MA**
3:15 VTMOS, A Two-Dlmenslonal Simulation Program for the Threshold Voltage and Subthreshold Current of VLSI 212
MOSFET Devices
S. G. Chamberlain**, S. Ramanan*, RIT, Rochester, NY*, Univ. of Waterloo, Waterloo, Ontario, Canada**
3:40 A Universal SPICE Model Development and Design Interface for Digital GaAs 216
F. L. Huang, S, E. Sussman-Fort, L. E. Lach, Gould, Inc., Rolling Meadows, IL
4:05 Models for the Optimization of Novel j-MOS Power Transistor Parameters 221
H. S. Abdel-Aty-Zohdy, Oakland University, Rochester, Ml
TUESDAY MORNING Holiday Hall (ABCD) Holiday Inn PAGE
DESIGN METHODOLOGIES 227
Chairman: Gregory W. Ledenbach
Co-Chairman: Peter M. Zeitzoff
9:10 A Comparison of Standard Cell and Gate Array Implementations in a Common CAD System 228
H. S. Jones, Jr., P. Nagle, H. T. Nguyen, GE Semiconductor, Research Triangle Park, NC
9:35 A User Programmable Reconfigurable Logic Array 233
W. S. Carter, K. Duong, R. H. Freeman, H-C Hsieh, J. Y. Ja, J. E. Mahoney, L. T. Ngo, S. L Sze, Xilinx, San Jose, CA
10:00 Zipper CMOS 236
C. M. Lee, E, W. Szeto, Bell Communications Research, Inc., Morristown, NJ
10:25 A Laser Programmable CMOS Array for Random Logic Design 240
J. Alspector, C. Lee, R. Contolinl, Bell Communications Research, Morristown, NJ
10:50 QuickChlp 4:A Methodology for the Prototyping of Mixed Analog-Digital Designs 244
R. Sparkes, Tektronix, Inc., Beaverton, OR
CONTENTS
TUESDAY MORNING Holiday Hall (ABCD) Holiday Inn PAGE
11:15 Multilevel Differential Logic—A New Design Technique 249
G. W. Birchby, Ferranti Electronics Ltd., Oldham, England
TUESDAY MORNING Mini Ballroom (EFG) Holiday Inn PAGE
PACKAGING AND INTERCONNECTION 253
Chairman: David E. Brown
Co-Chairman: David M. Lewis
8:50 TUTORIAL fPhotonic Interconnection
D. A. Kahn, Bell-Northern Research, Ottawa, Ontario, Canada
9:35 New Developments in Coflred Multilayer Ceramics for Custom Microelectronics 254
J. Reshey, Tektronix, Inc., Beaverton, OR
10:00 Application Specific Packaging for Video Display Drivers 256
S. Wetterling, M. R. Ehlert, Tektronix, Inc., Beaverton, OR
10:25 Adaptive Routing for Defect Avoidance in Discretionary Wafer Scale Interconnections 260
B. Donlan, H. Lin, R. Rajapakse, J. F. McDonald, Rensselaer Polytechnic Institute, Troy, NY
10:50 An Evolutionary Path for Digital System Design Based on a 8K-Gate Bipolar Macrocell Array 264
N. M. Griffin, L. W. Richter, R. C. Weintritt, C. S. Wong, Honeywell Information Systems, Phoenix, AZ
TUESDAY MORNING Lilac Ballroom North Convention Center PAGE
PLACEMENT AND ROUTING 271
Chairman: Mark Horowitz
Co-Chairman: Jake Buurma
9:10 Interactive Placement Tools for CMOS Gate Arrays 272
D. W. Hlghtower, T, P. Weis, F. Z. Marron, J. H. Dickhoff, General Electric Co., Research Triangle Park, NC
9:35 ThunderBIrd: A Complete Standard Cell Layout System 276
D. Braun, C. Sechen, A. Sangiovanni-Vlncentelli, Univ. of California, Berkley, CA
fManuscript unavailable for publication.
CONTENTS
TUESDAY MORNING Lilac Ballroom North Convention Center PAGE
10:00 Automatic Layout of Channelless Gate Array 281C. P. Hsu, R. A, Perry, S. Evans, J. Tang, J. Y. Liu, Hughes Aircraft Co., Newport Beach, CA
10:25 A Hierarchical Routing System for VLSI Including Large Macros 285T. Hiwatashi, M. Yamada, T. Mitsuhashi, Toshiba Corp., Kawasaki, Japan
10:50 A Mixed Knowledge-Based/Algorithmic Approach to Custom Integrated Circuit Floorplanning 289M. A. Jabri, D. J. Skellerm, Univ. of Sydney, New South Wales, Australia
11:15 DIM-REL: Performance Biased Placement Program for Custom IC Layout 293
E. Berkcan, E. Kinnen, Univ. of Rochester, Rochester, NY
11:40 Late Paper 297
Grldless Channel Routing and Compaction for Cell-Based 30 Custom IC LayoutH. Rabbie, J. Jacobsson, Daisy System Corp., Mountain View, CA
TUESDAY MORNING 101 Meeting Rooms Convention Center PAGE
FAULT GRADING & DETECTION 301
Chairman: Donald A. Soderman
Co-Chairman: Michael Moon
9:10 A Comprehensive Testchlp and Data Analysis Software for Technology Development and Process Control in a 302
Custom VLSI Manufacturing Environment
C-M Liu*, A. V. Kordesh*, P. Y. Chee**, l-S Liu*, M. Khambaty*, International Microelectronic Products, San Jose,CA*, Cleveland State Univ., Cleveland, OH**
9:35 A Fault-Isolation Test (FIT) Chip 307
D. J. Azaren, A. M. Miscione, J. B. Cho, TRW Microelectronics Center, Redondo Beach, CA
10:00 On-Chlp Testing for 30K-Gate MasterslIce 311
S. Sato*, H. Takahashi*, Y. Machida*, G. Goto*, T. Nakamura*, T. Shirato**, Fujitsu Laboratories Ltd., Atsugi, Japan*,Fujitsu Ltd., Atsugi, Japan**
10:25 HC20000: A Fast 20K Gate Array with Built-in Self Test and System Fault Isolation Capabilities 315
D. Bondurant, D. Baran, Honeywell, Inc., Colorado Springs, CO
10:50 Fast Fault Grading of Sequential Logic 319
F. Brglez*, K. Kozminski**, Microelectronics Center of North Carolina, Research Triangle Park, NC*, Duke Univ.,Durham, NC**
11:15 Transistor Level Fault Simulation Using Probabilistic TechniquesJ. Hallauer, R. D. Hess, Caedent Corp., Colorado Springs, CO
325
CONTENTS
TUESDAY AFTERNOON Holiday Inn (ABCD) Holiday Inn PAGE
MODULE GENERATORS 329
Chairman: Jake Buurma
Co-Chairman: Allan Goodman
2:00 Parameterized Modules in Standard Cell Workstation Libraries 330H. C. Benz, General Electric Corp., Research Triangle Park, NC
2:25 CMOS RAM, ROM and PLA Generators for ASIC Applications 334W. P. Swartz*. H. Khan**, D. A. Thomas***, C. R. Giuffre*, M. deWit*, T. Pavey**, C. Mcintosh**, W. H. Banzhaf*,Texas Instruments, Inc., Dallas, TX*, Texas Instruments Ltd., Bedford, England**, Texas Instruments, Inc., Houston,-j-y***
2:50 A Full-Automated VLSI Layout System Including the Custom Cell Compiler 339
K. Kawauchi, Y. Hatano, J. Ishii, S. Sum!, Fujitsu Ltd., Kawasaki, Japan
3:15 A Multiplier-Accumulator Silicon Compiler tD. Gluss, A. ElGamal, J. Greene, P-H Ang, LSI Logic Corp., Palo Alto, CA
3:40 Compilation Approach for Standard Cell Libraries 343
S. Dholakia, S. Bush, A. Martinez, B. Walker, C. Asato, VLSI Technology, Inc., San Jose, CA
4:05 Construction and Compaction of Multi-level Logic Arrays 347M. Hofmann, IBM Corp., Yorktown Heights, NY
4:30 Multiple PLA Folding by the Method of Simulated Annealing 351D. F, Wong, H. W. Leong, C. L. Liu, Univ. of Illinois, Urbana, IL
4:55 A Spatial Reasoning Approach to Cell Layout Generation 356M. Alexander, Gould AMI Semiconductors, Santa Clara, CA
TUESDAY AFTERNOON Mini Ballroom (EFG) Holiday Inn PAGE
ANALOG CIRCUIT TECHNIQUES 361
Chairman: David WayneCo-Chairman: Jagdish Tandon
2:00 A Low-Voltage High-Resolution CMOS A/D Converter with Analog Compensation 362J. Robert*, G. C. Temes**, F. Krummenacher*, V. Valencic*, P. Deval*, Ecole Polytechnlque Federate, Lausanne,
Switzerland*, Univ. of California, Los Angeles, CA**
fManuscript unavailable for publication.
CONTENTS
TUESDAY AFTERNOON Mini Ballroom (EFG) Holiday Inn PAGE
2:25 3 States Logic Controlled CMOS Cyclic A/D Converter
K. Gotoh, 0. Kobayashi, Fujitsu Ltd., Kawasaki, Japan
366
2:50 A 400MHz 8-Bit Bipolar Video DAC
D. Sebilie, J. Bondoc, N. Bhandari, G. Polhemus, H. Hingarh, Fairchild Research Center, Palo Alto, CA
370
3:15 A Micropower 4th Order Ellipitical Switched-Capacitor Low-Pass FilterK. Halonen, M. Steyaet, W. Sanson, Katholieke Univ. Leuven, Haverlee, Belgium
374
3:40 CMOS Triode Transconductor Continuous Time Filters
J. L. Pennock, P. J. Frith, R. G. Barker, Wolfson Microelectronics Ltd., Edinburgh, Scotland
378
4:05 Analog Signal Process for Cellular Radio ApplicationsF. Miro*, M. Berthin*, G. Muter*, M. El Banna**, C. Groves**, Aptek Micro-systems, Deerfield Beach, FL*, NovatelCommunications, Ltd., Calgary, Alberta, Canada**
382
4:30 Standard Analog Cell Design for Electrical Energy Management IC
G, Shenton, IMP, San Jose, CA386
4:55 A High Performance Custom Standard Cell CMOS Equalizer for Telecommunications ApplicationsC. Rahim*, C. Laber*, B. Pickett*, F. Baechtold**, Micro Linear Corp., San Jose, CA*, Transcom Electronics,
Portsmouth, Rl**
391
TUESDAY AFTERNOON Lilac Ballroom North Convention Center PAGE
TESTING AND RELIABILITY
Chairman: Stephen R. QuigleyCo-Chairman: Michael I. H. King
2:00 INVITED
Surface Mount Technology and Reliability for VLSI PackagesR. N. McLellan, W. H. Schroen, Texas Instruments, Inc., Dallas, TX
2:25 MOS Scaling Effects on ESD-Based Failures
P. S. Neelakantaswamy*, I. R. Turkman**, RIT Research Corp., Rochester, NY*, RIT, Rochester, NY**
2:50 An Efficient Statistical Procedure to Determine Guardbands for Parametric Testing of Integrated Circuits
J. G. Noguera, D. T. Amm, Northern Telecom Electronics, Ltd., Ottawa, Ontario, Canada
395
396
400
404
CONTENTS
TUESDAY AFTERNOON Lilac Ballroom North Convention Center PAGE
3:15 Simulation and Testing VTI of Gate Arrays 409
S. Kazmi, K. VanEgmond, VLSI Technology, inc., San Jose, CA
3:40 Advanced Testing Techniques for Structured ASIC Products 412
R. Rasmussen, Y. Chang, F. White, LSI Logic Corp., Milpitas, CA
4:05 Genesfl Silicon Compilation and Design for Testability 416
D. Sabo, D. Johannsen, R. Yau, Silicon Compilers, Inc., San Jose, CA
4:30 Design of CMOS VLSI Circuits for Testability 421
D, L. Liu, E. J. McCluskey, Stanford Univ., Stanford, CA
TUESDAY AFTERNOON 101 Meeting Rooms Convention Center PAGE
CUSTOM DIGITAL APPLICATIONS 425
Chairman: T. H. Lee
Co-Chairman: Lynn Fuller
2:00 A Local-Area Network VLSI Chip Set 426
K. Smith*, R, Morrell*, P. Hofhlne*, A. Soria*, D. Broadhead", M. Whitaker*, M. Huth**, Gould AMI Semiconductors,
Santa Clara, CA*, Concord Data Systems, Inc., Phoenix, AZ**
x2:25 Software Controlled Extended Frame Format PCM Transceiver Chip 431
V. Venditti, S. Opalski, B. Stemmler, Bell-Northern Research, Ottawa, Ontario, Canada
2:50 A 1 MBIT/SEC CMOS Data Separator and Write Precompensatlon Circuit for Floppy Disk Drives 435
S. Mehrotra, C. C. Austin, J. T. Kellis, Silicon Systems, Inc., Tustin, CA
3:15 A Fast Asynchronous RSA Encryption Chip 439
G. Orton, L, E. Peppard, S. E. Tavares, Queen's Univ., Kingston, Ontario, Canada
3:40 Multiplication-Unit for Adder-Based Signal Processors using a Modified 2nd Order Booth Algorithm 443
A, Stoelzle, Siermens A.G., Munich, West Germany
4:05 On the Synchronization of a Microprocessor 447
H. H. Chao, S, Ong, J. Y. Tang, F. Shin, IBM Corp., Yorktown Heights, NY
CONTENTS
TUESDAY EVENING 101 Meeting Rooms Convention Center PAGE
8:00 EVENING PANEL451
Hardware Accelerators—Life In the Fast Lane
MODERATOR:
Jake Buurma
GE Semiconductor
TUESDAY EVENING Lilac Ballroom North Convention Center PAGE
8:00 EVENING PANEL 452
Digital Signal Processing Alternatives
MODERATOR:
Tom Foxall
Pacific Microcircuits Ltd.
TUESDAY EVENING Holiday Hall (ABCD) Holiday Inn PAGE
8:00 EVENING PANEL 453
ASIC: Where Are We, Where Are We Going, and How Do We Get There?
MODERATOR:
Michael Moon
Intel Corp.
TUESDAY EVENING Mini Ballroom (EFG) Holiday Inn PAGE
8:00 EVENING PANEL 454
Breadboardlng vs. Logic Simulation
MODERATOR:
Gregory W. Ledenbach
Intel Corporation
CONTENTS
WEDNESDAY MORNING Holiday Hall (ABCD) Holiday Inn PAGE
CAD FOR CIRCUITS AND SYSTEMS 455
Chairman: Hoda S. Abdel-Aty-ZohdyCo-Chairman: Miguel A. Martinez
8:50 TUTORIAL tDesign Centering—The Key to Competitive Products
K. Singhal, Univ. of Waterlow, Waterloo, Ont, Canada
9:35 NEWTON: Logic Simulation with Circuit Simulation Accuracy for ASIC Design 456
A. G, Patel, W. Bridgewater, R. P. Pokala, National Semiconductor Corp., Santa Clara, CA
10:00 An Engineers Design Tool for the Design and Development of High Performance Total System Arrays 460F. R. Ramsay, Ferranti Electronics Ltd., Oldham, England
10:25 Fault Models for the NMOS Programmable Logic Array 467W. Maly, Carnegie-Mellon Univ., Pittsburgh, PA
10:50 Modeling Delay as a Function of Cell Size In a Wafer Scale System 471
T. L. Michalka, J. D. Meindl, Stanford University, Stanford, CA
11:15 Interconnect Propagation Delay Characterization 475
R. Laubhan, C. Stanchak, C. Kendall, NCR Microelectronics, Colorado Springs, CO
WEDNESDAY MORNING Mini Ballroom (EFG) Holiday Inn PAGE
PAPERS OF GENERAL INTEREST 481
Chairman: Lynn Fuller
Co-Chairman: Dick Bryant
8:50 TUTORIAL 482
IC Design: Legal Protection, Pitfalls and Safe Harbors
A. C, Johnson, Jr., W. Y. Conwell, Klarquist, Sparkman, Campbell, Leigh & Whinston, Portland, OR
9:35 A Model of Design Schedules for Application Specific ICs 490C. F. Fey, D. Paraskevopoulos, Xerox Corp., El Segundo, CA
10:00 Status of EDIF fM. Waters (EDIF Steering Committee Member), Motorola, Phoenix, AZ
tManuscript unavailable for publication.
CONTENTS
WEDNESDAY MORNING Lilac Ballroom North Convention Center PAGE
GaAs INTEGRATED CIRCUITS 497
Chairman: Raymond A. Milano
Co-Chairman: David Wayne
9:10 INVITED 498
Reliability and Yield Assessment of Digital GaAs Integrated Circuits
T. Reeder, A. Fraser, B. Roesch, T. Wilson, D. Ogbonnah, B. Crispin, TriQuint Semiconductor Inc., Beaverton, OR
9:35 Noise Margin Analysis of GaAs MESFET and HEMT Digital Logic Families tT. Gheewala, J. Jorgenson, Sperry Corp., St. Paul, MN
10:00 A GaAs Counter Family Designed Using Standard Cells 504
D. C. Larson*, G. S. LaRue**, G. D. McCormack*, TriQuint Semiconductor, Beaverton, OR*, GAIN Electronics Corp.,Somerville, NJ**
10:25 An ECL Compatible GaAs 504 4-lnput Nor Gate Array 508
D. P. Laude, Ford Microelectronics, Inc., Colorado Springs, CO
10:50 GaAs Gate Array Designs Using the Capacitor Diode FET Logic (CDFL) Approach 513
F. S. Lee, R. C. Eden, S. Yinger, J. Chow, GigaBit Logic, Newbury Park, CA
11:15 The Design and Performance of GaAs 2K Gate Array 517
A. Peczalski*. G. Lee*, W. Betten*, H. SomaP, T. Vu*, S. Hanka**, R. Novak**, G. Y. Lee**, B. Gilbert***, B.
Naused***, S. Karwoski***, Honeywell, Minneapolis, MN*, Honeywell, Bloomington, MN**, Mayo Foundation,
Rochester, MN***
11:40 GaAs CCDs for Analog Signal Processing ICs 521
R. Sahal, B. Hill, B. Mathur, S, Pittman, J. A. Higgins, Rockwell International, Thousand Oaks, CA
WEDNESDAY MORNING 101 Meeting Rooms Convention Center PAGE
SYMBOLIC AND PROCEDURAL DESIGN APPROACHES 529
Chairman: Alberto Sangiovanni-VincentelliCo-Chalrman: Ron Jerdonek
9:10 Systematic Construction of Symbolic Technology Files for Process/Foundry Independence 530
R. P. Larsen, Rockwell International Corp., Newport Beach, CA
9:35 SPARCS: A New Constraint-Based IC Symbolic Layout Spacer 534
J, L. Burns, A. R. Newton, Univ. of California, Berkeley, CA
tManuscript unavailable for publication.
CONTENTS
WEDNESDAY MORNING 101 Meeting Rooms Convention Center PAGE
10:00 Graphic Editor for Parametric Cells Design 540
R. Manione, G. P. Costantino, CSELT, Torino, Italy
10:25 SKILL—An Interactive Procedural Design Environment 544
G. Wood, H-F. S. Law, SDA Systems, Santa Clara, CA
10:50 Silicon Compilation of a Core Microprocessor 548
T. K. Ng, M S. Kaplan, Silicon Design Labs. Inc., Liberty Corner, NJ
11:15 A Silicon Compiler for Successive Approximation A/D and D/A Converters 552
P. E. Allen, P. R. Barton, Georgia Institute of Technology, Atlanta, GA
WEDNESDAY AFTERNOON Holiday Hall (ABCD) Holiday Inn PAGE
GATE ARRAYS 557
Chairman: Daniel F. DalyCo-Chairman: Donald A. Soderman
1:45 An HVIC Gate Array 558
D. Regenold, GE Semiconductor, Research Triangle Park, NC
2:10 A High Performance 6000 Gate BIMOS Logic Array 562
P. T. Hickman, F. Ormerod, D. W. Schucker, Motorola, Inc., Mesa, AZ
2:35 Configurable 6845 MegaCell Incorporated with 2i*.m CMOS Gate Array 565
K. Pierce, S. Nance, D. Vo, K. Banerjee, M. H. Yang, VLSI Technology, Inc., San Jose, CA
3:00 A High Performance 129K Gate CMOS Array 568
T. Wong*, A. Hui*, D. Wong*, T. Kobayashi**, H. Suzuki**, K. Yamasaki**, LSI Logic Corp., Milpitas, CA*, Toshiba
Corp., Kawasaki, Japan**
3:25 A 540K-Translstor CMOS Variable Track Mastersllce 572
Y. Kuramitsu, K. Sato, Y. Akasaka, I. Ohkura, Mitsubishi Electric Corp., Itami, Japan
3:50 A 100ps ECL Array with 1 GHz I/O Buffer 576
M. Ohuchi, G. Uemura, J. Takayama, K, Mizushima, T. Matuba, NEC Corp., Kawasaki, Japan
4:15 A 50 ps 7K-Gate Mastersllce Using Mixed-Cells Consisting of an NTL Gate and LCML Macrocell 580
H. Ichino, M. Suzuki, S. Konaka, E. Yamamoto, NTT Electrical Communications Labs, Kanagawa, Japan
CONTENTS
WEDNESDAY AFTERNOON Lilac Ballroom North Convention Center PAGE
ADVANCED PROCESSING TECHNIQUES 585
Chairman:J. S. T. HuangCo-Chairman: Thomas M. Kelly
1:45 INVITED 586
In-Situ Processing of Semiconductor Devices and Custom Integrated Circuits
A. J. Steckl, S. P. Murarka, J. C. Corelli, Rensselaer Polytechnic institute, Troy, NY
2:10 Focused Ion Beam Microsurgery for Integrated Circuit Customization or Repair 591
C. R. Musil*, J. L, Bartelt*, J. Melngailis**, Hughes Research Labs, Malibu, CA*, MIT, Cambridge, MA**
2:35 Application of the Focused Ion Beam (FIB) for Repair of Wafer Scale Interconnections 594
R. Rajapkse, H. Lin, J. F. McDonald, Rensselaer Polytechnic Institute, Troy, NY
3:00 Submicron Structures In a Single Layer of Proximity Corrected Electron Beam Resist 632
M. E. Haslam, J. F. McDonald, Rensselaer Polytechnic Institute, Troy, NY
3:25 A New Approach to Improving Wafer Fabrication Turnaround for Custom ICs 599
J. A. Schoeffel, A. L Goodman, ATEQ Corp., Beaverton, OR
3:50 An Algorithm for Characterization of Parameter Variation of Wafers 601
W. A. Miller, C. N. Anagnostopoulos, J. R. Fischer, Eastman Kodak Co., Rochester, NY
WEDNESDAY AFTERNOON 101 Meeting Rooms Convention Center PAGE
CIRCUIT ANALYSIS AND SIMULATION 607
Chairman: Jonathan Allen
Co-Chairman: Terry Sideris
1:25 TUTORIAL 608
Computer Aided Design of Analog Integrated Circuits
P. E. Allen, Georgia Institute of Technology, Atlanta, GA
2:10 QCritlc: A Rule-Based Analyzer for Bipolar Analog Circuit Designs 617
S. Bergquist*, R. Sparkes**, Oregon State Univ.*, Tektronix, Inc., Beaverton, OR**
2:35 Fast and Accurate Table Look-Up MOSFET Model for Circuit Simulation 621
D. Divekar, D. Ryan, J. Chan, J. Deustch, Shiva Multisystems Corp., Menlo Park, CA
3:00 General-Purpose Model Parameter Extraction Program with Initial Value Exploration Technique 624
M. Suglmoto, NEC Corp., Kawasaki, Japan
3:25 GASSIM: A Circuit Simulator for Large Scale GaAs Circuits 628
W. R. McKinley, Ford Microelectronics, Inc., Colorado Springs, CO