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University of Toronto Faculty of Applied Science and Engineering

Final Examination - April 30, 2019

ECE342S - Computer Hardware

Examiner - Prof. Natalie Enright Jerger

There are 6 questions and 14 pages. Do all questions. The total number of marks is 71. The duration of the test is 150 minutes.

ALL WORK IS TO BE DONE ON THESE SHEETS! Use the back of the pages if you need more space. Be sure to indicate clearly if your work continues elsewhere.

Please put your final solution in the box if one is provided.

Clear and concise answers will be considered more favourably than ones that ramble. Do not fill space just because it exists!

You are permitted any printed or written materials you wish.

You may use a faculty-approved non-programmable calculator.

Always give some explanations or reasoning for how you arrived at your solutions to help the marker understand your thinking.

State your assumptions. Show your work. Use your time wisely as not all questions will require the same amount of time. If you think that assumptions must be made to answer a question, state them clearly. If there are multiple possibilities, comment that there are, explain why and then provide at least one possible answer and state the corresponding assumptions.

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This page is for grading purposes only. The marks breakdown is given for each question.

1 [8]

2 [8]

3 [12]

4 [13]

5 [14]

6 [1.6]

Total [71]

Fj

1. Memory Mapped I/O

In this question, you must design the bus arbitration logic for a system with a 16-bit CPU, which connects peripherals via a 16-bit bus and uses a 2-byte addressable memory.

Address Size Starting Address Memory 8K bytes Ox0000 UART 4 x 1-byte registers Ox1000 Timer 2 x 2-byte registers 0x2000 LED 1 x 1-byte register 0x4000

[2 marks] (a) What is the maximum address value for the memory peripheral?

[2 marks] (b) In the table below, indicate the chip select logic that is needed to arbitrate bus access for all these peripherals? Your address signals are given as A[15 : 0] to answer this question.

I I Chip select signal I

UART

Timer

LED

[2 marks] (c) List only the peripherals which will need byte-enable signals to access all their registers.

[2 marks] (d) You must now add a new peripheral which starts at address 0x8000 and has 4 x 1-byte registers W X, Y and Z. Register W is at address 0x8000 and register X is at address 0x8001. Write the byte enable signals needed to access these registers.

Byte enable for W = Byte enable for X =

Byte enable for Y = Byte enable for Z =

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2. Testing

Consider the following circuit:

i;i

C

[2 marks] (a) It is not possible to test a stuck-at-0 fault on the output of G3. Explain why this is case.

[4 marks] (b) Redesign and redraw the circuit such that you can test a stuck-at-0 fault on the output of G3. You are allowed to add additional inputs. When not testing for a stuck-at-zero fault on the output of G3, the circuit should produce the same output as the original one.

[2 marks] (c) Give one test vector for the new circuit that will test for a stuck-at-0 fault on the output of G3.

3. Asynchronous Sequential Circuits I

[12 marks] Complete the flow table below for the following circuit. Note the flow table may have more rows and columns than your solution requires.

Wi

w2

zi

z2

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4. Asynchronous Sequential Circuits II

Transition diagrams. Consider the following flow table: Present state

Next State w2wl = 00 01 10 11

Output z

A B C - 0

B D® - G 0

C F - G 0

D D E C - 1

E A® - G 0 F ® E C - 0

G - B C (j 1

[4 marks] (a) Fill in the relabled flow table:

Present state

Next State w2wl = 00 01 10 11

Output z

A 0

B 0

C 0

D 1

E 0

F 0

G 1

[9 marks] (b) Given the following state assignment: A = 000, B = 001, C = 010, D = 011, E = 100, F = 101 and G = 110, annotate the cube below with all the mandatory and optional paths of the above relabeled flow table. Only a subset of edges are given; you may need to add additional edges to show all mandatory and optional paths.

A

The following is provided as a spare. If you use both, please clearly indicate which one you would like marked.

5. Datapath

In this question, you must design the datapath for a polynomial function shown in the equation below.

sinx= 16x(ir—x)

-

— 4x (7,- - x)

You may use any of the elements listed in the figure below.

Element Mux Subtractor N-bit shifter Multiplier Divider FE (t & tc(,) Constant

Delay (ns) 0 5 0 15 30 1 0

NOTE: For constants, please indicate the exact value of the constant in the box.

[6 marks] (a) Draw the non-pipelined datapath for this algorithm using the skeleton figure provided.

The following is provided as a spare. If you use both, please clearly indicate which one you would like marked.

H1.

[2 marks] (b) What is the maximum clock frequency of your non-pipelined design?

Frequency =

[4 marks] (c) Draw the pipelined datapath for this algorithm that achieves the maximum possible clock fre- quency using the skeleton figure provided.

The following is provided as a spare. If you use both, please clearly indicate which one you would like marked.

[2 marks] (d) What is the maximum clock frequency of your pipelined design?

Frequency =

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6. Verilog design

In this question. von will design hardware for t ile siginoid operat i ni. The equation for a Opnoid is

given below.

Ie'

clk

CIOCN

.. ..

re e I

reset SigmOIC ova(id

I number

i_n

t oresuit valid

S8.8

tiFcu =krlranu ovalid

(hi Timici IL Finn

Figure 1: I/O and timing specifications for signioicl circuit.

Dtign Specificatiotin:

The input is provided in S8.8 hxed-pnint foruiat. Flie output must be in the same format.

Ln unJcr is only valid when htalid is 1. At all other times the t_t'alid signal is held at S.

Once von finish your computation. the reHilt sliouihl he output ill O_tiaUlt. along with u_iifid

bcmg set to 1

You are allowed to use inbuilt verilog operations (e.g.. \\ for tlivisioii).

Pipeline your design to use 1 stages where each stage does one of the required mathematical

I ) cr at i0115.

You have a module avnAdde to calculate the exponential Function. TI us funct 1011 is inpleiiieiited using

purely coinhi lation luiic. The innnber accepts an S&S number as input and outputs the result as an

Sno number.

module exp(input [16:01 number, output [16:01 result);

HINT: Keep in mind t hat ant hniet ic opera I ins using fixed point numbers cause the deimual point

o he shifted. You must account for this in voin design to get the correct result.

'The siginoid operation is a couinionli red act ivat ion hitiction in neural networks.

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[4 marks] (a) Complete the figure below to implement the pipelined datapath for your design.

i_number o_result

The following is provided as a spare. If you use both, please clearly indicate which one you would like marked.

i_number

[4 marks] (b) Draw the control FSM for your design.

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[8 marks] (c) Complete the starter verilog code provided below to implement your design.

module signioid

input clock input reset

input i..valid

input [16:0] i_number,

output ovalid

output [16:0] o_result

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