z/Architecture IBM

Principles of Operation

SA22-7832-00

z/Architecture IBM

Principles of Operation

SA22-7832-00

Note:

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First Edition (December 2000)

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Contents

Notices . . . . . . . . . . . . . . . . . . . . . . . xvTrademarks . . . . . . . . . . . . . . . . . . . . xv

Preface . . . . . . . . . . . . . . . . . . . . . . xviiSize and Number Notation . . . . . . . . . xviiiBytes, Characters, and Codes . . . . . . . . xixOther Publications . . . . . . . . . . . . . . . xix

Chapter 1. Introduction . . . . . . . . . . . 1-1Highlights of z/Architecture . . . . . . . . . . . 1-1

General Instructions for 64-Bit Integers . . 1-2Other New General Instructions . . . . . . 1-2Floating-Point Instructions . . . . . . . . . . 1-4Control Instructions . . . . . . . . . . . . . 1-4Trimodal Addressing . . . . . . . . . . . . . 1-4

Modal Instructions . . . . . . . . . . . . . 1-4Effects on Bits 0-31 of a General

Register . . . . . . . . . . . . . . . . . 1-5Extended-Translation Facility 2 . . . . . . . 1-5

The ESA/390 Base . . . . . . . . . . . . . . . 1-6The ESA/370 and 370-XA Base . . . . . . 1-11

System Program . . . . . . . . . . . . . . . . . 1-13Compatibility . . . . . . . . . . . . . . . . . . . 1-13

Compatibility among z/ArchitectureSystems . . . . . . . . . . . . . . . . . . 1-13

Compatibility between z/Architecture andESA/390 . . . . . . . . . . . . . . . . . 1-14

Control-Program Compatibility . . . . . . 1-14Problem-State Compatibility . . . . . . . 1-14

Availability . . . . . . . . . . . . . . . . . . . . 1-14

Chapter 2. Organization . . . . . . . . . . . 2-1Main Storage . . . . . . . . . . . . . . . . . . . 2-2Expanded Storage . . . . . . . . . . . . . . . 2-2CPU . . . . . . . . . . . . . . . . . . . . . . . . 2-2

PSW . . . . . . . . . . . . . . . . . . . . . . 2-3General Registers . . . . . . . . . . . . . . 2-3Floating-Point Registers . . . . . . . . . . . 2-3Floating-Point-Control Register . . . . . . . 2-4Control Registers . . . . . . . . . . . . . . . 2-4Access Registers . . . . . . . . . . . . . . . 2-4Cryptographic Facility . . . . . . . . . . . . 2-6

External Time Reference . . . . . . . . . . . . 2-6I/O . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Channel Subsystem . . . . . . . . . . . . . 2-6Channel Paths . . . . . . . . . . . . . . . . 2-6I/O Devices and Control Units . . . . . . . 2-7

Operator Facilities . . . . . . . . . . . . . . . . 2-7

Chapter 3. Storage . . . . . . . . . . . . . . 3-1

Storage Addressing . . . . . . . . . . . . . . . 3-2Information Formats . . . . . . . . . . . . . 3-2Integral Boundaries . . . . . . . . . . . . . 3-3

Address Types and Formats . . . . . . . . . . 3-3Address Types . . . . . . . . . . . . . . . . 3-3

Absolute Address . . . . . . . . . . . . . 3-3Real Address . . . . . . . . . . . . . . . 3-4Virtual Address . . . . . . . . . . . . . . 3-4Primary Virtual Address . . . . . . . . . 3-4Secondary Virtual Address . . . . . . . . 3-4AR-Specified Virtual Address . . . . . . 3-5Home Virtual Address . . . . . . . . . . 3-5Logical Address . . . . . . . . . . . . . . 3-5Instruction Address . . . . . . . . . . . . 3-5Effective Address . . . . . . . . . . . . . 3-5

Address Size and Wraparound . . . . . . . 3-5Address Wraparound . . . . . . . . . . . 3-6

Storage Key . . . . . . . . . . . . . . . . . . . 3-8Protection . . . . . . . . . . . . . . . . . . . . . 3-9

Key-Controlled Protection . . . . . . . . . . 3-9Storage-Protection-Override Control . . 3-10Fetch-Protection-Override Control . . . 3-11

Access-List-Controlled Protection . . . . . 3-11Page Protection . . . . . . . . . . . . . . . 3-11Low-Address Protection . . . . . . . . . . . 3-12Suppression on Protection . . . . . . . . . 3-12

Reference Recording . . . . . . . . . . . . . . 3-14Change Recording . . . . . . . . . . . . . . . 3-14Prefixing . . . . . . . . . . . . . . . . . . . . . 3-15Address Spaces . . . . . . . . . . . . . . . . . 3-16

Changing to Different Address Spaces . 3-17Address-Space Number . . . . . . . . . 3-17

ASN Translation . . . . . . . . . . . . . . . . . 3-18ASN-Translation Controls . . . . . . . . . . 3-18

Control Register 14 . . . . . . . . . . . . 3-18ASN-Translation Tables . . . . . . . . . . . 3-19

ASN-First-Table Entries . . . . . . . . . 3-19ASN-Second-Table Entries . . . . . . . 3-19

ASN-Translation Process . . . . . . . . . . 3-21ASN-First-Table Lookup . . . . . . . . . 3-22ASN-Second-Table Lookup . . . . . . . 3-23Recognition of Exceptions during ASN

Translation . . . . . . . . . . . . . . . 3-23ASN Authorization . . . . . . . . . . . . . . . . 3-23

ASN-Authorization Controls . . . . . . . . . 3-23Control Register 4 . . . . . . . . . . . . . 3-23ASN-Second-Table Entry . . . . . . . . 3-24

Authority-Table Entries . . . . . . . . . . . 3-24ASN-Authorization Process . . . . . . . . . 3-24

Authority-Table Lookup . . . . . . . . . . 3-25

Copyright IBM Corp. 1990, 2000 iii

Recognition of Exceptions during ASNAuthorization . . . . . . . . . . . . . 3-26

Dynamic Address Translation . . . . . . . . . 3-26Translation Control . . . . . . . . . . . . . . 3-28

Translation Modes . . . . . . . . . . . . 3-28Control Register 0 . . . . . . . . . . . . . 3-29Control Register 1 . . . . . . . . . . . . . 3-29Control Register 7 . . . . . . . . . . . . . 3-30Control Register 13 . . . . . . . . . . . . 3-31

Translation Tables . . . . . . . . . . . . . . 3-31Region-Table Entries . . . . . . . . . . . 3-31Segment-Table Entries . . . . . . . . . . 3-33Page-Table Entries . . . . . . . . . . . . 3-33

Translation Process . . . . . . . . . . . . . 3-34Inspection of Real-Space Control . . . . 3-39Inspection of Designation-Type Control 3-39Lookup in a Table Designated by an

Address-Space-Control Element . . 3-39Lookup in a Table Designated by a

Region-Table Entry . . . . . . . . . . 3-40Page-Table Lookup . . . . . . . . . . . . 3-42Formation of the Real Address . . . . . 3-42Recognition of Exceptions during

Translation . . . . . . . . . . . . . . . 3-42Translation-Lookaside Buffer . . . . . . . . 3-42

TLB Structure . . . . . . . . . . . . . . . 3-43Formation of TLB Entries . . . . . . . . 3-43Use of TLB Entries . . . . . . . . . . . . 3-44Modification of Translation Tables . . . 3-45

Address Summary . . . . . . . . . . . . . . . . 3-47Addresses Translated . . . . . . . . . . . . 3-47Handling of Addresses . . . . . . . . . . . 3-48

Assigned Storage Locations . . . . . . . . . . 3-51

Chapter 4. Control . . . . . . . . . . . . . . 4-1Stopped, Operating, Load, and Check-Stop

States . . . . . . . . . . . . . . . . . . . . . . 4-1Stopped State . . . . . . . . . . . . . . . . 4-2Operating State . . . . . . . . . . . . . . . . 4-2Load State . . . . . . . . . . . . . . . . . . 4-2Check-Stop State . . . . . . . . . . . . . . 4-3

Program-Status Word . . . . . . . . . . . . . . 4-3Program-Status-Word Format . . . . . . . 4-5

Control Registers . . . . . . . . . . . . . . . . 4-7Tracing . . . . . . . . . . . . . . . . . . . . . . 4-10

Control-Register Allocation . . . . . . . . . 4-13Trace Entries . . . . . . . . . . . . . . . . . 4-13Operation . . . . . . . . . . . . . . . . . . . 4-23

Program-Event Recording . . . . . . . . . . . 4-24Control-Register Allocation and

Address-Space-Control Element . . . . 4-24Operation . . . . . . . . . . . . . . . . . . . 4-25

Identification of Cause . . . . . . . . . . 4-26Priority of Indication . . . . . . . . . . . . 4-28

Storage-Area Designation . . . . . . . . . . 4-29PER Events . . . . . . . . . . . . . . . . . . 4-30

Successful Branching . . . . . . . . . . . 4-30Instruction Fetching . . . . . . . . . . . . 4-31Storage Alteration . . . . . . . . . . . . . 4-31Store Using Real Address . . . . . . . . 4-32

Indication of PER Events Concurrentlywith Other Interruption Conditions . . . 4-32

Timing . . . . . . . . . . . . . . . . . . . . . . . 4-34Time-of-Day Clock . . . . . . . . . . . . . . 4-35

Format . . . . . . . . . . . . . . . . . . . 4-35States . . . . . . . . . . . . . . . . . . . . 4-35Changes in Clock State . . . . . . . . . 4-36Setting and Inspecting the Clock . . . . 4-36TOD Programmable Register . . . . . . 4-37

TOD-Clock Synchronization . . . . . . . . . 4-39Clock Comparator . . . . . . . . . . . . . . 4-39CPU Timer . . . . . . . . . . . . . . . . . . 4-40

Externally Initiated Functions . . . . . . . . . 4-41Resets . . . . . . . . . . . . . . . . . . . . . 4-41

CPU Reset . . . . . . . . . . . . . . . . . 4-45Initial CPU Reset . . . . . . . . . . . . . 4-46Subsystem Reset . . . . . . . . . . . . . 4-46Clear Reset . . . . . . . . . . . . . . . . 4-46Power-On Reset . . . . . . . . . . . . . 4-47

Initial Program Loading . . . . . . . . . . . 4-47Store Status . . . . . . . . . . . . . . . . . . 4-48

Multiprocessing . . . . . . . . . . . . . . . . . 4-49Shared Main Storage . . . . . . . . . . . . 4-49CPU-Address Identification . . . . . . . . . 4-49

CPU Signaling and Response . . . . . . . . . 4-49Signal-Processor Orders . . . . . . . . . . 4-49Conditions Determining Response . . . . . 4-53

Conditions Precluding Interpretation ofthe Order Code . . . . . . . . . . . . 4-53

Status Bits . . . . . . . . . . . . . . . . . 4-54

Chapter 5. Program Execution . . . . . . . 5-1Instructions . . . . . . . . . . . . . . . . . . . . 5-2

Operands . . . . . . . . . . . . . . . . . . . 5-2Instruction Formats . . . . . . . . . . . . . . 5-3

Register Operands . . . . . . . . . . . . 5-6Immediate Operands . . . . . . . . . . . 5-6Storage Operands . . . . . . . . . . . . 5-6

Address Generation . . . . . . . . . . . . . . . 5-7Trimodal Addressing . . . . . . . . . . . . . 5-7Sequential Instruction-Address Generation . 5-7Operand-Address Generation . . . . . . . 5-7

Formation of the Intermediate Value . . 5-7Formation of the Operand Address . . . 5-8

Branch-Address Generation . . . . . . . . 5-8Formation of the Intermediate Value . . 5-8Formation of the Branch Address . . . . 5-9

Instruction Execution and Sequencing . . . . 5-9

iv z/Architecture Principles of Operation

Decision Making . . . . . . . . . . . . . . . 5-10Loop Control . . . . . . . . . . . . . . . . . 5-10Subroutine Linkage without the Linkage

Stack . . . . . . . . . . . . . . . . . . . 5-10Simple Branch Instructions . . . . . . . 5-10Other Linkage Instructions . . . . . . . . 5-14

Interruptions . . . . . . . . . . . . . . . . . . 5-19Types of Instruction Ending . . . . . . . . . 5-19

Completion . . . . . . . . . . . . . . . . . 5-19Suppression . . . . . . . . . . . . . . . . 5-19Nullification . . . . . . . . . . . . . . . . . 5-20Termination . . . . . . . . . . . . . . . . 5-20

Interruptible Instructions . . . . . . . . . . . 5-20Point of Interruption . . . . . . . . . . . . 5-20Unit of Operation . . . . . . . . . . . . . 5-20Execution of Interruptible Instructions . 5-20Condition-Code Alternative to

Interruptibility . . . . . . . . . . . . . 5-21Exceptions to Nullification and

Suppression . . . . . . . . . . . . . . . 5-22Storage Change and Restoration for

DAT-Associated Access Exceptions 5-22Modification of DAT-Table Entries . . . 5-23Trial Execution for Editing Instructions

and Translate Instruction . . . . . . 5-23Authorization Mechanisms . . . . . . . . . . . 5-23

Mode Requirements . . . . . . . . . . . 5-24Extraction-Authority Control . . . . . . . 5-24PSW-Key Mask . . . . . . . . . . . . . . 5-24Secondary-Space Control . . . . . . . . 5-25Subsystem-Linkage Control . . . . . . . 5-25ASN-Translation Control . . . . . . . . . 5-25Authorization Index . . . . . . . . . . . . 5-25

PC-Number Translation . . . . . . . . . . . . . 5-29PC-Number Translation Control . . . . . . 5-29

Control Register 5 . . . . . . . . . . . . . 5-29PC-Number Translation Tables . . . . . . . 5-29

Linkage-Table Entries . . . . . . . . . . 5-29Entry-Table Entries . . . . . . . . . . . . 5-30

PC-Number-Translation Process . . . . . . 5-31Obtaining the Linkage-Table

Designation . . . . . . . . . . . . . . 5-32Linkage-Table Lookup . . . . . . . . . . 5-33Entry-Table Lookup . . . . . . . . . . . . 5-33Recognition of Exceptions during

PC-Number Translation . . . . . . . 5-33Home Address Space . . . . . . . . . . . . . 5-34Access-Register Introduction . . . . . . . . . . 5-34

Summary . . . . . . . . . . . . . . . . . . . 5-35Access-Register Functions . . . . . . . . . 5-35

Access-Register-Specified AddressSpaces . . . . . . . . . . . . . . . . . 5-35

Access-Register Instructions . . . . . . 5-42Access-Register Translation . . . . . . . . . . 5-43

Access-Register-Translation Control . . . . 5-43Control Register 2 . . . . . . . . . . . . . 5-43Control Register 5 . . . . . . . . . . . . . 5-43Control Register 8 . . . . . . . . . . . . . 5-43

Access Registers . . . . . . . . . . . . . . . 5-44Access-Register-Translation Tables . . . . 5-44

Dispatchable-Unit Control Table andAccess-List Designations . . . . . . 5-45

Access-List Entries . . . . . . . . . . . . 5-46ASN-Second-Table Entries . . . . . . . 5-47

Access-Register-Translation Process . . . 5-48Selecting the Access-List-Entry Token . 5-51Obtaining the Primary or Secondary

Address-Space-Control Element . . 5-51Checking the First Byte of the ALET . . 5-51Obtaining the Effective Access-List

Designation . . . . . . . . . . . . . . 5-51Access-List Lookup . . . . . . . . . . . . 5-51Locating the ASN-Second-Table Entry . 5-52Authorizing the Use of the Access-List

Entry . . . . . . . . . . . . . . . . . . 5-52Checking for Access-List-Controlled

Protection . . . . . . . . . . . . . . . 5-53Obtaining the Address-Space-Control

Element from the ASN-Second-TableEntry . . . . . . . . . . . . . . . . . . 5-53

Recognition of Exceptions duringAccess-Register Translation . . . . 5-53

ART-Lookaside Buffer . . . . . . . . . . . . 5-53ALB Structure . . . . . . . . . . . . . . . 5-53Formation of ALB Entries . . . . . . . . 5-54Use of ALB Entries . . . . . . . . . . . . 5-54Modification of ART Tables . . . . . . . 5-55

Subspace Groups . . . . . . . . . . . . . . . . 5-55Subspace-Group Tables . . . . . . . . . . 5-55

Subspace-Group Dispatchable-UnitControl Table . . . . . . . . . . . . . 5-55

Subspace-Group ASN-Second-TableEntries . . . . . . . . . . . . . . . . . 5-57

Subspace-Replacement Operations . . . . 5-59Linkage-Stack Introduction . . . . . . . . . . . 5-60

Summary . . . . . . . . . . . . . . . . . . . 5-60Linkage-Stack Functions . . . . . . . . . . 5-60

Transferring Program Control . . . . . . 5-60Branching Using the Linkage Stack . . 5-62Adding and Retrieving Information . . . 5-63Testing Authorization . . . . . . . . . . . 5-63Program-Problem Analysis . . . . . . . . 5-64

Linkage-Stack Entry-Table Entries . . . . . . 5-64Linkage-Stack Operations . . . . . . . . . . . 5-65

Linkage-Stack-Operations Control . . . . . 5-67Control Register 15 . . . . . . . . . . . . 5-67

Linkage Stack . . . . . . . . . . . . . . . . . 5-67Entry Descriptors . . . . . . . . . . . . . 5-67

Contents v

Header Entries . . . . . . . . . . . . . . 5-69Trailer Entries . . . . . . . . . . . . . . . 5-69State Entries . . . . . . . . . . . . . . . . 5-70

Stacking Process . . . . . . . . . . . . . . . 5-72Locating Space for a New Entry . . . . 5-72Forming the New Entry . . . . . . . . . . 5-73Updating the Current Entry . . . . . . . 5-74Updating Control Register 15 . . . . . . 5-74Recognition of Exceptions during the

Stacking Process . . . . . . . . . . . 5-74Unstacking Process . . . . . . . . . . . . . 5-75

Locating the Current Entry andProcessing a Header Entry . . . . . 5-75

Checking for a State Entry . . . . . . . . 5-76Restoring Information . . . . . . . . . . . 5-76Updating the Preceding Entry . . . . . . 5-77Updating Control Register 15 . . . . . . 5-77Recognition of Exceptions during the

Unstacking Process . . . . . . . . . 5-77Sequence of Storage References . . . . . . . 5-77

Conceptual Sequence . . . . . . . . . . 5-77Overlapped Operation of Instruction

Execution . . . . . . . . . . . . . . . 5-78Divisible Instruction Execution . . . . . . 5-78

Interlocks for Virtual-Storage References . 5-79Interlocks between Instructions . . . . . 5-79Interlocks within a Single Instruction . . 5-80

Instruction Fetching . . . . . . . . . . . . . 5-81ART-Table and DAT-Table Fetches . . . . 5-83Storage-Key Accesses . . . . . . . . . . . 5-83Storage-Operand References . . . . . . . 5-84

Storage-Operand Fetch References . . 5-84Storage-Operand Store References . . 5-84Storage-Operand Update References . 5-85

Storage-Operand Consistency . . . . . . . 5-86Single-Access References . . . . . . . . 5-86Multiple-Access References . . . . . . . 5-86Block-Concurrent References . . . . . . 5-87Consistency Specification . . . . . . . . 5-87

Relation between Operand Accesses . . . 5-88Other Storage References . . . . . . . . . 5-89

Serialization . . . . . . . . . . . . . . . . . . . 5-89CPU Serialization . . . . . . . . . . . . . . 5-89Channel-Program Serialization . . . . . . . 5-91

Chapter 6. Interruptions . . . . . . . . . . . 6-1Interruption Action . . . . . . . . . . . . . . . . 6-2

Interruption Code . . . . . . . . . . . . . . . 6-5Enabling and Disabling . . . . . . . . . . . 6-6Handling of Floating Interruption Conditions 6-7Instruction-Length Code . . . . . . . . . . . 6-7

Zero ILC . . . . . . . . . . . . . . . . . . 6-7ILC on Instruction-Fetching Exceptions . 6-8

Exceptions Associated with the PSW . . . 6-9

Early Exception Recognition . . . . . . . 6-9Late Exception Recognition . . . . . . . 6-10

External Interruption . . . . . . . . . . . . . . . 6-10Clock Comparator . . . . . . . . . . . . . . 6-11CPU Timer . . . . . . . . . . . . . . . . . . 6-11Emergency Signal . . . . . . . . . . . . . . 6-11ETR . . . . . . . . . . . . . . . . . . . . . . 6-12External Call . . . . . . . . . . . . . . . . . 6-12Interrupt Key . . . . . . . . . . . . . . . . . 6-12Malfunction Alert . . . . . . . . . . . . . . . 6-12Service Signal . . . . . . . . . . . . . . . . 6-13

I/O Interruption . . . . . . . . . . . . . . . . . . 6-13Machine-Check Interruption . . . . . . . . . . 6-13Program Interruption . . . . . . . . . . . . . . 6-14

Data-Exception Code (DXC) . . . . . . . . 6-14Priority of Program Interruptions for

Data Exceptions . . . . . . . . . . . 6-16Program-Interruption Conditions . . . . . . 6-16

Addressing Exception . . . . . . . . . . 6-16AFX-Translation Exception . . . . . . . . 6-19ALEN-Translation Exception . . . . . . . 6-19ALE-Sequence Exception . . . . . . . . 6-19ALET-Specification Exception . . . . . . 6-19ASCE-Type Exception . . . . . . . . . . 6-19ASTE-Sequence Exception . . . . . . . 6-20ASTE-Validity Exception . . . . . . . . . 6-20ASX-Translation Exception . . . . . . . 6-21Crypto-Operation Exception . . . . . . . 6-21Data Exception . . . . . . . . . . . . . . 6-21Decimal-Divide Exception . . . . . . . . 6-22Decimal-Overflow Exception . . . . . . . 6-22Execute Exception . . . . . . . . . . . . 6-22EX-Translation Exception . . . . . . . . 6-22Extended-Authority Exception . . . . . . 6-22Fixed-Point-Divide Exception . . . . . . 6-23Fixed-Point-Overflow Exception . . . . . 6-23HFP-Divide Exception . . . . . . . . . . 6-23HFP-Exponent-Overflow Exception . . . 6-23HFP-Exponent-Underflow Exception . . 6-23HFP-Significance Exception . . . . . . . 6-24HFP-Square-Root Exception . . . . . . 6-24LX-Translation Exception . . . . . . . . 6-24Monitor Event . . . . . . . . . . . . . . . 6-24Operand Exception . . . . . . . . . . . . 6-25Operation Exception . . . . . . . . . . . 6-25Page-Translation Exception . . . . . . . 6-26PC-Translation-Specification Exception 6-26PER Event . . . . . . . . . . . . . . . . . 6-26Primary-Authority Exception . . . . . . . 6-26Privileged-Operation Exception . . . . . 6-27Protection Exception . . . . . . . . . . . 6-27Region-First-Translation Exception . . . 6-28Region-Second-Translation Exception . 6-29Region-Third-Translation Exception . . 6-29

vi z/Architecture Principles of Operation

Secondary-Authority Exception . . . . . 6-29Segment-Translation Exception . . . . . 6-30Space-Switch Event . . . . . . . . . . . 6-30Special-Operation Exception . . . . . . 6-31Specification Exception . . . . . . . . . . 6-32Stack-Empty Exception . . . . . . . . . . 6-33Stack-Full Exception . . . . . . . . . . . 6-34Stack-Operation Exception . . . . . . . . 6-34Stack-Specification Exception . . . . . . 6-34Stack-Type Exception . . . . . . . . . . 6-34Trace-Table Exception . . . . . . . . . . 6-34Translation-Specification Exception . . . 6-35

Collective Program-Interruption Names . . 6-35Recognition of Access Exceptions . . . . . 6-35Multiple Program-Interruption Conditions . 6-39

Access Exceptions . . . . . . . . . . . . 6-42ASN-Translation Exceptions . . . . . . . 6-45Subspace-Replacement Exceptions . . 6-46Trace Exceptions . . . . . . . . . . . . . 6-46

Restart Interruption . . . . . . . . . . . . . . . 6-46Supervisor-Call Interruption . . . . . . . . . . 6-47Priority of Interruptions . . . . . . . . . . . . . 6-47

Chapter 7. General Instructions . . . . . . 7-1Data Format . . . . . . . . . . . . . . . . . . . 7-2Binary-Integer Representation . . . . . . . . . 7-2Binary Arithmetic . . . . . . . . . . . . . . . . 7-3

Signed Binary Arithmetic . . . . . . . . . . 7-4Addition and Subtraction . . . . . . . . . 7-4Fixed-Point Overflow . . . . . . . . . . . 7-4

Unsigned Binary Arithmetic . . . . . . . . . 7-4Signed and Logical Comparison . . . . . . . . 7-5Instructions . . . . . . . . . . . . . . . . . . . . 7-6

ADD . . . . . . . . . . . . . . . . . . . . . . 7-16ADD HALFWORD . . . . . . . . . . . . . . 7-16ADD HALFWORD IMMEDIATE . . . . . . 7-16ADD LOGICAL . . . . . . . . . . . . . . . . 7-17ADD LOGICAL WITH CARRY . . . . . . . 7-17AND . . . . . . . . . . . . . . . . . . . . . . 7-18AND IMMEDIATE . . . . . . . . . . . . . . 7-19BRANCH AND LINK . . . . . . . . . . . . . 7-19BRANCH AND SAVE . . . . . . . . . . . . 7-20BRANCH AND SAVE AND SET MODE . 7-21BRANCH AND SET MODE . . . . . . . . . 7-22BRANCH ON CONDITION . . . . . . . . . 7-23BRANCH ON COUNT . . . . . . . . . . . . 7-24BRANCH ON INDEX HIGH . . . . . . . . . 7-24BRANCH ON INDEX LOW OR EQUAL . . 7-25BRANCH RELATIVE AND SAVE . . . . . 7-26BRANCH RELATIVE AND SAVE LONG . 7-26BRANCH RELATIVE ON CONDITION . . 7-26BRANCH RELATIVE ON CONDITION

LONG . . . . . . . . . . . . . . . . . . . 7-26BRANCH RELATIVE ON COUNT . . . . . 7-27

BRANCH RELATIVE ON INDEX HIGH . . 7-28BRANCH RELATIVE ON INDEX LOW

OR EQUAL . . . . . . . . . . . . . . . . 7-28CHECKSUM . . . . . . . . . . . . . . . . . 7-29COMPARE . . . . . . . . . . . . . . . . . . 7-32COMPARE AND FORM CODEWORD . . 7-33COMPARE AND SWAP . . . . . . . . . . . 7-40COMPARE DOUBLE AND SWAP . . . . . 7-40COMPARE HALFWORD . . . . . . . . . . 7-42COMPARE HALFWORD IMMEDIATE . . 7-42COMPARE LOGICAL . . . . . . . . . . . . 7-42COMPARE LOGICAL CHARACTERS

UNDER MASK . . . . . . . . . . . . . . 7-43COMPARE LOGICAL LONG . . . . . . . . 7-44COMPARE LOGICAL LONG EXTENDED 7-46COMPARE LOGICAL LONG UNICODE . 7-50COMPARE LOGICAL STRING . . . . . . . 7-53COMPARE UNTIL SUBSTRING EQUAL . 7-54COMPRESSION CALL . . . . . . . . . . . 7-58CONVERT TO BINARY . . . . . . . . . . . 7-69CONVERT TO DECIMAL . . . . . . . . . . 7-70CONVERT UNICODE TO UTF-8 . . . . . 7-71CONVERT UTF-8 TO UNICODE . . . . . 7-74COPY ACCESS . . . . . . . . . . . . . . . 7-77DIVIDE . . . . . . . . . . . . . . . . . . . . 7-77DIVIDE LOGICAL . . . . . . . . . . . . . . 7-77DIVIDE SINGLE . . . . . . . . . . . . . . . 7-78EXCLUSIVE OR . . . . . . . . . . . . . . . 7-79EXECUTE . . . . . . . . . . . . . . . . . . . 7-80EXTRACT ACCESS . . . . . . . . . . . . . 7-81EXTRACT PSW . . . . . . . . . . . . . . . 7-81INSERT CHARACTER . . . . . . . . . . . 7-81INSERT CHARACTERS UNDER MASK . 7-81INSERT IMMEDIATE . . . . . . . . . . . . 7-82INSERT PROGRAM MASK . . . . . . . . . 7-83LOAD . . . . . . . . . . . . . . . . . . . . . 7-83LOAD ACCESS MULTIPLE . . . . . . . . . 7-84LOAD ADDRESS . . . . . . . . . . . . . . 7-84LOAD ADDRESS EXTENDED . . . . . . . 7-84LOAD ADDRESS RELATIVE LONG . . . 7-85LOAD AND TEST . . . . . . . . . . . . . . 7-86LOAD COMPLEMENT . . . . . . . . . . . . 7-86LOAD HALFWORD . . . . . . . . . . . . . 7-87LOAD HALFWORD IMMEDIATE . . . . . 7-87LOAD LOGICAL . . . . . . . . . . . . . . . 7-87LOAD LOGICAL CHARACTER . . . . . . 7-87LOAD LOGICAL HALFWORD . . . . . . . 7-88LOAD LOGICAL IMMEDIATE . . . . . . . 7-88LOAD LOGICAL THIRTY ONE BITS . . . 7-88LOAD MULTIPLE . . . . . . . . . . . . . . 7-88LOAD MULTIPLE DISJOINT . . . . . . . . 7-89LOAD MULTIPLE HIGH . . . . . . . . . . . 7-89LOAD NEGATIVE . . . . . . . . . . . . . . 7-90LOAD PAIR FROM QUADWORD . . . . . 7-90

Contents vii

LOAD POSITIVE . . . . . . . . . . . . . . . 7-90LOAD REVERSED . . . . . . . . . . . . . . 7-91MONITOR CALL . . . . . . . . . . . . . . . 7-92MOVE . . . . . . . . . . . . . . . . . . . . . 7-93MOVE INVERSE . . . . . . . . . . . . . . . 7-93MOVE LONG . . . . . . . . . . . . . . . . . 7-94MOVE LONG EXTENDED . . . . . . . . . 7-97MOVE LONG UNICODE . . . . . . . . . 7-101MOVE NUMERICS . . . . . . . . . . . . . 7-104MOVE STRING . . . . . . . . . . . . . . . 7-104MOVE WITH OFFSET . . . . . . . . . . . 7-106MOVE ZONES . . . . . . . . . . . . . . . 7-106MULTIPLY . . . . . . . . . . . . . . . . . 7-107MULTIPLY HALFWORD . . . . . . . . . 7-107MULTIPLY HALFWORD IMMEDIATE . . 7-108MULTIPLY LOGICAL . . . . . . . . . . . 7-108MULTIPLY SINGLE . . . . . . . . . . . . 7-109OR . . . . . . . . . . . . . . . . . . . . . . 7-110OR IMMEDIATE . . . . . . . . . . . . . . 7-111PACK . . . . . . . . . . . . . . . . . . . . 7-111PACK ASCII . . . . . . . . . . . . . . . . 7-112PACK UNICODE . . . . . . . . . . . . . . 7-113PERFORM LOCKED OPERATION . . . 7-114ROTATE LEFT SINGLE LOGICAL . . . 7-129SEARCH STRING . . . . . . . . . . . . . 7-130SET ACCESS . . . . . . . . . . . . . . . 7-131SET ADDRESSING MODE . . . . . . . . 7-131SET PROGRAM MASK . . . . . . . . . . 7-132SHIFT LEFT DOUBLE . . . . . . . . . . . 7-132SHIFT LEFT DOUBLE LOGICAL . . . . 7-133SHIFT LEFT SINGLE . . . . . . . . . . . 7-134SHIFT LEFT SINGLE LOGICAL . . . . . 7-134SHIFT RIGHT DOUBLE . . . . . . . . . . 7-135SHIFT RIGHT DOUBLE LOGICAL . . . 7-135SHIFT RIGHT SINGLE . . . . . . . . . . 7-136SHIFT RIGHT SINGLE LOGICAL . . . . 7-136STORE . . . . . . . . . . . . . . . . . . . 7-137STORE ACCESS MULTIPLE . . . . . . . 7-137STORE CHARACTER . . . . . . . . . . . 7-137STORE CHARACTERS UNDER MASK . 7-138STORE CLOCK . . . . . . . . . . . . . . 7-138STORE CLOCK EXTENDED . . . . . . . 7-139STORE HALFWORD . . . . . . . . . . . 7-141STORE MULTIPLE . . . . . . . . . . . . 7-141STORE MULTIPLE HIGH . . . . . . . . . 7-142STORE PAIR TO QUADWORD . . . . . 7-142STORE REVERSED . . . . . . . . . . . . 7-142SUBTRACT . . . . . . . . . . . . . . . . . 7-143SUBTRACT HALFWORD . . . . . . . . . 7-144SUBTRACT LOGICAL . . . . . . . . . . . 7-144SUBTRACT LOGICAL WITH BORROW . 7-145SUPERVISOR CALL . . . . . . . . . . . 7-146TEST ADDRESSING MODE . . . . . . . 7-146TEST AND SET . . . . . . . . . . . . . . 7-146

TEST UNDER MASK (TEST UNDERMASK HIGH, TEST UNDER MASKLOW) . . . . . . . . . . . . . . . . . . 7-147

TRANSLATE . . . . . . . . . . . . . . . . 7-148TRANSLATE AND TEST . . . . . . . . . 7-149TRANSLATE EXTENDED . . . . . . . . 7-150TRANSLATE ONE TO ONE . . . . . . . 7-152TRANSLATE ONE TO TWO . . . . . . . 7-152TRANSLATE TWO TO ONE . . . . . . . 7-152TRANSLATE TWO TO TWO . . . . . . . 7-153UNPACK . . . . . . . . . . . . . . . . . . 7-157UNPACK ASCII . . . . . . . . . . . . . . 7-158UNPACK UNICODE . . . . . . . . . . . . 7-159UPDATE TREE . . . . . . . . . . . . . . . 7-160

Chapter 8. Decimal Instructions . . . . . . 8-1Decimal-Number Formats . . . . . . . . . . . 8-1

Zoned Format . . . . . . . . . . . . . . . . . 8-1Packed Format . . . . . . . . . . . . . . . . 8-1Decimal Codes . . . . . . . . . . . . . . . . 8-2

Decimal Operations . . . . . . . . . . . . . . . 8-2Decimal-Arithmetic Instructions . . . . . . . 8-2Editing Instructions . . . . . . . . . . . . . . 8-3Execution of Decimal Instructions . . . . . 8-3Other Instructions for Decimal Operands . 8-3Decimal-Operand Data Exception . . . . . 8-4

Instructions . . . . . . . . . . . . . . . . . . . . 8-4ADD DECIMAL . . . . . . . . . . . . . . . . 8-5COMPARE DECIMAL . . . . . . . . . . . . 8-6DIVIDE DECIMAL . . . . . . . . . . . . . . 8-6EDIT . . . . . . . . . . . . . . . . . . . . . . 8-7EDIT AND MARK . . . . . . . . . . . . . . 8-9MULTIPLY DECIMAL . . . . . . . . . . . . 8-11SHIFT AND ROUND DECIMAL . . . . . . 8-11SUBTRACT DECIMAL . . . . . . . . . . . 8-12TEST DECIMAL . . . . . . . . . . . . . . . 8-13ZERO AND ADD . . . . . . . . . . . . . . . 8-13

Chapter 9. Floating-Point Overview andSupport Instructions . . . . . . . . . . . . 9-1

Registers And Controls . . . . . . . . . . . . . 9-2Floating-Point Registers . . . . . . . . . . . 9-2

Additional Floating-Point (AFP)Registers . . . . . . . . . . . . . . . . 9-2

Valid Floating-Point-RegisterDesignations . . . . . . . . . . . . . . 9-2

Floating-Point-Control (FPC) Register . . . 9-2AFP-Register-Control Bit . . . . . . . . . . 9-2Explicit Rounding Methods . . . . . . . . . 9-3

Summary of Rounding Action . . . . . . 9-3Comparison of BFP and HFP Number

Representations . . . . . . . . . . . . . . . . 9-4BFP and HFP Number Ranges . . . . . . 9-4

viii z/Architecture Principles of Operation

Equivalent BFP and HFP NumberRepresentations . . . . . . . . . . . . . . 9-4

Instructions . . . . . . . . . . . . . . . . . . . . 9-8CONVERT BFP TO HFP . . . . . . . . . . 9-10CONVERT HFP TO BFP . . . . . . . . . . 9-11LOAD . . . . . . . . . . . . . . . . . . . . . 9-12LOAD ZERO . . . . . . . . . . . . . . . . . 9-13STORE . . . . . . . . . . . . . . . . . . . . 9-13

Summary of All Floating-Point Instructions . . 9-13

Chapter 10. Control Instructions . . . . . . 10-1BRANCH AND SET AUTHORITY . . . . . 10-6BRANCH AND STACK . . . . . . . . . . 10-10BRANCH IN SUBSPACE GROUP . . . . 10-13COMPARE AND SWAP AND PURGE . 10-18DIAGNOSE . . . . . . . . . . . . . . . . . 10-20EXTRACT AND SET EXTENDED

AUTHORITY . . . . . . . . . . . . . . 10-20EXTRACT PRIMARY ASN . . . . . . . . 10-20EXTRACT SECONDARY ASN . . . . . . 10-21EXTRACT STACKED REGISTERS . . . 10-21EXTRACT STACKED STATE . . . . . . 10-23INSERT ADDRESS SPACE CONTROL . 10-26INSERT PSW KEY . . . . . . . . . . . . . 10-27INSERT STORAGE KEY EXTENDED . 10-27INSERT VIRTUAL STORAGE KEY . . . 10-28INVALIDATE PAGE TABLE ENTRY . . . 10-29LOAD ADDRESS SPACE

PARAMETERS . . . . . . . . . . . . . 10-30LOAD CONTROL . . . . . . . . . . . . . 10-39LOAD PSW . . . . . . . . . . . . . . . . . 10-39LOAD PSW EXTENDED . . . . . . . . . 10-40LOAD REAL ADDRESS . . . . . . . . . . 10-41LOAD USING REAL ADDRESS . . . . . 10-46MODIFY STACKED STATE . . . . . . . 10-46MOVE PAGE . . . . . . . . . . . . . . . . 10-48MOVE TO PRIMARY . . . . . . . . . . . 10-50MOVE TO SECONDARY . . . . . . . . . 10-50MOVE WITH DESTINATION KEY . . . . 10-52MOVE WITH KEY . . . . . . . . . . . . . 10-53MOVE WITH SOURCE KEY . . . . . . . 10-54PAGE IN . . . . . . . . . . . . . . . . . . 10-55PAGE OUT . . . . . . . . . . . . . . . . . 10-56PROGRAM CALL . . . . . . . . . . . . . 10-57PROGRAM RETURN . . . . . . . . . . . 10-70PROGRAM TRANSFER . . . . . . . . . . 10-74PURGE ALB . . . . . . . . . . . . . . . . 10-79PURGE TLB . . . . . . . . . . . . . . . . 10-80RESET REFERENCE BIT EXTENDED . 10-80RESUME PROGRAM . . . . . . . . . . . 10-81SET ADDRESS SPACE CONTROL . . . 10-83SET ADDRESS SPACE CONTROL

FAST . . . . . . . . . . . . . . . . . . 10-83SET CLOCK . . . . . . . . . . . . . . . . 10-85

SET CLOCK COMPARATOR . . . . . . 10-86SET CLOCK PROGRAMMABLE FIELD . 10-86SET CPU TIMER . . . . . . . . . . . . . . 10-86SET PREFIX . . . . . . . . . . . . . . . . 10-87SET PSW KEY FROM ADDRESS . . . . 10-87SET SECONDARY ASN . . . . . . . . . 10-88SET STORAGE KEY EXTENDED . . . . 10-91SET SYSTEM MASK . . . . . . . . . . . 10-91SIGNAL PROCESSOR . . . . . . . . . . 10-91STORE CLOCK COMPARATOR . . . . 10-93STORE CONTROL . . . . . . . . . . . . 10-93STORE CPU ADDRESS . . . . . . . . . 10-94STORE CPU ID . . . . . . . . . . . . . . 10-94STORE CPU TIMER . . . . . . . . . . . . 10-95STORE FACILITY LIST . . . . . . . . . . 10-95STORE PREFIX . . . . . . . . . . . . . . 10-95STORE REAL ADDRESS . . . . . . . . . 10-96STORE SYSTEM INFORMATION . . . . 10-97STORE THEN AND SYSTEM MASK . 10-107STORE THEN OR SYSTEM MASK . . 10-107STORE USING REAL ADDRESS . . . 10-107TEST ACCESS . . . . . . . . . . . . . . 10-108TEST BLOCK . . . . . . . . . . . . . . . 10-110TEST PROTECTION . . . . . . . . . . 10-113TRACE . . . . . . . . . . . . . . . . . . 10-115TRAP . . . . . . . . . . . . . . . . . . . 10-116

Chapter 11. Machine-Check Handling . . . 11-1Machine-Check Detection . . . . . . . . . . . 11-2Correction of Machine Malfunctions . . . . . . 11-2

Error Checking and Correction . . . . . . . 11-2CPU Retry . . . . . . . . . . . . . . . . . . . 11-2

Effects of CPU Retry . . . . . . . . . . . 11-3Checkpoint Synchronization . . . . . . . 11-3Handling of Machine Checks during

Checkpoint Synchronization . . . . . 11-3Checkpoint-Synchronization Operations 11-3Checkpoint-Synchronization Action . . . 11-4

Channel-Subsystem Recovery . . . . . . . 11-4Unit Deletion . . . . . . . . . . . . . . . . . 11-4

Handling of Machine Checks . . . . . . . . . 11-5Validation . . . . . . . . . . . . . . . . . . . 11-5Invalid CBC in Storage . . . . . . . . . . . 11-6

Programmed Validation of Storage . . . 11-7Invalid CBC in Storage Keys . . . . . . . . 11-7Invalid CBC in Registers . . . . . . . . . 11-10

Check-Stop State . . . . . . . . . . . . . . . 11-11System Check Stop . . . . . . . . . . . 11-11

Machine-Check Interruption . . . . . . . . . 11-11Exigent Conditions . . . . . . . . . . . . . 11-11Repressible Conditions . . . . . . . . . . 11-12Interruption Action . . . . . . . . . . . . . 11-12Point of Interruption . . . . . . . . . . . . 11-14

Machine-Check-Interruption Code . . . . . . 11-15

Contents ix

Subclass . . . . . . . . . . . . . . . . . . . 11-16System Damage . . . . . . . . . . . . 11-16Instruction-Processing Damage . . . . 11-16System Recovery . . . . . . . . . . . . 11-16Timing-Facility Damage . . . . . . . . 11-16External Damage . . . . . . . . . . . . 11-17Degradation . . . . . . . . . . . . . . . 11-17Warning . . . . . . . . . . . . . . . . . 11-17Channel Report Pending . . . . . . . . 11-17Service-Processor Damage . . . . . . 11-18Channel-Subsystem Damage . . . . . 11-18

Subclass Modifiers . . . . . . . . . . . . . 11-18Backed Up . . . . . . . . . . . . . . . . 11-18Delayed Access Exception . . . . . . . 11-18Ancillary Report . . . . . . . . . . . . . 11-18

SynchronousMachine-Check-Interruption Conditions 11-18

Processing Backup . . . . . . . . . . . 11-18Processing Damage . . . . . . . . . . 11-19

Storage Errors . . . . . . . . . . . . . . . 11-19Storage Error Uncorrected . . . . . . . 11-19Storage Error Corrected . . . . . . . . 11-20Storage-Key Error Uncorrected . . . . 11-20Storage Degradation . . . . . . . . . . 11-20Indirect Storage Error . . . . . . . . . . 11-20

Machine-Check Interruption-CodeValidity Bits . . . . . . . . . . . . . . . 11-21

PSW-MWP Validity . . . . . . . . . . . 11-21PSW Mask and Key Validity . . . . . . 11-21PSW Program-Mask and

Condition-Code Validity . . . . . . 11-21PSW-Instruction-Address Validity . . . 11-21Failing-Storage-Address Validity . . . 11-21External-Damage-Code Validity . . . . 11-21Floating-Point-Register Validity . . . . 11-21General-Register Validity . . . . . . . . 11-21Control-Register Validity . . . . . . . . 11-21Storage Logical Validity . . . . . . . . 11-22Access-Register Validity . . . . . . . . 11-22TOD-Programmable-Register Validity . 11-22Floating-Point-Control-Register

Validity . . . . . . . . . . . . . . . . 11-22CPU-Timer Validity . . . . . . . . . . . 11-22Clock-Comparator Validity . . . . . . . 11-22

Machine-Check Extended InterruptionInformation . . . . . . . . . . . . . . . . . 11-22

Register-Save Areas . . . . . . . . . . . . 11-22External-Damage Code . . . . . . . . . . 11-23Failing-Storage Address . . . . . . . . . . 11-23

Handling of Machine-Check Conditions . . 11-23Floating Interruption Conditions . . . . . 11-23

Floating Machine-Check-InterruptionConditions . . . . . . . . . . . . . . 11-24

Floating I/O Interruptions . . . . . . . . 11-24

Machine-Check Masking . . . . . . . . . . . 11-24Channel-Report-Pending Subclass

Mask . . . . . . . . . . . . . . . . . 11-24Recovery Subclass Mask . . . . . . . 11-25Degradation Subclass Mask . . . . . . 11-25External-Damage Subclass Mask . . . 11-25Warning Subclass Mask . . . . . . . . 11-25

Machine-Check Logout . . . . . . . . . . . . 11-25Summary of Machine-Check Masking . . . 11-25

Chapter 12. Operator Facilities . . . . . . . 12-1Manual Operation . . . . . . . . . . . . . . . . 12-1Basic Operator Facilities . . . . . . . . . . . . 12-1

Address-Compare Controls . . . . . . . . . 12-1Alter-and-Display Controls . . . . . . . . . 12-2Architectural-Mode Indicator . . . . . . . . 12-2Architectural-Mode-Selection Controls . . . 12-2Check-Stop Indicator . . . . . . . . . . . . 12-3IML Controls . . . . . . . . . . . . . . . . . 12-3Interrupt Key . . . . . . . . . . . . . . . . . 12-3Load Indicator . . . . . . . . . . . . . . . . 12-3Load-Clear Key . . . . . . . . . . . . . . . . 12-3Load-Normal Key . . . . . . . . . . . . . . . 12-3Load-Unit-Address Controls . . . . . . . . . 12-3Manual Indicator . . . . . . . . . . . . . . . 12-3Power Controls . . . . . . . . . . . . . . . . 12-4Rate Control . . . . . . . . . . . . . . . . . 12-4Restart Key . . . . . . . . . . . . . . . . . . 12-4Start Key . . . . . . . . . . . . . . . . . . . 12-4Stop Key . . . . . . . . . . . . . . . . . . . 12-4Store-Status Key . . . . . . . . . . . . . . . 12-5System-Reset-Clear Key . . . . . . . . . . 12-5System-Reset-Normal Key . . . . . . . . . 12-5Test Indicator . . . . . . . . . . . . . . . . . 12-5TOD-Clock Control . . . . . . . . . . . . . . 12-5Wait Indicator . . . . . . . . . . . . . . . . . 12-6

Multiprocessing Configurations . . . . . . . . 12-6

Chapter 13. I/O Overview . . . . . . . . . . 13-1Input/Output (I/O) . . . . . . . . . . . . . . . . 13-1The Channel Subsystem . . . . . . . . . . . . 13-1

Subchannels . . . . . . . . . . . . . . . . . 13-2Attachment of Input/Output Devices . . . . . 13-2

Channel Paths . . . . . . . . . . . . . . . . 13-2Control Units . . . . . . . . . . . . . . . . . 13-4I/O Devices . . . . . . . . . . . . . . . . . . 13-4

I/O Addressing . . . . . . . . . . . . . . . . . . 13-5Channel-Path Identifier . . . . . . . . . . . 13-5Subchannel Number . . . . . . . . . . . . . 13-5Device Number . . . . . . . . . . . . . . . . 13-5Device Identifier . . . . . . . . . . . . . . . 13-5

Execution of I/O Operations . . . . . . . . . . 13-6Start-Function Initiation . . . . . . . . . . . 13-6Path Management . . . . . . . . . . . . . . 13-6

x z/Architecture Principles of Operation

Channel-Program Execution . . . . . . . . 13-7Conclusion of I/O Operations . . . . . . . . 13-7I/O Interruptions . . . . . . . . . . . . . . . 13-9

Chapter 14. I/O Instructions . . . . . . . . . 14-1I/O-Instruction Formats . . . . . . . . . . . . . 14-1I/O-Instruction Execution . . . . . . . . . . . . 14-1

Serialization . . . . . . . . . . . . . . . . . . 14-1Operand Access . . . . . . . . . . . . . . . 14-1Condition Code . . . . . . . . . . . . . . . . 14-2Program Exceptions . . . . . . . . . . . . . 14-2

Instructions . . . . . . . . . . . . . . . . . . . . 14-2CANCEL SUBCHANNEL . . . . . . . . . . 14-4CLEAR SUBCHANNEL . . . . . . . . . . . 14-4HALT SUBCHANNEL . . . . . . . . . . . . 14-5MODIFY SUBCHANNEL . . . . . . . . . . 14-7RESET CHANNEL PATH . . . . . . . . . . 14-8RESUME SUBCHANNEL . . . . . . . . . . 14-9SET ADDRESS LIMIT . . . . . . . . . . . 14-11SET CHANNEL MONITOR . . . . . . . . 14-12START SUBCHANNEL . . . . . . . . . . 14-14STORE CHANNEL PATH STATUS . . . 14-15STORE CHANNEL REPORT WORD . . 14-16STORE SUBCHANNEL . . . . . . . . . . 14-17TEST PENDING INTERRUPTION . . . . 14-17TEST SUBCHANNEL . . . . . . . . . . . 14-19

Chapter 15. Basic I/O Functions . . . . . . 15-1Control of Basic I/O Functions . . . . . . . . . 15-1

Subchannel-Information Block . . . . . . . 15-1Path-Management-Control Word . . . . 15-2Subchannel-Status Word . . . . . . . . . 15-7Model-Dependent Area . . . . . . . . . . 15-7Summary of Modifiable Fields . . . . . . 15-7

Channel-Path Allegiance . . . . . . . . . . . 15-10Working Allegiance . . . . . . . . . . . . . 15-11Active Allegiance . . . . . . . . . . . . . . 15-11Dedicated Allegiance . . . . . . . . . . . 15-11Channel-Path Availability . . . . . . . . . 15-12Control-Unit Type . . . . . . . . . . . . . 15-12

Clear Function . . . . . . . . . . . . . . . . . 15-13Clear-Function Path Management . . . . 15-13Clear-Function Subchannel Modification . 15-13Clear-Function Signaling and

Completion . . . . . . . . . . . . . . . 15-14Halt Function . . . . . . . . . . . . . . . . . . 15-14

Halt-Function Path Management . . . . . 15-15Halt-Function Signaling and Completion . 15-15

Start Function and Resume Function . . . . 15-17Start-Function and Resume-Function

Path Management . . . . . . . . . . . 15-18Execution of I/O Operations . . . . . . . . . 15-20

Blocking of Data . . . . . . . . . . . . . . 15-21Operation-Request Block . . . . . . . . . 15-21

Channel-Command Word . . . . . . . . . 15-26Command Code . . . . . . . . . . . . . . 15-28Designation of Storage Area . . . . . . . 15-28Chaining . . . . . . . . . . . . . . . . . . . 15-30

Data Chaining . . . . . . . . . . . . . . 15-32Command Chaining . . . . . . . . . . . 15-33

Skipping . . . . . . . . . . . . . . . . . . . 15-34Program-Controlled Interruption . . . . . 15-34CCW Indirect Data Addressing . . . . . . 15-35Suspension of Channel-Program

Execution . . . . . . . . . . . . . . . . 15-37Commands and Flags . . . . . . . . . . . 15-39Branching in Channel Programs . . . . . 15-40

Transfer in Channel . . . . . . . . . . . 15-40Command Retry . . . . . . . . . . . . . . 15-41

Concluding I/O Operations Prior to Initiation 15-41Concluding I/O Operations during Initiation . 15-41Immediate Conclusion of I/O Operations . . 15-42Concluding I/O Operations During Data

Transfer . . . . . . . . . . . . . . . . . . 15-42Channel-Path-Reset Function . . . . . . . . 15-44

Channel-Path-Reset-Function Signaling . 15-44Channel-Path-Reset

Function-Completion Signaling . . . . 15-44

Chapter 16. I/O Interruptions . . . . . . . . 16-1Interruption Conditions . . . . . . . . . . . . . 16-2

Intermediate Interruption Condition . . . . 16-4Primary Interruption Condition . . . . . . . 16-4Secondary Interruption Condition . . . . . 16-4Alert Interruption Condition . . . . . . . . . 16-4

Priority of Interruptions . . . . . . . . . . . . . 16-5Interruption Action . . . . . . . . . . . . . . . . 16-5Interruption-Response Block . . . . . . . . . . 16-6Subchannel-Status Word . . . . . . . . . . . . 16-6

Subchannel Key . . . . . . . . . . . . . . 16-8Suspend Control (S) . . . . . . . . . . . 16-8Extended-Status-Word Format (L) . . . 16-8Deferred Condition Code (CC) . . . . . 16-8Format (F) . . . . . . . . . . . . . . . . 16-10Prefetch (P) . . . . . . . . . . . . . . . 16-10Initial-Status-Interruption Control (I) . . 16-11Address-Limit-Checking Control (A) . 16-11Suppress-Suspended Interruption (U) . 16-11

Subchannel-Control Field . . . . . . . . . 16-11Zero Condition Code (Z) . . . . . . . . 16-11Extended Control (E) . . . . . . . . . . 16-11Path Not Operational (N) . . . . . . . . 16-12Function Control (FC) . . . . . . . . . 16-12Activity Control (AC) . . . . . . . . . . 16-13Status Control (SC) . . . . . . . . . . . 16-16

CCW-Address Field . . . . . . . . . . . . 16-18Device-Status Field . . . . . . . . . . . . 16-23Subchannel-Status Field . . . . . . . . . 16-23

Contents xi

Program-Controlled Interruption . . . . 16-23Incorrect Length . . . . . . . . . . . . . 16-23Program Check . . . . . . . . . . . . . 16-24Protection Check . . . . . . . . . . . . 16-26Channel-Data Check . . . . . . . . . . 16-26Channel-Control Check . . . . . . . . 16-27Interface-Control Check . . . . . . . . 16-28Chaining Check . . . . . . . . . . . . . 16-29

Count Field . . . . . . . . . . . . . . . . . 16-29Extended-Status Word . . . . . . . . . . . . 16-32

Extended-Status Format 0 . . . . . . . . 16-32Subchannel Logout . . . . . . . . . . . 16-32Extended-Report Word . . . . . . . . . 16-36Failing-Storage Address . . . . . . . . 16-37Secondary-CCW Address . . . . . . . 16-38

Extended-Status Format 1 . . . . . . . . 16-38Extended-Status Format 2 . . . . . . . . 16-38Extended-Status Format 3 . . . . . . . . 16-39

Extended-Control Word . . . . . . . . . . . . 16-40

Chapter 17. I/O Support Functions . . . . 17-1Channel-Subsystem Monitoring . . . . . . . . 17-1

Channel-Subsystem Timing . . . . . . . . . 17-1Channel-Subsystem Timer . . . . . . . . 17-2

Measurement-Block Update . . . . . . . . 17-2Measurement Block . . . . . . . . . . . . 17-3Measurement-Block Origin . . . . . . . . 17-5Measurement-Block Key . . . . . . . . . 17-6Measurement-Block Index . . . . . . . . 17-6Measurement-Block-Update Mode . . . 17-6Measurement-Block-Update Enable . . 17-6Control-Unit-Queuing Measurement . . 17-7Control-Unit-Defer Time . . . . . . . . . 17-7Device-Active-Only Measurement . . . . 17-7Time-Interval-Measurement Accuracy . 17-7

Device-Connect-Time Measurement . . . . 17-8Device-Connect-Time-Measurement

Mode . . . . . . . . . . . . . . . . . . 17-8Device-Connect-Time-Measurement

Enable . . . . . . . . . . . . . . . . . 17-8Signals and Resets . . . . . . . . . . . . . . . 17-9

Signals . . . . . . . . . . . . . . . . . . . . . 17-9Halt Signal . . . . . . . . . . . . . . . . . 17-9Clear Signal . . . . . . . . . . . . . . . . 17-9Reset Signal . . . . . . . . . . . . . . . 17-10

Resets . . . . . . . . . . . . . . . . . . . . 17-10Channel-Path Reset . . . . . . . . . . 17-10I/O-System Reset . . . . . . . . . . . . 17-10

Externally Initiated Functions . . . . . . . . 17-14Initial Program Loading . . . . . . . . . . 17-15Reconfiguration of the I/O System . . . . 17-17

Status Verification . . . . . . . . . . . . . . . 17-17Address-Limit Checking . . . . . . . . . . . 17-17Configuration Alert . . . . . . . . . . . . . . 17-18

Incorrect-Length-Indication Suppression . . 17-18Concurrent Sense . . . . . . . . . . . . . . . 17-18Channel-Subsystem Recovery . . . . . . . . 17-19

Channel Report . . . . . . . . . . . . . . . 17-19Channel-Report Word . . . . . . . . . . . 17-21

Channel Subsystem I/O-Priority Facility . . 17-22Number of Channel Subsystem

Priority Levels . . . . . . . . . . . . 17-23

Chapter 18. Hexadecimal-Floating-PointInstructions . . . . . . . . . . . . . . . . . 18-1

HFP Arithmetic . . . . . . . . . . . . . . . . . . 18-1HFP Number Representation . . . . . . . . 18-1Normalization . . . . . . . . . . . . . . . . . 18-3HFP Data Format . . . . . . . . . . . . . . 18-3

Instructions . . . . . . . . . . . . . . . . . . . . 18-4ADD NORMALIZED . . . . . . . . . . . . . 18-8ADD UNNORMALIZED . . . . . . . . . . . 18-9COMPARE . . . . . . . . . . . . . . . . . 18-10CONVERT FROM FIXED . . . . . . . . . 18-11CONVERT TO FIXED . . . . . . . . . . . 18-11DIVIDE . . . . . . . . . . . . . . . . . . . 18-12HALVE . . . . . . . . . . . . . . . . . . . . 18-13LOAD AND TEST . . . . . . . . . . . . . 18-14LOAD COMPLEMENT . . . . . . . . . . . 18-14LOAD FP INTEGER . . . . . . . . . . . . 18-15LOAD LENGTHENED . . . . . . . . . . . 18-15LOAD NEGATIVE . . . . . . . . . . . . . 18-16LOAD POSITIVE . . . . . . . . . . . . . . 18-16LOAD ROUNDED . . . . . . . . . . . . . 18-17MULTIPLY . . . . . . . . . . . . . . . . . 18-18SQUARE ROOT . . . . . . . . . . . . . . 18-19SUBTRACT NORMALIZED . . . . . . . . 18-21SUBTRACT UNNORMALIZED . . . . . . 18-21

Chapter 19. Binary-Floating-PointInstructions . . . . . . . . . . . . . . . . . 19-1

Binary-Floating-Point Facility . . . . . . . . . . 19-1Floating-Point-Control (FPC) Register . . . 19-2

IEEE Masks and Flags . . . . . . . . . . 19-3FPC DXC Byte . . . . . . . . . . . . . . 19-3Operations on the FPC Register . . . . 19-3

BFP Arithmetic . . . . . . . . . . . . . . . . . . 19-4BFP Data Formats . . . . . . . . . . . . . . 19-4

BFP Short Format . . . . . . . . . . . . . 19-4BFP Long Format . . . . . . . . . . . . . 19-4BFP Extended Format . . . . . . . . . . 19-4Biased Exponent . . . . . . . . . . . . . 19-4Significand . . . . . . . . . . . . . . . . . 19-4Values of Nonzero Numbers . . . . . . 19-4

Classes of BFP Data . . . . . . . . . . . . 19-5Zeros . . . . . . . . . . . . . . . . . . . . 19-6Denormalized Numbers . . . . . . . . . 19-6Normalized Numbers . . . . . . . . . . . 19-6

xii z/Architecture Principles of Operation

Infinities . . . . . . . . . . . . . . . . . . 19-6Signaling and Quiet NaNs . . . . . . . . 19-6

BFP-Format Conversion . . . . . . . . . . . 19-7BFP Rounding . . . . . . . . . . . . . . . . 19-7

Rounding Mode . . . . . . . . . . . . . . 19-7Normalization and Denormalization . . . . 19-8BFP Comparison . . . . . . . . . . . . . . . 19-8Condition Codes for BFP Instructions . . . 19-9Remainder . . . . . . . . . . . . . . . . . . 19-9IEEE Exception Conditions . . . . . . . . 19-10

IEEE Invalid Operation . . . . . . . . . 19-10IEEE Division-By-Zero . . . . . . . . . 19-11IEEE Overflow . . . . . . . . . . . . . . 19-11IEEE Underflow . . . . . . . . . . . . . 19-12IEEE Inexact . . . . . . . . . . . . . . . 19-12

Result Figures . . . . . . . . . . . . . . . . . 19-13Data-Exception Codes (DXC) and

Abbreviations . . . . . . . . . . . . . . 19-14Instructions . . . . . . . . . . . . . . . . . . . 19-14

ADD . . . . . . . . . . . . . . . . . . . . . 19-18COMPARE . . . . . . . . . . . . . . . . . 19-23COMPARE AND SIGNAL . . . . . . . . . 19-24CONVERT FROM FIXED . . . . . . . . . 19-26CONVERT TO FIXED . . . . . . . . . . . 19-26DIVIDE . . . . . . . . . . . . . . . . . . . 19-29DIVIDE TO INTEGER . . . . . . . . . . . 19-29EXTRACT FPC . . . . . . . . . . . . . . . 19-34LOAD AND TEST . . . . . . . . . . . . . 19-35LOAD COMPLEMENT . . . . . . . . . . . 19-35LOAD FP INTEGER . . . . . . . . . . . . 19-36LOAD FPC . . . . . . . . . . . . . . . . . 19-37LOAD LENGTHENED . . . . . . . . . . . 19-38LOAD NEGATIVE . . . . . . . . . . . . . 19-38LOAD POSITIVE . . . . . . . . . . . . . . 19-39LOAD ROUNDED . . . . . . . . . . . . . 19-39MULTIPLY . . . . . . . . . . . . . . . . . 19-40MULTIPLY AND ADD . . . . . . . . . . . 19-42MULTIPLY AND SUBTRACT . . . . . . . 19-42SET FPC . . . . . . . . . . . . . . . . . . 19-44SET ROUNDING MODE . . . . . . . . . 19-44SQUARE ROOT . . . . . . . . . . . . . . 19-45STORE FPC . . . . . . . . . . . . . . . . 19-45SUBTRACT . . . . . . . . . . . . . . . . . 19-46TEST DATA CLASS . . . . . . . . . . . . 19-46

Appendix A. Number Representation andInstruction-Use Examples . . . . . . . . . A-1

Number Representation . . . . . . . . . . . . A-2Binary Integers . . . . . . . . . . . . . . . . A-2

Signed Binary Integers . . . . . . . . . . A-2Unsigned Binary Integers . . . . . . . . A-3

Decimal Integers . . . . . . . . . . . . . . . A-4Hexadecimal-Floating-Point Numbers . . . A-5Conversion Example . . . . . . . . . . . . . A-6

Instruction-Use Examples . . . . . . . . . . . A-6Machine Format . . . . . . . . . . . . . . . A-7Assembler-Language Format . . . . . . . . A-7

Addressing Mode in Examples . . . . . A-7General Instructions . . . . . . . . . . . . . . . A-7

ADD HALFWORD (AH) . . . . . . . . . . . A-7AND (N, NC, NI, NR) . . . . . . . . . . . . A-8

NI Example . . . . . . . . . . . . . . . . A-8Linkage Instructions (BAL, BALR, BAS,

BASR, BASSM, BSM) . . . . . . . . . . . A-8Other BALR and BASR Examples . . . A-9

BRANCH AND STACK (BAKR) . . . . . A-10BAKR Example 1 . . . . . . . . . . . . A-10BAKR Example 2 . . . . . . . . . . . . A-11BAKR Example 3 . . . . . . . . . . . . A-11

BRANCH ON CONDITION (BC, BCR) . A-11BRANCH ON COUNT (BCT, BCTR) . . A-12BRANCH ON INDEX HIGH (BXH) . . . . A-12

BXH Example 1 . . . . . . . . . . . . . A-12BXH Example 2 . . . . . . . . . . . . . A-13

BRANCH ON INDEX LOW OR EQUAL(BXLE) . . . . . . . . . . . . . . . . . . A-13

BXLE Example 1 . . . . . . . . . . . . A-13BXLE Example 2 . . . . . . . . . . . . A-14

COMPARE AND FORM CODEWORD(CFC) . . . . . . . . . . . . . . . . . . . A-14

COMPARE HALFWORD (CH) . . . . . . A-14COMPARE LOGICAL (CL, CLC, CLI,

CLR) . . . . . . . . . . . . . . . . . . . . A-14CLC Example . . . . . . . . . . . . . . A-14CLI Example . . . . . . . . . . . . . . . A-15CLR Example . . . . . . . . . . . . . . A-15

COMPARE LOGICAL CHARACTERSUNDER MASK (CLM) . . . . . . . . . . A-15

COMPARE LOGICAL LONG (CLCL) . . A-16COMPARE LOGICAL STRING (CLST) . A-17CONVERT TO BINARY (CVB) . . . . . . A-18CONVERT TO DECIMAL (CVD) . . . . . A-18DIVIDE (D, DR) . . . . . . . . . . . . . . . A-19EXCLUSIVE OR (X, XC, XI, XR) . . . . A-19

XC Example . . . . . . . . . . . . . . . A-19XI Example . . . . . . . . . . . . . . . A-20

EXECUTE (EX) . . . . . . . . . . . . . . . A-21INSERT CHARACTERS UNDER MASK

(ICM) . . . . . . . . . . . . . . . . . . . A-21LOAD (L, LR) . . . . . . . . . . . . . . . . A-22LOAD ADDRESS (LA) . . . . . . . . . . . A-22LOAD HALFWORD (LH) . . . . . . . . . A-23MOVE (MVC, MVI) . . . . . . . . . . . . . A-23

MVC Example . . . . . . . . . . . . . . A-23MVI Example . . . . . . . . . . . . . . A-24

MOVE INVERSE (MVCIN) . . . . . . . . A-24MOVE LONG (MVCL) . . . . . . . . . . . A-25MOVE NUMERICS (MVN) . . . . . . . . A-25

Contents xiii

MOVE STRING (MVST) . . . . . . . . . . A-26MOVE WITH OFFSET (MVO) . . . . . . A-26MOVE ZONES (MVZ) . . . . . . . . . . . A-27MULTIPLY (M, MR) . . . . . . . . . . . . A-27MULTIPLY HALFWORD (MH) . . . . . . A-27OR (O, OC, OI, OR) . . . . . . . . . . . . A-28

OI Example . . . . . . . . . . . . . . . A-28PACK (PACK) . . . . . . . . . . . . . . . A-28SEARCH STRING (SRST) . . . . . . . . A-29

SRST Example 1 . . . . . . . . . . . . A-29SRST Example 2 . . . . . . . . . . . . A-29

SHIFT LEFT DOUBLE (SLDA) . . . . . . A-29SHIFT LEFT SINGLE (SLA) . . . . . . . A-30STORE CHARACTERS UNDER MASK

(STCM) . . . . . . . . . . . . . . . . . . A-30STORE MULTIPLE (STM) . . . . . . . . A-30TEST UNDER MASK (TM) . . . . . . . . A-31TRANSLATE (TR) . . . . . . . . . . . . . A-31TRANSLATE AND TEST (TRT) . . . . . A-32UNPACK (UNPK) . . . . . . . . . . . . . A-33UPDATE TREE (UPT) . . . . . . . . . . . A-34

Decimal Instructions . . . . . . . . . . . . . . A-34ADD DECIMAL (AP) . . . . . . . . . . . . A-34COMPARE DECIMAL (CP) . . . . . . . . A-34DIVIDE DECIMAL (DP) . . . . . . . . . . A-34EDIT (ED) . . . . . . . . . . . . . . . . . . A-35EDIT AND MARK (EDMK) . . . . . . . . A-36MULTIPLY DECIMAL (MP) . . . . . . . . A-36SHIFT AND ROUND DECIMAL (SRP) . A-37

Decimal Left Shift . . . . . . . . . . . . A-37Decimal Right Shift . . . . . . . . . . . A-37Decimal Right Shift and Round . . . . A-38Multiplying by a Variable Power of 10 . A-38

ZERO AND ADD (ZAP) . . . . . . . . . . A-38Hexadecimal-Floating-Point Instructions . . A-39

ADD NORMALIZED (AD, ADR, AE, AER,AXR) . . . . . . . . . . . . . . . . . . . . A-39

ADD UNNORMALIZED (AU, AUR, AW,AWR) . . . . . . . . . . . . . . . . . . . A-39

COMPARE (CD, CDR, CE, CER) . . . . A-40DIVIDE (DD, DDR, DE, DER) . . . . . . A-40HALVE (HDR, HER) . . . . . . . . . . . . A-41

MULTIPLY (MD, MDR, MDE, MDER,MXD, MXDR, MXR) . . . . . . . . . . . A-41

Hexadecimal-Floating-Point-NumberConversion . . . . . . . . . . . . . . . . A-42

Fixed Point to Hexadecimal FloatingPoint . . . . . . . . . . . . . . . . . . A-42

Hexadecimal Floating Point to FixedPoint . . . . . . . . . . . . . . . . . . A-42

Multiprogramming and MultiprocessingExamples . . . . . . . . . . . . . . . . . . A-43

Example of a Program Failure Using ORImmediate . . . . . . . . . . . . . . . . A-43

Conditional Swapping Instructions (CS,CDS) . . . . . . . . . . . . . . . . . . . A-44

Setting a Single Bit . . . . . . . . . . . A-44Updating Counters . . . . . . . . . . . A-45

Bypassing Post and Wait . . . . . . . . . A-45Bypass Post Routine . . . . . . . . . . A-45Bypass Wait Routine . . . . . . . . . . A-46

Lock/Unlock . . . . . . . . . . . . . . . . . A-46Lock/Unlock with LIFO Queuing for

Contentions . . . . . . . . . . . . . . A-46Lock/Unlock with FIFO Queuing for

Contentions . . . . . . . . . . . . . . A-47Free-Pool Manipulation . . . . . . . . . . A-48PERFORM LOCKED OPERATION (PLO) A-50

Sorting Instructions . . . . . . . . . . . . . . A-51Tree Format . . . . . . . . . . . . . . . . . A-51Example of Use of Sort Instructions . . . A-53

Appendix B. Lists of Instructions . . . . . B-1

Appendix C. Condition-Code Settings . . C-1

Appendix G. Table of Powers of 2 . . . . . G-1

Appendix H. Hexadecimal Tables . . . . . H-1

Appendix I. EBCDIC and Other Codes . . . I-1

Index . . . . . . . . . . . . . . . . . . . . . . . X-1

xiv z/Architecture Principles of Operation

Notices

References in this publication to IBM products,programs or services do not imply that IBMintends to make these available in all countries inwhich IBM operates. Any reference to an IBMproduct, program, or service is not intended tostate or imply that only IBM's product, program, orservice may be used. Any functionally equivalentproduct, program, or service that does not infringeany of IBM's intellectual property rights may beused instead of the IBM product, program, orservice. Evaluation and verification of operation inconjunction with other products, except thoseexpressly designated by IBM, is the user's respon-sibility.

IBM may have patents or pending patent applica-tions covering subject matter in this document.The furnishing of this document does not give youany license to these patents. You can sendlicense inquiries, in writing, to the IBM Director ofLicensing, IBM Corporation, 500 ColumbusAvenue, Thornwood, NY, 10594 USA.

Trademarks

The following terms, denoted by an asterisk (*) atthe first or most prominent occurrence in this pub-lication, are trademarks of the International Busi-ness Machines Corporation in the United States orother countries:

AIX/ESA BookMaster CICS DB2

Enterprise Systems Architecture/370Enterprise Systems Architecture/390Enterprise Systems Connection Architecture

ESA/370 ESA/390 ESCON FICON MVS/ESA OS/390

Processor Resource/Systems Manager PR/SM Sysplex Timer System/370 VM/ESA z/Architecture z/OS

Copyright IBM Corp. 1990, 2000 xv

xvi z/Architecture Principles of Operation

Preface

This publication provides, for reference purposes,a detailed z/Architecture* description.

The publication applies only to systems operatingas defined by z/Architecture. For systems oper-ating in accordance with the Enterprise SystemsArchitecture/390* (ESA/390*) definition, the IBMESA/390 Principles of Operation, SA22-7201,should be consulted.

The publication describes each function at thelevel of detail needed to prepare an assembler-language program that relies on that function. Itdoes not, however, describe the notation and con-ventions that must be employed in preparing sucha program, for which the user must instead referto the appropriate assembler-language publication.

The information in this publication is provided prin-cipally for use by assembler-language program-mers, although anyone concerned with thefunctional details of z/Architecture will find ituseful.

This publication is written as a reference andshould not be considered an introduction or a text-book. It assumes the user has a basic knowledgeof data-processing systems.

All facilities discussed in this publication are notnecessarily available on every model. Further-more, in some instances the definitions have beenstructured to allow for some degree ofextendibility, and therefore certain capabilities maybe described or implied that are not offered onany model. Examples of such capabilities are theuse of a 16-bit field in the subsystem-identificationword to identify the channel subsystem, the size ofthe CPU address, and the number of CPUssharing main storage. The allowance for this typeof extendibility should not be construed asimplying any intention by IBM to provide suchcapabilities. For information about the character-istics and availability of facilities on a specificmodel, see the functional characteristics publica-tion for that model.

Largely because this publication is arranged forreference, certain words and phrases appear, ofnecessity, earlier in the publication than the prin-cipal discussions explaining them. The readerwho encounters a problem because of thisarrangement should refer to the index, which indi-cates the location of the key description.

The information presented in this publication isgrouped in 19 chapters and several appendixes:

Chapter 1, Introduction, highlights the major facili-ties of z/Architecture.

Chapter 2, Organization, describes the majorgroupings within the system—main storage,expanded storage, the central processing unit(CPU), the external time reference (ETR), andinput/output—with some attention given to thecomposition and characteristics of thosegroupings.

Chapter 3, Storage, explains the informationformats, the addressing of storage, and the facili-ties for storage protection. It also deals withdynamic address translation (DAT), which,coupled with special programming support, makesthe use of a virtual storage possible.

Chapter 4, Control, describes the facilities for theswitching of system status, for special externallyinitiated operations, for debugging, and for timing.It deals specifically with CPU states, controlmodes, the program-status word (PSW), controlregisters, tracing, program-event recording, timingfacilities, resets, store status, and initial programloading.

Chapter 5, Program Execution, explains the role ofinstructions in program execution, looks in detail atinstruction formats, and describes briefly the useof the program-status word (PSW), of branching,and of interruptions. It contains the principaldescription of the advanced address-space facili-ties that were introduced in ESA/370*. It alsodetails the aspects of program execution on one

z/Architecture, Enterprise Systems Architecture/390, ESA/390, and ESA/370 are trademarks of the International BusinessMachines Corporation.

Copyright IBM Corp. 1990, 2000 xvii

CPU as observed by other CPUs and by channelprograms.

Chapter 6, Interruptions, details the mechanismthat permits the CPU to change its state as aresult of conditions external to the system, withinthe system, or within the CPU itself. Six classesof interruptions are identified and described:machine-check interruptions, program inter-ruptions, supervisor-call interruptions, externalinterruptions, input/output interruptions, and restartinterruptions.

Chapter 7, General Instructions, contains detaileddescriptions of logical and binary-integer dataformats and of all unprivileged instructions exceptthe decimal and floating-point instructions.

Chapter 8, Decimal Instructions, describes indetail decimal data formats and the decimalinstructions.

Chapter 9, Floating-Point Overview and SupportInstructions, includes an introduction to thefloating-point operations, detailed descriptions ofthose instructions common to both hexadecimal-floating-point and binary-floating-point operations,and summaries of all floating-point instructions.

Chapter 10, Control Instructions, contains detaileddescriptions of all of the semiprivileged and privi-leged instructions except for the I/O instructions.

Chapter 11, Machine-Check Handling, describesthe mechanisms for detecting, correcting, andreporting machine malfunctions.

Chapter 12, Operator Facilities, describes thebasic manual functions and controls available foroperating and controlling the system.

Chapters 13-17 of this publication provide adetailed definition of the functions performed bythe channel subsystem and the logical interfacebetween the CPU and the channel subsystem.

Chapter 13, I/O Overview, provides a briefdescription of the basic components and operationof the channel subsystem.

Chapter 14, I/O Instructions, contains thedescription of the I/O instructions.

Chapter 15, Basic I/O Functions, describes thebasic I/O functions performed by the channel sub-system, including the initiation, control, and con-clusion of I/O operations.

Chapter 16, I/O Interruptions, covers I/O inter-ruptions and interruption conditions.

Chapter 17, I/O Support Functions, describes suchfunctions as channel-subsystem usage monitoring,resets, initial-program loading, reconfiguration, andchannel-subsystem recovery.

Chapter 18, Hexadecimal-Floating-PointInstructions, contains detailed descriptions of thehexadecimal-floating-point (HFP) data formats andthe HFP instructions.

Chapter 19, Binary-Floating-Point Instructions,contains detailed descriptions of the binary-floating-point (BFP) data formats and the BFPinstructions.

The Appendixes include:

Information about number representation Instruction-use examples Lists of the instructions arranged in several

sequences A summary of the condition-code settings A table of the powers of 2 Tabular information helpful in dealing with

hexadecimal numbers A table of EBCDIC and other codes.

Size and Number Notation

In this publication, the letters K, M, G, T, P, and Edenote the multipliers 2ñð, 2òð, 2óð, 2ôð, 2õð, and2öð, respectively. Although the letters are bor-rowed from the decimal system and stand for kilo(10ó), mega (10ö), giga (10ù), tera (10ñò), peta(10ñõ), and exa (10ñø), they do not have thedecimal meaning but instead represent the powerof 2 closest to the corresponding power of 10.Their meaning in this publication is as follows:

xviii z/Architecture Principles of Operation

┌──────────┬─────────────────────────────────┐│ Symbol │ Value │├──────────┼─────────────────────────────────┤│ K (kilo) │ 1,ð24 = 2ñð ││ │ ││ M (mega) │ 1,ð48,576 = 2òð ││ │ ││ G (giga) │ 1,ð73,741,824 = 2óð ││ │ ││ T (tera) │ 1,ð99,511,627,776 = 2ôð ││ │ ││ P (peta) │ 1,125,899,9ð6,842,624 = 2õð ││ │ ││ E (exa) │ 1,152,921,5ð4,6ð6,846,976 = 2öð │└──────────┴─────────────────────────────────┘

The following are some examples of the use of K,M, G, T, and E:

2,048 is expressed as 2K.4,096 is expressed as 4K.65,536 is expressed as 64K (not 65K).2òô is expressed as 16M.2óñ is expressed as 2G.2ôò is expressed as 4T.2öô is expressed as 16E.

When the words “thousand” and “million” areused, no special power-of-2 meaning is assignedto them.

All numbers in this publication are in decimalunless they are explicitly noted as being in binaryor hexadecimal (hex).

Bytes, Characters, and Codes

Although the System/360 architecture was ori-ginally designed to support the Extended Binary-Coded-Decimal Interchange Code (EBCDIC), theinstructions and data formats of the architectureare for the most part independent of the externalcode which is to be processed by the machine.For most instructions, all 256 possible combina-tions of bit patterns for a particular byte can beprocessed, independent of the character which thebit pattern is intended to represent. Forinstructions which use the zoned format, and forthose few instructions which are dependent on aparticular external code, the instruction TRANS-LATE may be used to convert data from one codeto another code. Thus, a machine operating inaccordance with z/Architecture can process

EBCDIC, ASCII, or any other code which can berepresented in eight or fewer bits per character.

In this publication, unless otherwise specified, thevalue given for a byte is the value obtained byconsidering the bits of the byte to represent abinary code. Thus, when a byte is said to containa zero, the value 00000000 binary, or 00 hex, ismeant, and not the value for an EBCDIC character“0,” which would be F0 hex.

Other Publications

The parallel-I/O interface is described in the publi-cation IBM System/360 and System/370 I/O Inter-face Channel to Control Unit Original EquipmentManufacturers' Information, GA22-6974.

The parallel-I/O channel-to-channel adapter isdescribed in the publication IBM EnterpriseSystems Architecture/390 Channel-to-ChannelAdapter for the System/360 and System/370 I/OInterface, SA22-7091.

The Enterprise Systems Connection Architecture*(ESCON*) I/O interface, referred to in this publi-cation along with the FICON I/O interface as theserial-I/O interface, is described in the publicationIBM Enterprise Systems Architecture/390 ESCONI/O Interface, SA22-7202.

The FICON I/O interface is described in the ANSIstandards document Fibre Channel - Single-ByteCommand Code Sets-2 (FC-SB-2).

The channel-to-channel adapter for the serial-I/Ointerface is described in the publication IBM Enter-prise Systems Architecture/390 ESCON Channel-to-Channel-Adapter, SA22-7203.

The commands, status, and sense data that arecommon to all I/O devices that comply withz/Architecture are described in the publication IBMEnterprise Systems Architecture/390 CommonI/O-Device Commands and Self Description,SA22-7204.

The compression facility is described in the publi-cation IBM Enterprise Systems Architecture/390Data Compression, SA22-7208. The

Enterprise Systems Connection Architecture and ESCON are trademarks of the International Business Machines Corporation.

Preface xix

z/Architecture form of the COMPRESSION CALLinstruction is described in this publication.

The interpretive-execution facility is described inthe publication IBM 370-XA Interpretive Execution,SA22-7095.

xx z/Architecture Principles of Operation

Chapter 1. Introduction

Highlights of z/Architecture . . . . . . . . . . . 1-1General Instructions for 64-Bit Integers . . 1-2Other New General Instructions . . . . . . 1-2Floating-Point Instructions . . . . . . . . . . 1-4Control Instructions . . . . . . . . . . . . . 1-4Trimodal Addressing . . . . . . . . . . . . . 1-4

Modal Instructions . . . . . . . . . . . . . 1-4Effects on Bits 0-31 of a General

Register . . . . . . . . . . . . . . . . . 1-5Extended-Translation Facility 2 . . . . . . . 1-5

The ESA/390 Base . . . . . . . . . . . . . . . 1-6

The ESA/370 and 370-XA Base . . . . . . 1-11System Program . . . . . . . . . . . . . . . . . 1-13Compatibility . . . . . . . . . . . . . . . . . . . 1-13

Compatibility among z/ArchitectureSystems . . . . . . . . . . . . . . . . . . 1-13

Compatibility between z/Architecture andESA/390 . . . . . . . . . . . . . . . . . 1-14

Control-Program Compatibility . . . . . . 1-14Problem-State Compatibility . . . . . . . 1-14

Availability . . . . . . . . . . . . . . . . . . . . 1-14

This publication provides, for reference purposes,a detailed description of z/Architecture.

The architecture of a system defines its attributesas seen by the programmer, that is, the concep-tual structure and functional behavior of themachine, as distinct from the organization of thedata flow, the logical design, the physical design,and the performance of any particular implementa-tion. Several dissimilar machine implementationsmay conform to a single architecture. When theexecution of a set of programs on differentmachine implementations produces the resultsthat are defined by a single architecture, theimplementations are considered to be compatiblefor those programs.

Highlights of z/Architecturez/Architecture is the next step in the evolutionfrom the System/360 to the System/370,System/370 extended architecture (370-XA),Enterprise Systems Architecture/370* (ESA/370),and Enterprise Systems Architecture/390(ESA/390). z/Architecture includes all of the facili-ties of ESA/390 except for the asynchronous-pageout, asynchronous-data-mover,program-call-fast, and vector facilities.z/Architecture also provides significant extensions,as follows:

Sixty-four-bit general registers and control reg-isters.

A 64-bit addressing mode, in addition to the24-bit and 31-bit addressing modes ofESA/390, which are carried forward toz/Architecture.

Both operand addresses and instructionaddresses can be 64-bit addresses. Theprogram-status word (PSW) is expanded to 16bytes to contain the larger instruction address.The PSW also contains a newly assigned bitthat specifies the 64-bit addressing mode.

Up to three additional levels of dynamic-address-translation (DAT) tables, called regiontables, for translating 64-bit virtual addresses.

A virtual address space may be specifiedeither by a segment-table designation as inESA/390 or by a region-table designation, andeither of these types of designation is calledan address-space-control element (ASCE).An ASCE may alternatively be a real-spacedesignation that causes virtual addresses tobe treated simply as real addresses withoutthe use of DAT tables.

An 8K-byte prefix area for containing largerold and new PSWs and register save areas.

A SIGNAL PROCESSOR order for switchingbetween the ESA/390 and z/Architecturearchitectural modes.

Initial program loading sets the ESA/390 archi-tectural mode. The new SIGNALPROCESSOR order then can be used to setthe z/Architecture mode or to return from

Enterprise Systems Architecture/370 is a trademark of the International Business Machines Corporation.

Copyright IBM Corp. 1990, 2000 1-1

z/Architecture to ESA/390. This order causesall CPUs in the configuration always to be inthe same architectural mode.

Many new instructions, many of which operateon 64-bit binary integers

Some of the new instructions that do not operateon 64-bit binary integers have also been added toESA/390.

All of the ESA/390 instructions, except for those ofthe four facilities named above, are included inz/Architecture.

The bit positions of the general registers andcontrol registers of z/Architecture are numbered0-63. An ESA/390 instruction that operates on bitpositions 0-31 of a 32-bit register in ESA/390operates instead on bit positions 32-63 of a 64-bitregister in z/Architecture.

General Instructions for 64-BitIntegers

The 32-bit-binary-integer instructions of ESA/390have new analogs in z/Architecture that operateon 64-bit binary integers. There are two types ofanalogs:

Analogs that use two 64-bit binary integers toproduce a 64-bit binary integer. For example,the ESA/390 ADD instruction (A for a storage-to-register operation or AR for a register-to-register operation) has the analogs AG (adds64 bits from storage to the contents of a 64-bitgeneral register) and AGR (adds the contentsof a 64-bit general register to the contents ofanother 64-bit general register). Theseanalogs are distinguished by having “G” intheir mnemonics.

Analogs that use a 64-bit binary integer and a32-bit binary integer to produce a 64-bit binaryinteger. The 32-bit integer is either sign-extended or extended on the left with zeros,depending on whether the operation is signedor unsigned, respectively. For example, theESA/390 ADD (A or AR) instruction has theanalogs AGF (adds 32 bits from storage to thecontents of a 64-bit general register) andAGFR (adds the contents of bit positions32-63 of a 64-bit general register to the con-tents of another 64-bit general register).These analogs are distinguished by having“GF” in their mnemonics.

Other New General Instructions

The other additional or significantly enhancedgeneral instructions of z/Architecture are high-lighted as follows:

ADD LOGICAL WITH CARRY and SUB-TRACT LOGICAL WITH BORROW operateon either 32-bit or 64-bit unsigned binary inte-gers and include a carry or borrow, as repres-ented by the leftmost bit of the two-bitcondition code in the PSW, in the computa-tion. This can improve the performance ofoperating on extended-precision integers (inte-gers longer than 64 bits).

AND IMMEDIATE and OR IMMEDIATEcombine a two-byte immediate operand withany of the two bytes on two-byte boundariesin a 64-bit general register.

BRANCH AND SAVE AND SET MODE andBRANCH AND SET MODE are enhanced sothat they set bit 63 of the R± general registerto one if the current addressing mode is the64-bit mode and they set the 64-bitaddressing mode if bit 63 of the R² generalregister is one. This allows “pointer-directed”linkages between programs in differentaddressing modes, including any of the 24-bit,31-bit, and 64-bit modes.

BRANCH RELATIVE AND SAVE LONG andBRANCH RELATIVE ON CONDITION LONGare like the BRANCH RELATIVE AND SAVEand BRANCH RELATIVE ON CONDITIONinstructions of ESA/390 except that the newinstructions use a 32-bit immediate field. Thisincreases the target range available throughrelative branching.

COMPARE AND FORM CODEWORD isenhanced so that, in the 64-bit addressingmode, the comparison unit is six bytes insteadof two and the resulting codeword is eightbytes instead of four. UPDATE TREE isenhanced so that, in the 64-bit addressingmode, a node is 16 bytes instead of eight andthe codeword in a node is eight bytes insteadof four. This improves the performance ofsorting records having long keys.

DIVIDE LOGICAL and MULTIPLY LOGICALprovide operations on unsigned binary inte-gers and produce either 32-bit or 64-bit quo-tients and remainders or products.

1-2 z/Architecture Principles of Operation

DIVIDE SINGLE divides a 64-bit dividend by a32-bit or 64-bit divisor and produces a 64-bitquotient and remainder. MULTIPLY SINGLEis enhanced so it can multiply a 64-bit multipli-cand by a 32-bit or 64-bit multiplier andproduce a 64-bit product.

EXTRACT PSW, extracts the entire currentPSW to allow determination of the currentmachine state, for example, determination ofwhether the CPU is in the problem state orthe supervisor state.

INSERT IMMEDIATE inserts a two-byte imme-diate operand into a 64-bit general register onany of the two-byte boundaries in the register.LOAD LOGICAL IMMEDIATE does the sameand also clears the remainder of the register.

LOAD ADDRESS RELATIVE LONG forms anaddress relative to the current (unupdated)instruction address by means of a signed32-bit immediate field.

LOAD LOGICAL THIRTY ONE BITS placesthe rightmost 31 bits of either a general reg-ister or a word in storage, with 33 zerosappended on the left, in a general register.

LOAD MULTIPLE DISJOINT loads the left-most 32 bits of each register in a range ofgeneral registers from one area in storage andthe rightmost 32 bits of each of those registersfrom another area in storage. This is for usein place of a LOAD MULTIPLE HIGH instruc-tion and a 32-bit LOAD MULTIPLE instructionwhen one of the storage areas is addressedby one of the registers loaded.

LOAD MULTIPLE HIGH and STORE MUL-TIPLE HIGH load or store the leftmost 32 bitsof each register in a range of general regis-ters, allowing augmentation of existing pro-grams that load or store the rightmost 32 bitsby means of LOAD MULTIPLE and STOREMULTIPLE. (Sixty-four-bit forms of LOADMULTIPLE and STORE MULTIPLE also areprovided.)

LOAD PAIR FROM QUADWORD and STOREPAIR TO QUADWORD operate between aneven-odd pair of 64-bit general registers and aquadword in storage (16 bytes aligned on a

16-byte boundary). These instructions providequadword consistency (all bytes appear to beloaded or stored concurrently in amultiple-CPU system). (Only the 64-bit formof COMPARE DOUBLE AND SWAP also pro-vides quadword consistency.)

LOAD REVERSED and STORE REVERSEDload or store a two-byte, four-byte, or eight-byte unit in storage with the left-to-rightsequence of the bytes reversed. LOADREVERSED also can move a four-byte oreight-byte unit between two general registers.These operations allow conversion between“little-endian” and “big-endian” formats.

PERFORM LOCKED OPERATION isenhanced with two more sets of functioncodes, with each set providing six differentoperations. One of the additional sets pro-vides operations on 64-bit operands in 64-bitgeneral registers, and the other provides oper-ations on 128-bit operands in a parameter list.

ROTATE LEFT SINGLE LOGICAL obtains 32bits or 64 bits from a general register, rotatesthem (the leftmost bit replaces the rightmostbit), and places the result in another generalregister (a nondestructive rotate).

SET ADDRESSING MODE can set any of the24-bit, 31-bit, and 64-bit addressing modes.

SHIFT LEFT SINGLE, SHIFT LEFT SINGLELOGICAL, SHIFT RIGHT SINGLE, and SHIFTRIGHT SINGLE LOGICAL are enhanced with64-bit forms that obtain the source operandfrom one general register and place the resultoperand in another general register (a nonde-structive shift).

TEST UNDER MASK HIGH and TESTUNDER MASK LOW, which are ESA/390instructions, are given the alternative nameTEST UNDER MASK, and two additionalforms are added so that a two-byte immediateoperand can be used to test the bits of twobytes located on any of the two-byte bounda-ries in a 64-bit general register. (TheESA/390 instruction TEST UNDER MASK,which uses a one-byte immediate operand totest a byte in storage, continues to be pro-vided.)

Chapter 1. Introduction 1-3

Floating-Point Instructions

The z/Architecture floating-point instructions arethe same as in ESA/390 except that instructionsare added for converting between 64-bit signedbinary integers and either hexadecimal or binaryfloating-point data. These new instructions have“G” in their mnemonics.

Control Instructions

The new or enhanced control instructions ofz/Architecture are highlighted as follows:

EXTRACT AND SET EXTENDEDAUTHORITY is a privileged instruction forchanging the extended authorization index ina control register. This enables real-spacedesignations to be used more efficiently bymeans of access lists.

EXTRACT STACKED REGISTERS isenhanced to extract optionally all 64 bits ofthe contents of one or more saved generalregisters.

EXTRACT STACKED STATE is enchanced toextract optionally the entire contents of thesaved PSW, including a 64-bit instructionaddress.

LOAD CONTROL and STORE CONTROL areenhanced for operating optionally on 64-bitcontrol registers.

LOAD PSW uses an eight-byte storageoperand as in ESA/390 and expands thisoperand to a 16-byte z/Architecture PSW.

LOAD PSW EXTENDED directly loads a16-byte PSW.

LOAD REAL ADDRESS in its ESA/390 formand in the 24-bit or 31-bit addressing modeoperates as in ESA/390 if the translation issuccessful and the obtained real address hasa value less than 2G bytes. LOAD REALADDRESS in its ESA/390 form and in the64-bit addressing mode, or in its enhancedz/Architecture form in any addressing mode,loads a 64-bit real address.

LOAD USING REAL ADDRESS and STOREUSING REAL ADDRESS are enhanced tohave optionally 64-bit operands.

STORE FACILITY LIST is a privileged instruc-tion that stores at real location 200 an indi-

cation of whether z/Architecture is installedand of whether it is active. This instruction isadded also to ESA/390 and indicates alsowhether the new z/Architecture instructionsthat have been added to ESA/390 are avail-able. Real location 200 has previously con-tained all zeros in most systems and can beexamined by a problem-state programwhether or not STORE FACILITY LIST isinstalled. The information stored at reallocation 200 also indicates whether theextended-translation facility 2 is installed.

STORE REAL ADDRESS is like LOAD REALADDRESS except that STORE REALADDRESS stores the resulting addressinstead of placing it in a register.

TRACE is enhanced to record optionally thecontents of 64-bit general registers.

Trimodal Addressing

“Trimodal addressing” refers to the ability to switchbetween the 24-bit, 31-bit, and 64-bit addressingmodes. This switching can be done by means of:

The old instructions BRANCH AND SAVEAND SET MODE and BRANCH AND SETMODE. Both of these instructions set the64-bit addressing mode if bit 63 of the R²general register is one. If bit 63 is zero, theinstructions set the 24-bit or 31-bit addressingmode if bit 32 of the register is zero or one,respectively.

The new instruction SET ADDRESSINGMODE (SAM24, SAM31, and SAM64). Theinstruction sets the 24-bit, 31-bit, or