principles of computer architecture appendix a: digital

Appendix A - Digital Logic

© 1999 M. Murdocca and V. Heuring

itionscircuit in which logical ombinations of the inputs.

decisions are made based ts as well as the past

it. has an internal state, and

h current inputs and its ne controller.



l Logic Unitt of outputs according to

ally have two distinct 0, 0 and 1, or 5 v. and 0 v.

nctions of the inputs, and ly after the inputs change. A o the CLU, which produces ing functions f0 – fm

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocc

A.1 IntroductionA.2 Combinational LogicA.3 Truth TablesA.4 Logic GatesA.5 Properties of Boolean

AlgebraA.6 The Sum-of-Products Form,

and Logic DiagramsA.7 The Product-of-Sums FormA.8 Positive vs. Negative LogicA.9 The Data SheetA.10 Digital Components

A.11 Sequential LogicA.12 Design of Finite St

MachinesA.13 Mealy vs. Moore MA.14 RegistersA.15 Counters

a and V. Heuring

ate

achines

Principles of Computer Architecture by M. Murdocca and V. Heuring

one or more mapping functions. • Inputs and outputs for a CLU norm

(binary) values: high and low, 1 andfor example.

• The outputs of a CLU are strictly futhe outputs are updated immediateset of inputs i0 – in are presented ta set of outputs according to mapp

A-1 Appendix


Principles of Computer ArchitecMiles Murdocca and Vincent Heuring

Appendix A: Digital Logic

A-2 Appendix

Chapter Contents

A - Digital Logic

a and V. Heuring

ture

A - Digital Logic

A-3


Some Defin• Combinational logic: a digital logic

decisions are made based only on ce.g. an adder.

• Sequential logic: a circuit in which on combinations of the current inpuhistory of inputs. e.g. a memory un

• Finite state machine: a circuit whichwhose outputs are functions of botinternal state. e.g. a vending machi

A-4

The Combinationa• Translates a set of inputs into a se



g All Possible nary Variables

have names: AND, XOR, use upper case spelling.)



eir Symbols

”te when drawing AND vs. OR.)


• Logically identical truth table to the original (see previslide), if the switches are configured up-side down.

a and V. Heuring

ous


• Note the use of the “inversion bubble.• (Be careful about the “nose” of the ga

Logic symbols for AND, OR, buffer, and NOT Boolean functions

A-5 Appendix


Truth Tables• Developed in 1854 by George Boole• further developed by Claude Shannon (Bell Labs)• Outputs are computed for all possible input combinati

(how many input combinations are there?Consider a room with two light switches. How must they work†

†Don't show this to your electrician, or wire your house this way. Tdefinitely violates the electric code. The practical circuit never leavto the light "hot" when the light is turned off. Can you figure how?

A-6 Appendix

Alternate Assignments of OutpuSwitch Settings

A - Digital Logic

a and V. Heuring

ons

?

his circuit es the lines

A - Digital Logic

ts to

A-7


Truth Tables ShowinFunctions of Two Bi

• The more frequently used functionsOR, NOR, XOR, and NAND. (Always

A-8

Logic Gates and Th



ansistor Level

tor Used erter

Inverter TransferFunction



in Transistor-ic (TTL)

a and V. Heuring Principles of Computer Architecture by M. Murdocca and V. Heuring
A-9 Appendix


Logic symbols for NAND, NOR, Xand XNOR Boolean function

A-10 Appendix

Variations of Basic Logic GatSymbols

A - Digital Logic

a and V. Heuring

OR, s

A - Digital Logic

e

A-11


The Inverter at the Tr

Transistor Symbol

PowerTerminals A Transis

as an Inv

A-12

Allowable Voltages Transistor-Log



s of Boolean

Postulates

Theorems

A, B, etc. are Literals; 0 and 1 are constants.

Principle of duality: The dual of a Boolean function is gotten by replacing AND with OR and OR with AND, constant 1s by 0s, and 0s by 1s

Postulat



heorem

“pushing the bubbles,”

Discuss: Applying DeMorgan’s theorem byand “bubble tricks.”

A-13 Appendix


Transistor-Level Circuits Fo2-Input a) NAND and b)NOR Ga

A-14 Appendix

Tri-State Buffers• Outputs can be 0, 1, or “electrically disconnected.”

A - Digital Logic

a and V. Heuring

rtes

A - Digital Logic

A-15


The Basic PropertieAlgebra

A-16

DeMorgan’s T



Circuit that ority Function

the Gate Count?



it Intersections


• The SOP form for the 3-input majority gate is:

• M = ABC + ABC + ABC + ABC = m3 + m5 +m6 +m7 = Σ• Each of the 2n terms are called minterms, running from 0

• Note the relationship between minterm number and boole• Discuss: common-sense interpretation of equation.

a and V. Heuring

(3, 5, 6, 7)to 2n - 1

an value.


A-17 Appendix


The Sum-of-Products (SOP) Fo

• Transform the function into a two-level AND-OR equa• Implement the function with an arrangement of logic g

from the set {AND, OR, NOT}• M is true when A=0, B=1, and C=1, or when A=1, B=0,

and so on for the remaining cases.• Represent logic equations by using the sum-of-produ

form

Fig. A.15—Truth Table for The Majority Function

A B C FMinterm

Index

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

0

1

2

3

4

5

6

7

1

0

0-side 1-s

0

A balance tips to the right depending on w

there are more 0’s o

A-18 Appendix

The SOP Form of the Majority G

A - Digital Logic

a and V. Heuring

rm

tionates

and C=1,

cts (SOP)

ide

left or hether r 1’s.

A - Digital Logic

ate

A-19


A 2-Level AND-ORImplements the Maj

Discuss: What is

A-20

Notation Used at Circu



Logic (Cont’d.)



onents

normally made using as components, rather e majority function can be

tes) in an integrated circuit

gates. to 1000 gates.0,000 logic gates.0,000-upward.e distinctions are useful inf circuits.omponents:


•Negative logic: truth, or assertion is represented by logic 0 , lower vfalsity, de- or unassertion, logic 1, is represented by lower voltage

a and V. Heuring

oltage;


• High level digital circuit designs arecollections of logic gates referred tothan using individual logic gates. Thviewed as a component.

• Levels of integration (numbers of ga(IC):

• Small scale integration (SSI): 10-100• Medium scale integration (MSI): 100• Large scale integration (LSI): 1000-1• Very large scale integration (VLSI): 1• These levels are approximate, but th

comparing the relative complexity o• Let us consider several useful MSI c

A-21 Appendix


A 2-Level OR-AND Circuit thaImplements the Majority Funct

A-22 Appendix

Positive vs. Negative Logic•Positive logic: truth, or assertion is represented by logic 1, higher vofalsity, de- or unassertion, logic 0, is represented by lower voltage.

A - Digital Logic

a and V. Heuring

t ion

A - Digital Logic

ltage;

A-23


Positive and Negative

A-26

Digital Comp



jority Function Mux

elected minterms of the function.



g a 4-1 Mux to rity Function

lect a pair of minterms. The ted from {0, 1, C, C} to pick ir.

Principle: Use the A and B inputs to sevalue applied to the MUX input is selecthe desired behavior of the minterm pa

A-27 Appendix


4 to 1 MUX

A-28 Appendix

The Multiplexer

A - Digital Logic

a and V. Heuring

A - Digital Logic

A-29


Implementing the Mawith an 8-1

Principle: Use the mux select to pick out the s

A-30

More Efficiency: UsinImplement the Majo



Implement the ction



ncoders into a binary encoding, f a decoder. on the inputs.


Compare toFig A.29


• Can be thought of as the converse o• A priority encoder imposes an order• Ai has a higher priority than Ai+1

A-31 Appendix


The Demultiplexer (DEMUX)

A-32 Appendix

The Demultiplexer is a Decoder an Enable Input

A - Digital Logic

a and V. Heuring

A - Digital Logic

with

A-34


Using a Decoder to Majority Fun

A-35

The Priority E• An encoder translates a set of input



ment an Adder



A Realization of a Full Adder

A-36 Appendix


Programmable Logic Arrays (PLA

• A PLA is a customizable AND matrix followed by a customizable OR matrix:

A-37 Appendix

Using a PLA to Implement the MaFunction

A - Digital Logic

a and V. Heuring

s)

A - Digital Logic

jority

A-38


Using PLAs to Imple

A-39

A Multi-Bit Ripple-Carry Adder

PL



mped Delay

ut (which is lumped at the s at the basis of the element, the flip-flop.



h

itive logic) device.


• An FSM is composed of a combinational logic unit and delay elements (called flip-flops) in a feedback path, which maintains state information.


• The S-R latch is an active high (pos

A-40 Appendix


Sequential Logic

• The combinational logic circuits we have been studyinghave no memory. The outputs always follow the inputs.

• There is a need for circuits with memory, which behavedifferently depending upon their previous state.

• An example is a vending machine, which must remembmany and what kinds of coins have been inserted. The mshould behave according to not only the current coin insebut also upon how many and what kinds of coins have beinserted previously.

• These are referred to as finite state machines, because have at most a finite number of states.

A-41 Appendix

Classical Model of a Finite StaMachine

A - Digital Logic

a and V. Heuring

so far

er how achine rted, en

they can

A - Digital Logic

te

A-42


NOR Gate with Lu

• The delay between input and outpoutput for the purpose of analysis) ifunctioning of an important memory

A-43

S-R Latc



he Clock Paces m

n” happens when the clock clock cycle allows eir inputs settle at the high.



efixes024. For everything else, ise for 1M, 1G, etc.


• It is desirable to be able to “turn off” the latch so it doesrespond to such hazards.

a and V. Heuring

not


like clock speeds, 1K = 1000, and likew

A-44 Appendix


NAND Implementation of S-R L

A-45 Appendix

A Hazard

A - Digital Logic

a and V. Heuring

atch

A - Digital Logic

A-46


A Clock Waveform: Tthe Syste

• In a positive logic system, the “actiois high, or positive. The low part of thepropagation between subcircuits, so thcorrect value when the clock next goes

A-47

Scientific Pr• For computer memory, 1K = 210 = 1



lip-Flop

w data into the master, ous data. The falling edge into the slave.



Latch S=R=1 problem of the S-R

bles K, and vice-versa.oes momentarily to 1 and d in the reset state, the latch1’s catching.”de) addresses this problem.


• The clocked D latch, has a potential problem: If D changthe clock is high, the output will also change. The Master-flip-flop (next slide) addresses this problem.

a and V. Heuring

es while Slave


latch, because Q enables J while Q’ disa• However, there is still a problem. If J gthen back to 0 while the latch is active anwill “catch” the 1. This is referred to as “• The J-K Master-Slave flip-flop (next sli

A-48 Appendix


Clocked S-R Latch

• The clock signal, CLK, enables the S and R inputs to the

A-49 Appendix

Clocked D Latch

A - Digital Logic

a and V. Heuring

latch.

A - Digital Logic

A-50


Master-Slave F

• The rising edge of the clock loads newhile the slave continues to hold previof the clock loads the new master data

A-51

Clocked J-K• The J-K latch eliminates the disallowed



red D Flip-Flop



-4 Counter RESET input.ke on values of 00, 01, 10,


• The presence of a constant 1 at J and K means that the fwill change its state from 0 to 1 or 1 to 0 each time it is clothe T (Toggle) input.

a and V. Heuring

lip-flop cked by


• Counter has a clock input (CLK) and a• Counter has two output lines, which taand 11 on subsequent clock cycles.

A-52 Appendix


Master-Slave J-K Flip-Flop

A-53 Appendix

Clocked T Flip-Flop

A - Digital Logic

a and V. Heuring

A - Digital Logic

A-54


Negative Edge-Trigge• When the clock is high, the two input latches output 0, so the Main latch remains in its previous state, regardless of changes in D.• When the clock goes high-to-low, values in the two input latches will affect the state of the Main latch.• While the clock is low, D cannot affect the Main latch.

A-55

Example: Modulo



Mod-4 Counter



d-4 Counter

A-56 Appendix


State Transition

Diagram for Mod-4

Counter

A-57 Appendix

State Table for Mod-4 Counte

A - Digital Logic

a and V. Heuring

A - Digital Logic

r

A-58


State Assignment for

A-59

Truth Table for Mo



ce Detector

ts a 1 when exactly two of

uces an output sequence of

. diagram (next slide).



tate Transition


used to toggle the input of the next flip-flop when its outpu

a and V. Heuring

t is 1.


• Design a machine that outputs a 1 when exactly two of the last three inputs are 1.

A-60 Appendix


Logic Design for Mod-4 Count

A-73 Appendix

Modulo-8 Counter• Note the use of the T flip-flops, implemented as J-K’s. Th

A - Digital Logic

a and V. Heuring

er

A - Digital Logic

ey are

A-61


Example: A Sequen

• Example: Design a machine that outputhe last three inputs are 1.• e.g. input sequence of 011011100 prod001111010.• Assume input is a 1-bit serial line.• Use D flip-flops and 8-to-1 Multiplexers• Start by constructing a state transition

A-62

Sequence Detector SDiagram



ogic Diagram



ng Machineer

for a vending machine ach), dimes (10 cents each),

value of the money inserted hine vends the item and transaction.

• Example: Design a finite state machinecontroller that accepts nickels (5 cents eand quarters (25 cents each). When the equals or exceeds twenty cents, the macreturns change if any, and waits for next• Implement with PLA and D flip-flops.

A-63 Appendix


Sequence Detector State Tab

A-64 Appendix

Sequence Detector State Assign

A - Digital Logic

a and V. Heuring

le

A - Digital Logic

ment

A-65


Sequence Detector L

A-66

Example: A VendiControll



ne Controller



nterf Inputs and Present State.chines, in which next state puts.f Present State only.

• Previous FSM designs were Mealy Mawas computed from present state and in• Moore Model: Outputs are functions o

A-67 Appendix


Vending Machine State TransitDiagram

A-68 Appendix

Vending Machine State Table aState Assignment

A - Digital Logic

a and V. Heuring

ion

A - Digital Logic

nd

A-69


PLA Vending Machi

A-70

Moore Cou• Mealy Model: Outputs are functions o

A - Digital Logic

a and V. Heuring

an gang

A-72 Appendix A - Digital Logic

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring

Left-Right Shift

Register with

Parallel Read and

Write

A-71 Appendix


Four-Bit Register• Makes use of tri-state buffers so that multiple registers ctheir outputs to common output lines.

principles of computer architecture appendix a: digital

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