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Amplifier

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MOS as two port network

D

G

S

In

Out

VSS

𝐼𝐷 =1

2𝜇𝐶𝑜𝑥

𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑇𝐻

2 1 + 𝑉𝐷𝑆 ≈

≈1

2𝜇𝐶𝑜𝑥

𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑇𝐻

2

ro

vin + -

vout gmvGS

vGS

Small signal model 𝑇𝑟𝑎𝑛𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑎𝑛𝑐𝑒 𝑔𝑚 =𝑑𝐼𝐷𝑑𝑉𝐺𝑆

𝐴

𝑉=1

𝐷𝑦𝑛𝑎𝑚𝑖𝑐 𝑟𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 𝑟0 =𝑑𝐼𝐷

𝑑𝑉𝐷𝑆

−1

𝑉

𝐴=

𝐹𝑙𝑢𝑐𝑡𝑎𝑡𝑖𝑜𝑛 𝑜𝑓 𝐼𝐷 𝑑𝐼𝐷 = 𝑔𝑚𝑑𝑉𝐺𝑆 𝑖𝐷 = 𝑔𝑚𝑣𝐺𝑆

5 grudnia 2013 4

MOS as two port network

D

G

S

In

Out

VSS

𝐼𝐷 =1

2𝜇𝐶𝑜𝑥

𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑇𝐻

2 1 + 𝑉𝐷𝑆 ≈

≈1

2𝜇𝐶𝑜𝑥

𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑇𝐻

2

ro

vin + -

vout

vGS

gmvGS

Small signal model

If VGS = constant MOS delivers quasi constant current MOS is working as source current

𝑟0 =𝑑𝐼𝐷𝑑𝑉𝐷𝑆

−1

=1

12𝜇𝐶𝑜𝑥

𝑊𝐿𝑉𝐺𝑆 − 𝑉𝑇𝐻

2≈1

𝐼𝐷

𝑉𝐺𝑆 = 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡 ⇒ 𝑑𝑉𝐺𝑆 = 𝑣𝐺𝑆 = 0 ⇒ 𝑖𝐷 = 𝑔𝑚𝑣𝐺𝑆 = 0

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MOS as two port network

D

G

S

In

Out

VSS

𝐼𝐷 =1

2𝜇𝐶𝑜𝑥

𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑇𝐻

2 1 + 𝑉𝐷𝑆 ≈

≈1

2𝜇𝐶𝑜𝑥

𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑇𝐻

2

ro

vin + -

vout gmvGS

vGS

Small signal model

If VGS = VDS MOS (connected as diode) is working as active load (resistor)

𝒓𝑳 =𝑑𝑉𝐷𝑆𝑑𝐼𝐷=𝑑𝑉𝐺𝑆𝑑𝐼𝐷=1

𝑔𝑚

1𝑔𝑚

RD = 1M

RD = 5k

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One Stage Amplifier

RD = 10k

RD = 100k

V in

VSS

RD

D

S

VDD

ID

V out

7

One Stage Amplifier

𝐼𝐷 =1

2𝜇𝐶𝑜𝑥

𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑇𝐻

2 𝐼𝐷 = 𝜇𝐶𝑜𝑥

𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑇𝐻 𝑉𝐷𝑆 −

𝑉𝐷𝑆2

2

𝑟0 = 0 𝑟0 =1

𝜇𝐶𝑜𝑥𝑊𝐿𝑉𝐺𝑆 − 𝑉𝑇𝐻 − 𝑉𝐷𝑆

8

One Stage Amplifier

𝐼𝐷 =1

2𝜇𝐶𝑜𝑥

𝑊

𝐿𝑉𝐺𝑆 − 𝑉𝑇𝐻

2 1 + 𝑉𝐷𝑆

} ~1,01

𝑟0 ≈1

𝐼𝐷 𝑟0 =

1

𝜇𝐶𝑜𝑥𝑊𝐿𝑉𝐺𝑆 − 𝑉𝑇𝐻 − 𝑉𝐷𝑆

5 grudnia 2013 9

Offset voltage (DC) shifts the signal (AC) on desidered level

One Stage Amplifier

Out

VSS

VDD

R2

R1 RD ID

In

𝑉𝐺𝑆 =𝑅2

𝑅1 + 𝑅2𝑉𝐷𝐷

𝑈 = 𝐶𝑜𝑛𝑠𝑡 = 𝑅𝐼 0 =⇒ 𝑅 = 𝑡𝑔𝛼 = 0

D

G

S

In

Out

VSS

VDD

RD

The VDD supply voltage acts as an AC ground because its value remains constant with time.

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One Stage Amplifier

The pMOS transistor can replace RD– is working as so called active resistance

D

G

S

In

Out

VSS

RD

VDD

D

G

S

In

Out

VSS

VDD

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Gain A is proportional to the load resistance RLoad and transconductance gm

One Stage Amplifier

Gain calculation:

𝐴𝑉 =𝑣𝑜𝑢𝑡

𝑣𝑖𝑛

= −d𝑖𝐷∙𝑅𝐷

d𝑣𝐺𝑆

= −𝑔𝑚 ∙ 𝑅𝐷

Out

VSS

VDD

R2

R1 RD ID

In

13

Current Sources

A MOSFET behaves as a current source , when it is in saturation mode.

NMOS draws current from a point to ground (sinks current), whereas PMOS draws current from VDD to a point (sources current).

NMOS or PMOS devices configured as shown above operate as current sources

X

VSS

ID Vb

Y

VDD

ID Vb

𝐼𝐷 =𝛽

2𝑉𝑏 − 𝑉𝑇

2 𝐼𝐷 =𝛽

2𝑉𝐷𝐷 − 𝑉𝑏 − 𝑉𝑇

2

14

Current Sources

NMOS or PMOS devices configured as shown above do not operate as current sources because variation of VX or VY directly changes the gate-source voltage of each transistor, thus changing the drain current considerably.

X

VSS

ID Vb

Y

VDD

ID Vb

15

Common-Source Stage

Common-source stage is when the input is applied to the gate and the output at the drain. Source is the common pin for input and output. For small signals, M1 converts the input voltage variations to proportional drain current changes, and RD transforms the drain currents to the output voltage. The VDD supply voltage acts as an AC ground because its value

remains constant with time. Thus, we simply “ground” the supply voltage in small-signal analysis.

vout

VSS

VDD

RD

ID

vin

RD vin

+ -

vout

gmv1

v1

small signals model

r0

16

Common-Source Stage

If channel-length modulation is neglected =0 , the small-signal model yields vin = v1 and vout = −gmv1RD, where The voltage gain of the common-source stage is

DDoxnv

Dm

in

outv

RIL

WCA

Rgv

vA

2

Doxnm IL

WCg 2

Vout

VSS

VDD

RD

ID

Vin

RD vin

+ -

vout

gmV1 v1

small signals model

17

CS Stage with =0

The output impedance of the CS amplifier is simply equal to load

resistance RL. The voltage gain Av is equal

Lmv RgA

RL vin

+ -

vx gmV1 v1

+ -

ix

18

CS Stage with 0

However, channel length modulation affects CS stages as drain current is also a weak function of VDS, for small-signal can be calculated resistance r0

OLout

in

OLmv

rRR

R

rRgA

||

||

DTHGSoxn

DS

Do

IVVL

WCV

Ir

1

2

1

1

2

1

RL vin

+ -

vx gmV1 v1

+ -

ix

ro

19

CS Stage with Current-Source Load

Frequently an active current-source load is used. Because v1= 0 the gm2v1=0.

This is advantageous because a current-source has a high output resistance and can tolerate a small voltage drop across it.

21

211

||

||

OOout

OOmv

rrR

rrgA

Vout

VSS

VDD

ID

Vin

Vb + -

v1

r02

Vout

Vin r01

gm2v1

20

PMOS CS Stage with NMOS as Load

Similarly, with PMOS as input stage and NMOS as the load, the voltage gain is the same as before. Transistor M2 generates a small-signal current equal to gm2vin

)||(212 OOmv

rrgA Vout

VSS

VDD

ID

Vin

Vb

21

CS Stage with Diode-Connected Load

Doxnm IL

WCg 2

We may use a diode-connected MOSFET as the drain load.

With λ = 0, M2 acts as a small-signal resistance equal to 1/gm2

More accurate expression take channel-length modulation into account:

Vout

VSS

VDD

ID

Vin

1/gm2 r02

Vout

Vin r01

𝑟𝐿 =𝑑𝑣𝐷𝑆𝑑𝑖𝐷=𝑑𝑣𝐺𝑆𝑑𝑖𝐷=1

𝑔𝑚

𝐴𝑣 = −𝑔𝑚1 ∙ 𝑟𝐿 = −𝑔𝑚1 ∙1

𝑔𝑚2 𝐴𝑣 = −

𝑊1𝐿1𝑊2𝐿2

𝐴𝑣 = −𝑔𝑚1 ∙ 𝑟𝐿 = −𝑔𝑚11

𝑔𝑚2| 𝑟02 |𝑟01

22

CS Stage with Degeneration

When a CS stage is degenerated, its gain, I/O impedances, and linearity change. The degeneration resistor sustains a fraction of the input voltage

change.

What happend if we put RS resistance between source and ground?

𝑣𝑖𝑛 = 𝑣1 + 𝑔𝑚𝑣1𝑅𝑆 𝑣1 =𝑣𝑖𝑛

1+𝑔𝑚𝑅𝑆

Vout

VSS

VDD

RD

ID

Vin

RS

RD vin

+ -

vout

gmV1 v1

RS

23

CS Stage with Degeneration

Since gmv1 flows through RD, vout= −gmv1RD and vin = v1(1 + gmRs)

What happend if we put RS resistance between source and ground?

Vout

VSS

VDD

RD

ID

Vin

RS

RD vin

+ -

vout

gmV1 v1

RS

𝐴𝑣 =𝑣𝑜𝑢𝑡𝑣𝑖𝑛= −

𝑔𝑚𝑅𝐷1 + 𝑔𝑚𝑅𝑆

= −𝑅𝐷

𝑅𝑆 +1𝑔𝑚

24

Example of CS Stage with Degeneration

Transistor M2 serves as a diode-connected device, presenting an impedance of 1/gm2. The gain is calculated if RS is replaced with 1/gm2:

21

11

mm

Dv

gg

RA

Compute the voltage gain of the circuit if λ = 0.

A diode-connected device degenerates a CS stage.

Vout

VSS

VDD

RD

ID

Vin

Vout

VSS

VDD

RD

ID

Vin

1/gm2

25

CS Core with Biasing

Degeneration is used to stabilize bias point, and a bypass capacitor can be used to obtain a larger small-signal voltage gain at the frequency of interest.

S

m

D

G

v

Rg

R

RRR

RRA

1||

||

21

2121 ||RRR in

Such a circuit no longer exhibits an infinite input impedance

Dm

G

v RgRRR

RRA

21

21

||

||

Vout

VSS

VDD

R2

R1 RD

RS

ID

Vin

Vout

VSS

VDD

R2

R1 RD

RS

ID

Vin

Vout

VSS

VDD

R2

R1 RD

RS

ID

Vin

RG

C2

S

m

Dv

Rg

RA

1

Source follower

27

Source Follower Stage

1v

A

If the gate voltage of M1 is raised by a small amount, Vin, the gate-source voltage tends to increase, thereby raising the source current and hence the output voltage. Thus, Vout “follows” Vin. Since the dc level of Vout is lower than that of Vin by VGS, we say the follower can serve as a “level shift” circuit. We expect this topology to exhibit a subunity gain

Vout

VSS

VDD

ID

vin

RL

28

Source Follower Core

The voltage gain is therefore positive and less than unity. It is desirable to maximize RL (and rO).

The source follower can be analyzed as a resistor divider.

LO

m

LO

in

outV

Rrg

Rr

v

vA

||1

||

LOmout Rrvgv ||1

outin vvv 1

resistor divider

r0 vin

+ -

gmV1 v1

RL vout vin

+ -

1/gm

RL||r0

vout

29

Source Follower Example

In this example, M2 acts as a current source.

If rO1||rO2 » 1/gm1, then Av ≈ 1.

21

1

21

||1

||

OO

m

OO

v

rrg

rrA

Vout

VSS

VDD

ID

vin

Vb

Vout

vin

r02

r01

30

Source Follower with Biasing

RG sets the gate voltage to VDD, whereas RS sets the drain current.

The quadratic equation above can be solved for ID.

22

1THSDDDoxnD VRIV

L

WCI

GSSDDD VRIV

Vout

VSS

VDD

vin

RL

RG C1

C2

31

Supply-Independent Biasing

If Rs is replaced by a current source, drain current ID becomes independent of supply voltage.

Vout

VSS

VDD

vin

RG C1

C2 Vout

VSS

VDD

Vin

RG C1

C2

Vb

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Differential

Amplifier

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The differential pair is composed of two equal transistors. The goal of the differential amplifier is to compare two analog signals, and to

amplify their difference.

Current mirror 1:1

nMOS differential pair

Differential Amplifier

Vout+

VSS

VDD

V- V+

Vout-

ID ID

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Vout = Vout+ - Vout- = K(Vin+ - Vin -)

Usually, the gain K is high, ranging from 10 to 1000. The consequence is that the differential amplifier output saturates very rapidly, because of the supply

voltage limits.

Current mirror 1:1

nMOS differential pair

In-

In+ Out

Differential Amplifier

Vout

VSS

VDD

V- V+

ID ID

5 grudnia 2013 35

If one input is set to reference voltage, the out amplified the difference of input with respect to reference voltage

Vout

VSS

VDD

Vin

Vref

Reference voltage stage

nMOS differential pair

ID ID

In-

In+ Out

Differential Amplifier

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Differential Amplifier

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Differential Amplifier